General Sith Chart Matching Table of Contents I. General Ipedance Matching II. Ipedance Transforation for Power Aplifiers III. Ipedance Matching with a Sith Chart IV. Inputs V. Network Eleents VI. S-Paraeter Frequency Response VII. Copyright Inforation
General Ipedance Matching This worksheets discusses in detail graphical ipedance atching with a Sith chart. A few notes on atching networks before we start: Matching networks have two ain purposes. The first is to deliver allow the axiu power transfer fro a source in series with a source ipedance of Z S to a load ipedance Z L. The second is to provide a desired ipedance to a circuit to achieve other desired characteristics, such as to filter, to aintain a desired filter transfer characteristics, to an LNA to provide a low noise figure, or to a transiission line to reduce reflections. Here the atching networks are designed for narrowband networks, such as RF transitters and receivers, but not broadband applications, such as audio applications, cable odes, backplanes, ethernet, etc. Let's start with the available source power and load power definitions: V Srs V Lrs Z L P S = P L = V Lrs = V Srs R S R L Z S + Z L The power gain of the network is a found by dividing the expression for the output power divided by the input power. P L Z L RS R L + X L R G p = = S = P S Z S + Z L R L ( R S + R L ) + ( X L + X S ) R L To optiize the power gain for a given load ipedance the derivative of power gain with respect to the source resistance and reactance is set to zero, and the source ipedance is solved. This is easiest done in a two step process by first finding the optial source reactance, d G p dx S The source resistance can be found siilarly with =, which gives an optial source reactance of: X Sopt d G p dr S = X L R Sopt = R L =, giving an optial source resistance of: This ipedance is also said to give zero power reflection. That is all of the power is transferred to the load, and none is reflected back to source. When viewing the power signals as waves it is difficult to view a reflection, when the atching network consists of discrete eleents. When studying distributed structures, such as transission lines, we see the find that zero reflection occurs for true atched line and load ipedance (not conjugate). So if you are delivering power fro a source through an input atching network, through a transission line, through an output atching network, and finally to a load, how is that you can provide axiu power delivery to the load with a conjugate atch, but have zero reflections? The answer is: "You can't, " because this situation does not occur in practice. In practice in order for a transission line to have an iaginary characteristic ipedance it ust be lossy. Ipedance Transforation for Power Aplifiers Careful! Output networks for power aplifiers are ore coonly "ipedance transforation" networks rather than "ipedance atching" networks. The goal of a power aplifier is to efficiently transfer power fro a DC power supply to a load at an RF frequency; however an ipedance atching network provides axiu power transfer fro an RF source to a load. In turns out the two are the sae for output powers less than (V DD -V DSsat ) //R L, which is around W for a oh load and 3V supply. For powers above this, the load is transfored to an ipedance, seen fro the power aplifier, which is uch lower than the output ipedance of the PA.
Ipedance Matching with a Sith Chart I a personally not a big fan of sith charts, but they have soe historical value, are coonly used in network analyzers, and they allow you to plot infinite change in ipedance in a finite area. Here we describe a coon older ethod for graphically atching a coplex source ipedance to a coplex load ipedance is using a Sith chart. useful functions and identities Units Constants Inputs Z L := oh + j 3oh Z S := oh + j.oh f := 9MHz Z := Ω Reference ipedance for S paraeters Step : The source and load ipedances are converted to reflection coefficients and placed on the sith chart. One of the two ipedances is conjugated, so that a conjugate atch is achieved. Here we arbitrarily choose the source to be the conjugated ipedance. Z S Z Γ S := Z S + Z Γ S = Load ipedance Source ipedance Frequency Γ S = 9.994 ω := π f Γ L := Z L Z Z L + Z Γ L =.3 Γ L =.99 3
Step -: Starting with a source ipedance we can gradually add series or parallel eleents to provide the necessary atch and frequency response. Using the following syntax: sp: series or parallel: s=series, p=parallel (shunt) LCtype: eleent type: R=resistance, C=capacitance, L=inductance, T=transission line LC: eleent value: unitless value for ohs, farads, henries, or characteristic ipedance in ohs. g*l: propagation constant: if a transission line Z end : end ipedance of a shunt transission line: usually zero or infinity. In the following exaple we use all the possible eleents for illustration Network Eleents Shunt Inductors: For parallel inductors, a segent is plotted, which starts with the previous ipedance and sweeps the inductance down fro infinity to the specified value. nh LCtype := "L" sp := "p" LC := H Series Capacitors: For series capacitors, a segent is plotted, which starts with the previous ipedance and sweeps the capacitance fro to the specified value. pf LCtype := "C" sp := "s" LC := F Shunt Capacitors: For parallel capacitors, a segent is plotted, which starts with the previous ipedance and sweeps the capacitance fro to the specified value. pf LCtype := "C" sp := "p" LC := 3 3 3 F Series Resistors: For series resistors, a segent is plotted, which starts with the previous ipedance and sweeps the resistance fro to the specified value..ω LCtype := "R" sp := "s" LC := 4 4 4 Ω Shunt Resistors: For parallel resistors, a segent is plotted, which starts with the previous ipedance and sweeps the resistance fro infinity to the specified value. C R L C Ω LCtype := "R" sp := "p" LC := Ω R Shorted Shunt Transission Lines: For shorted shunt transission lines (which look like shunt inductors), a segent is plotted, which starts with the previous ipedance and sweeps in the electrical length (j*γ*len) fro π/ (which akes the line look like an open) down to the specified value. R_l oh := G_l := C_l pf.nh := L_l := Z end := Ω oh R_l + j ω L_l LCtype := "T" sp := "p" LC := len :=. LC = G_l + j ω C_l Ω ( G_l j ω 4 ) l, Z γl := R_l + j ω L_l + C_l len γl =.i
( G_l j ω ) γl := R_l + j ω L_l + C_l len γl =.i Open Shunt Transission Line: For open shunt transission lines (which look like shunt capacitors), a segent is plotted, which starts with the previous ipedance and sweeps in the length fro to the specified value. oh R_l := G_l := C_l pf.nh := L_l := Z end := Ω oh R_l + j ω L_l len := µ LCtype := "T" sp := "p" LC := LC = G_l + j ω C_l Ω Series Inductors: ( G_l j ω ) γl := R_l + j ω L_l + C_l len γl =.3i 4 Series Transission Line: For series transission lines, a segent is plotted, which starts with the previous ipedance and sweeps in the length fro to the specified value. R_l oh := G_l := C_l pf.nh := L_l := oh LCtype := "T" R_l + j ω L_l sp := "s" LC := len := 4 LC = G_l + j ω C_l Ω ( G_l j ω ) γl := R_l + j ω L_l + C_l len γl =.i For series inductors, a segent is plotted, which starts with the previous ipedance and sweeps the inductance fro to the specified value. l, Z l, Z LCtype := "L" sp := "s" LC :=. nh 9 9 9 H L Overall Circuit Scheatic As you add or reove circuit eleents above the following picture will update to reflect the actual scheatic. Iages Q and VSWR contours Curve Generation Grid "p" "L" "s" "C" 3 "p" "C" 4 "s" "R". = sp = "p" LCtype = "R" LC = "p" γl = Z "T" end =.i "p" "T".3i "s" "T" 4 9 "s" "L".i 3 4 9 Ω
9 "s" "L".i 9 9 Q = 3 Q = 4 Q = Q = 3 33 ML =...3.4 db 4 3 GridY GridZ Source Ipedance Load Conjugate Constant Q Contour Constant VSWR Contours Matching Eleents
S Paraeter Frequency Response S-paraeter is an abbreviation for scattering paraeters. S-paraeters are a easure of the power gain of a network. The ter scattering coes fro the concept of a cue ball scattering other balls as it transfers power to the. S ij is the easure of power gain fro port j to port i. Specifically, the square root of power gain. For exaple, S, the ost useful S-paraeter, is the easure of the ratio of output power to the available input power. This is an iportant sentence. This sentence is used to perfor hand calculations. The output power is easy to explain, it is V Ors /R L. The available input power is trickier to explain. Available input power is the axiu power that can be delivered fro a source. For a source ipedance of R S, and a source voltage of V Srs ; the available input power is (V Srs /) /R S. Why, because axiu power is delivered is to a resistance of R S. Thus a voltage division of two for the voltage, when delivering axiu available power. Thus the power gain of a network, S, is found by dividing the two powers *V o /V S *sqrt(r S /R L ). S-paraeters are ost conveniently calculated by converting an ipedance or adittance atrix into a S-paraeter atrix. So we start by finding the adittance (Y) paraeters for the lowpass L atching network. Adittance (Y) paraeters are found by driving a port with a voltage source, shorting the rest, and easuring the current at all the ports. ABCD( ω) := ABCD prev for.. ( length( LC) ) Zx if LCtype = "C" j ω LC F Ω H Zx j ω LC if LCtype = "L" Ω Zx LC if LCtype = "R" Z end + LC Ω tanh γl Zx LC if LCtype = "T" LC Ω + Z end tanh( γl ) Zx ABCDx if ( sp = "s" ) ( LCtype "T" ) ABCDx if sp = "p" Zx cosh γl LC sinh γl ( ) ABCDx if sp = "s" sinh( γl ) cosh( γl ) LC ABCD ABCDx ABCD prev ABCD prev ABCD ABCD LCtype "T" ( = ) ABCD to S paraeter conversion with a coon ipedance on all ports using this expression fro "Microwave Engineering" by Pozar. := A ABCD, ABCDS ABCD, Z B ABCD,
C ABCD, D ABCD, A + B Ω C Z + + D Z Ω A + B Ω C Z D Z Ω ( A D B C) B Ω A + C Z + D Z Ω if A + B Ω C Z + Z Ω A + B Ω C Z if + + D = Z Ω This scattering paraeter conversion routine (to convert to arbitrary source and load ipedances) is given "Applied RF Techniques I" lecture notes, but is incorrect. A correct version of the routine is found on page 3 of "Microwave Aplifiers and Oscillators," by Christian Gentili. Z Send Z Sbegin := Γ S S conv S, Z Sbegin, Z Send, Z Lbegin, Z Lend S ω Z Send + Z Sbegin Z Lend Z Lbegin Γ L Z Lend + Z Lbegin ( Γ L S, ) D Γ S S, Γ S A Γ S Γ L A Γ L ( Γ S ) ( Γ L ) Γ S Γ L S S,, A ( Γ L S, ) S Γ, S + Γ L S S,, A D A S A, ( Γ L ) D A S, Γ S A D A ( Γ S S, ) S Γ, L + A D := ABCDS ABCD( ω), Z S-paraeters of ideal atching network with actual load and source ipedances. := S conv ( S ( ω), Z, Z S, Z, Z L ) Oh S-paraeters of ideal atching network. S ω Plots of lossy and ideal S-paraaters of the atching network verses frequency. Be careful when using these plots, as they do not reflect the change in source and load ipedance vs. frequency (for exaple if driver output ipedance is capacitive). f f start := f stop f nui f stop f vectori := f start ω i := π f vectori s := j ω f i i start i S vs. Frequency := Starting and stopping frequencies for plot S vs. Frequency (, ) log S ω i (, ) log S ω i
(, ) log S ω i (, ) log S ω i. 3. 4. f vectori. 3. 4. f vectori (, ) log S ω i MHz S vs. Frequency 3 4 9. 3. 4. f vectori MHz (, ) log S ω i Copyright Inforation MHz S vs. Frequency 4 4. 3. 4. f vectori All software and other aterials included in this docuent are protected by copyright, and are owned or controlled by Circuit Sage. The routines are protected by copyright as a collective work and/or copilation, pursuant to federal copyright laws, international conventions, and other copyright laws. Any reproduction, odification, publication, transission, transfer, sale, distribution, perforance, display or exploitation of any of the routines, whether in whole or in part, without the express written perission of Circuit Sage is prohibited. MHz 9