July 26, 2005 Samsung K4H510838C-UCCC 512Mbit DDR SDRAM Structural Analysis For comments, questions, or more information about this report, or for any additional technical needs concerning semiconductor technology, please call Sales at Chipworks. 3685 Richmond Road, Suite 500, Ottawa, ON K2H 5B7, Canada Tel: 613.829.0414 Fax: 613.829.0515 www.chipworks.com
Structural Analysis Table of Contents 1 Overview 1.1 List of Figures 1.2 List of Tables 1.3 Introduction 1.4 Company Profile 1.5 Device Summary 1.6 Major Findings 2 Device Overview 2.1 Package and Die 2.2 Die Features 3 Process Analysis 3.1 General Device Structure 3.2 Bond Pads 3.3 Dielectrics 3.4 Metallization 3.5 Vias and Contacts 3.6 Peripheral Transistors and Poly 3.7 Recessed Channel Array Transistors (RCATs) 3.8 Isolation 3.9 Wells and Substrate 3.10 Redundancy Fuses 4 Memory Cell Analysis 4.1 DRAM Cross-Sectional Analysis (Parallel to Bit Line) 4.2 DRAM Cross-Sectional Analysis (Parallel to Word Line) 4.3 DRAM Plan-View Analysis
Structural Analysis 5 Materials Analysis 5.1 SIMS Analysis of Dielectrics 5.2 TEM EDS Analysis of IMDs and PMD 5.3 TEM EDS Analysis of Metallization 5.4 TEM EDS Analysis of Capacitors 5.5 TEM EDS Analysis of Transistors and Contact Implant 6 Critical Dimensions 6.1 Horizontal Dimensions 6.2 Vertical Dimensions 7 References Report Evaluation
Overview 1-1 1 Overview 1.1 List of Figures 2 Device Overview 2.1.1 Package Top 2.1.2 Package Bottom 2.1.3 Plan-View Package X-Ray 2.1.4 Die Photograph 2.1.5 Annotated Die Photograph 2.1.6 Die Marking 2.2.1 Die Corner 1 2.2.2 Die Corner 2 2.2.3 Bond Pads 3 Process Analysis 3.1.1 General Device Structure 3.1.2 Die Edge 3.1.3 Die Edge Seal 3.2.1 Ball Bond Overview 3.2.2 Bond Pad Edge 3.3.1 Dielectric Layers 3.3.2 Device Passivation Sub Layers (TEM) 3.3.3 Overall View of IMD 2 3.3.4 Detailed View of IMD 2 Sub Layers (TEM) 3.3.5 Overall View of IMD 1 3.3.6 Detailed View of IMD 1 Lower Levels and PMD 3.3.7 Detailed View of IMD 1-2 Layer (TEM) 3.3.8 Detailed View of PMD (TEM) 3.4.1 Minimum Pitch Metal 3 3.4.2 Metal 3 Composition (TEM) 3.4.3 Minimum Pitch Metal 2 3.4.4 Metal 2 Composition (TEM) 3.4.5 Detail of Metal 2 Cap (TEM) 3.4.6 Minimum Pitch Metal 1 Bit Lines 3.4.7 Metal 1 Composition (TEM) 3.5.1 Minimum Pitch Via 2s 3.5.2 Via 1 Contacts to Poly 6 and Metal 1
Overview 1-2 3.5.3 Via 1 Contacts to Poly 3 and Poly 6 3.5.4 Minimum Pitch Via 1s and Contacts 3.5.5 Detail of Top of Via 1 3.5.6 Detail of Top of Via 1 (TEM) 3.5.7 Detail of Tops of Minimum Pitch Via 1s (TEM) 3.5.8 Detail of Bottom Via 1 3.5.9 Detail of Bottom of Via 1 (TEM) 3.5.10 Metal 1 Contact to Poly 2 3.5.11 Minimum Pitch Poly 2 Contacts (TEM) 3.5.12 Minimum Pitch Contacts to Polycide 3.5.13 Detail of Tungsten Contact to Si (TEM) 3.6.1 NMOS Peripheral Transistors 3.6.2 PMOS Peripheral Transistor 3.6.3 Peripheral Transistor Thin Gate Oxide (TEM) 3.6.4 TEM Lattice Image of Thin Gate Oxide (Peripheral Transistor) 3.6.5 Peripheral Transistor Thin Gate Oxide/STI Interface (TEM) 3.6.6 Peripheral Transistor Thick Gate Oxide (TEM) 3.6.7 TEM Lattice Image of Thick Gate Oxide (Periphal Transistor) 3.6.8 Poly 3 Interconnect Plan-View 3.6.9 Poly 3 Interconnect 3.7.1 Recessed Channel Array Transistors (RCATs) 3.7.2 Detail of RCATs (TEM) 3.7.3 Detail of Recessed Channel (TEM) 3.7.4 TEM Lattice Image of Gate Oxide Bottom of Recessed Channel 3.8.1 Minimum Width STI 3.8.2 STI Sidewall (TEM) 3.9.1 SCM of Embedded P-Well 3.9.2 Detail of Embedded P-Well Boundary 3.9.3 SRP Plot of N-Well (Periphery) 3.9.4 SRP Plot of P-Well (Periphery) 3.9.5 SRP Plot of Well Structure Beneath DRAM Array 3.10.1 Redundancy Fuses 3.10.2 Fuse Window 3.10.3 Redundancy Fuses Parallel to Fuse Link 3.10.4 Detail of Redundancy Fuses Parallel to Fuse Link 3.10.5 Redundancy Fuses Perpendicular Fuse Link 3.10.6 Redundancy Fuses Perpendicular Fuse Link
Overview 1-3 4 Memory Cell Analysis 4.1.1 DRAM Parallel to Bit Line Overview 4.1.2 Top of Storage Capacitors (TEM) 4.1.3 Bottom Storage Capacitors (TEM) 4.1.4 Capacitor Contacts (TEM) 4.1.5 DRAM Parallel to Bit Line Bit Line Contacts (Edge of Memory Block) 4.2.1 DRAM Parallel to Word Line Capacitor Contacts 4.2.2 Capacitor Dielectric 4.2.3 Dielectric Over Field 4.2.4 Capacitor Contacts/Metal 1 Bit Lines (TEM) 4.2.5 Capacitor Contacts Edge of Memory Block (TEM) 4.2.6 DRAM Parallel to Word Line (Edge of Memory Block) 4.2.7 Metal 1 Bit Lines and Poly 1 Word Line (TEM) 4.2.8 Bit Line Contacts (TEM) 4.3.1 Plan-View Analysis Reference 4.3.2 Poly 6 Capacitor Top Plate 4.3.3 Storage Capacitor Overview 4.3.4 MIS Storage Capacitor Cylinders (TEM) 4.3.5 MIS Storage Capacitor Cylinders (TEM) 4.3.6 MIS Storage Capacitor Cylinder Composition (TEM) 4.3.7 Poly 3 Capacitor Landing Pads 4.3.8 Metal 1 Bit Lines 4.3.9 Poly 2 Array Contacts 4.3.10 Poly 1 Word Lines 4.3.11 Diffusions and STI
Overview 1-4 5 Materials Analysis 5.1.1 SIMS Profile of Dielectrics 5.2.1 TEM EDS Spectrum of Passivation 2 5.2.2 TEM EDS Spectrum of IMD 2-2 5.2.3 TEM EDS Spectrum of IMD 1-4 5.2.4 TEM EDS Spectrum of IMD 1-1 5.2.5 TEM EDS Spectrum of Metal 1 Hard Mask 5.2.6 TEM EDS Spectrum of PMD 3 5.2.7 TEM EDS Spectrum of Gate Capping Layer 5.3.1 TEM EDS Spectrum of Metal 2 Cap 2 5.3.2 TEM EDS Spectrum of Metal 2 Cap 1 5.3.3 TEM EDS Spectrum of Metal 2 Ti:Al Alloy (Above Barrier) 5.3.4 TEM EDS Spectrum of Metal 2 Barrier 5.3.5 TEM EDS Spectrum of Metal 1 Body/Adhesion Layer 5.4.1 TEM EDS Spectrum of Poly 6 Top Plate 5.4.2 TEM EDS Spectrum of Poly 5 Inside Capacitor Cylinder 5.4.3 TEM EDS Spectrum of TiN in Capacitor 5.4.4 TEM EDS Spectrum of Al 2 O 3 Dielectric 5.4.5 TEM EDS Spectrum of HfO 2 Dielectric 5.5.1 TEM EDS Spectrum of Gate Silicide 5.5.2 TEM EDS Spectrum of Contact Silicide 1.2 List of Tables 2.2.1 Bond Pad Dimensions 3.3.1 Dielectric Composition and Thicknesses 3.4.1 Metallization Vertical Dimensions 3.4.2 Metallization Horizontal Dimensions 3.5.1 Via and Contact Dimensions 3.6.1 Peripheral Transistor and Polycide Dimensions 3.7.1 RCAT Dimensions 4.2.1 Capacitor Dielectric Thicknesses (On Field)
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