Chapter 1, Introduction

Similar documents
Progress due to: Feature size reduction - 0.7X/3 years (Moore s Law). Increasing chip size - 16% per year. Creativity in implementing functions.

VLSI Design. Introduction

EMT 251 Introduction to IC Design

Lecture Integrated circuits era

Transistor was first invented by William.B.Shockley, Walter Brattain and John Bardeen of Bell Labratories. In 1961, first IC was introduced.

420 Intro to VLSI Design

VLSI Design. Introduction

Introduction to VLSI ASIC Design and Technology

Chapter 3 Basics Semiconductor Devices and Processing

Chapter 3: Basics Semiconductor Devices and Processing 2006/9/27 1. Topics

Silicon VLSI Technology. Fundamentals, Practice and Modeling. Class Notes For Instructors. J. D. Plummer, M. D. Deal and P. B.

Integrated Circuit Technology (Course Code: EE662) Lecture 1: Introduction

Assoc. Prof. Dr. MONTREE SIRIPRUCHYANUN

+1 (479)

MICROPROCESSOR TECHNOLOGY

FABRICATION OF CMOS INTEGRATED CIRCUITS. Dr. Mohammed M. Farag

EE4800 CMOS Digital IC Design & Analysis. Lecture 1 Introduction Zhuo Feng

Lecture 8. MOS Transistors; Cheap Computers; Everycircuit

ECE 2300 Digital Logic & Computer Organization

Lecture 0: Introduction

Topic 3. CMOS Fabrication Process

IH2655 Design and Characterisation of Nano- and Microdevices. Lecture 1 Introduction and technology roadmap

Basic Fabrication Steps

In 1951 William Shockley developed the world first junction transistor. One year later Geoffrey W. A. Dummer published the concept of the integrated

Layout of a Inverter. Topic 3. CMOS Fabrication Process. The CMOS Process - photolithography (2) The CMOS Process - photolithography (1) v o.

Photolithography I ( Part 1 )

2.8 - CMOS TECHNOLOGY

Design cycle for MEMS

Introduction to Electronic Devices

CMOS: Fabrication principles and design rules

Digital Integrated Circuits

Intel's 65 nm Logic Technology Demonstrated on 0.57 µm 2 SRAM Cells

Mathematics and Science in Schools in Sub-Saharan Africa

Logic and Computer Design Fundamentals. Chapter 6 Selected Design Topics. Part 1 The Design Space

Lecture 1 Introduction to Solid State Electronics

Spiral 1 / Unit 8. Transistor Implementations CMOS Logic Gates

LSI ON GLASS SUBSTRATES

CMOS Digital Integrated Circuits Lec 2 Fabrication of MOSFETs

2009 Spring CS211 Digital Systems & Lab 1 CHAPTER 3: TECHNOLOGY (PART 2)

The future of lithography and its impact on design

Chapter 15 Summary and Future Trends

Lecture 020 ECE4430 Review II (1/5/04) Page 020-1

ECE 5745 Complex Digital ASIC Design Topic 2: CMOS Devices

Lecture 020 ECE4430 Review II (1/5/04) Page 020-1

EE241 - Spring 2013 Advanced Digital Integrated Circuits. Announcements. Sign up for Piazza if you haven t already

Introduction. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002

EE669: VLSI TECHNOLOGY

EE141-Fall 2009 Digital Integrated Circuits

Microelectronics, BSc course

Introduction. Reading: Chapter 1. Courtesy of Dr. Dansereau, Dr. Brown, Dr. Vranesic, Dr. Harris, and Dr. Choi.

Methods for Manufacturing Improvement IEOR 130. Prof. Robert C. Leachman University of California at Berkeley. August, 2017

Chapter 1 Introduction Historical Perspective

ELCN100 Electronic Lab. Instruments and Measurements Spring Lecture 01: Introduction

The Art of ANALOG LAYOUT Second Edition

32nm High-K/Metal Gate Version Including 2nd Generation Intel Core processor family

Advanced Digital Integrated Circuits. Lecture 2: Scaling Trends. Announcements. No office hour next Monday. Extra office hour Tuesday 2-3pm

EE 410: Integrated Circuit Fabrication Laboratory

EC0306 INTRODUCTION TO VLSI DESIGN

VLSI: An Introduction

DIGITAL TECHNICS. Dr. Bálint Pődör. Óbuda University, Microelectronics and Technology Institute

Electronic Circuits. Lecturer. Schedule. Electronic Circuits. Books

DIGITAL TECHNICS II. Dr. Bálint Pődör. Óbuda University, Microelectronics and Technology Institute 6. LECTURE: LOGIC CIRCUITS I

Lecture #29. Moore s Law

EE 330 Lecture 7. Design Rules. IC Fabrication Technology Part 1

Digital Integrated Circuits 1: Fundamentals

Introduction. Introduction. Digital Integrated Circuits A Design Perspective. Introduction. The First Computer

Improved Inverter: Current-Source Pull-Up. MOS Inverter with Current-Source Pull-Up. What else could be connected between the drain and V DD?

FUTURE PROSPECTS FOR CMOS ACTIVE PIXEL SENSORS

Introduction to Digital Logic Missouri S&T University CPE 2210 Electric Circuits

LSI Logic LSI53C1030 PCI-X to Dual Channel Ultra320 SCSI Controller 0.18 µm CMOS Process

ECE520 VLSI Design. Lecture 2: Basic MOS Physics. Payman Zarkesh-Ha

CPE/EE 427, CPE 527 VLSI Design I L01: Introduction, Design Metrics. What is this course all about?

Lecture 33 - The Short Metal-Oxide-Semiconductor Field-Effect Transistor (cont.) April 30, 2007

Variation-Aware Design for Nanometer Generation LSI

This Week s Subject. DRAM & Flexible RRAM. p-channel MOSFET (PMOS) CMOS: Complementary Metal Oxide Semiconductor

Basic Characteristics of Digital ICs

Process Control Limits in a CMOS ASIC Fabrication Process K. Jayavel, K.S.R.C.Murthy

40nm Node CMOS Platform UX8

CS 6135 VLSI Physical Design Automation Fall 2003

Chapter 2 : Semiconductor Materials & Devices (II) Feb

From Sand to Silicon Making of a Chip Illustrations May 2009

EE 434 ASIC & Digital Systems

Design Simulation and Analysis of NMOS Characteristics for Varying Oxide Thickness

Lecture 27 ANNOUNCEMENTS. Regular office hours will end on Monday 12/10 Special office hours will be posted on the EE105 website

Propagation Delay, Circuit Timing & Adder Design. ECE 152A Winter 2012

Propagation Delay, Circuit Timing & Adder Design

Maxim MAX3940E Electro-Absorption Modulator Structural Analysis

Shorthand Notation for NMOS and PMOS Transistors

Physical Design of Digital Integrated Circuits (EN0291 S40) Sherief Reda Division of Engineering, Brown University Fall 2006

1 Digital EE141 Integrated Circuits 2nd Introduction

1. Introduction. Institute of Microelectronic Systems. Status of Microelectronics Technology. (nm) Core voltage (V) Gate oxide thickness t OX

Unit-1. MOS Transistor Theory

Introduction to Microdevices and Microsystems

SAMPLE SLIDES & COURSE OUTLINE. Core Competency In Semiconductor Technology: 2. FABRICATION. Dr. Theodore (Ted) Dellin

Semiconductor TCAD Tools

Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, Digital EE141 Integrated Circuits 2nd Introduction

Digital Integrated Circuits EECS 312

Outcomes. Spiral 1 / Unit 8. DeMorgan s Theorem DEMORGAN'S THEOREM. Transistor Implementations CMOS Logic Gates

Introduction to Materials Engineering: Materials Driving the Electronics Revolution Robert Hull, MSE

VLSI Design. Brief Syllabus. Course Scope. Major Contents. IC Evolution. Today s Outline

Transcription:

Introduction to Semiconductor Manufacturing Technology Chapter 1, Introduction hxiao89@hotmail.com 1

Objective After taking this course, you will able to Use common semiconductor terminology Describe a basic IC fabrication sequence Briefly explain each process step Relate your job or products to semiconductor manufacturing process 2

Topics Introduction IC Device and Design Semiconductor Manufacturing Processes Future Trends 3

Introduction First Transistor, AT&T Bell Labs, 1947 First Single Crystal Germanium, 1952 First Single Crystal Silicon, 1954 First IC device, TI, 1958 First IC product, Fairchild Camera, 1961 4

First Transistor, Bell Lab, 1947 Photo courtesy: AT&T Archive 5

First Transistor and Its Inventors John Bardeen, William Shockley and Walter Brattain Photo courtesy: Lucent Technologies Inc. 6

First IC Device Made by Jack Kilby of Texas Instrument in 1958 Photo courtesy: Texas Instruments 7

First Silicon IC Chip Made by Robert Noyce of Fairchild Camera in 1961 Photo courtesy: Fairchild Semiconductor International 8

Moore s Law Intel co-founder Gorden Moore notice in 1964 Number of transistors doubled every 12 months while price unchanged Slowed down in the 1980s to every 18 months Amazingly still correct, likely to keep until 2010. 9

Moore s Law, Intel s Version Transistors Pentium III 10M 1M 80486 Pentium 100K 10K 1K 80386 8086 80286 4040 8080 1975 1980 1985 1990 1995 2000 10

IC Scales Integration level Abbreviation Number of devices on a chip Small Scale Integration SSI 2 to 50 Medium Scale Integration MSI 50 to 5,000 Large Scale Integration LSI 5,000 to 100,000 Very Large Scale Integration VLSI 100,000 to 10,000,000 Ultra Large Scale Integration ULSI 10,000,000 to 1,000,000,000 Super Large Scale Integration SLSI over 1,000,000,000 11

Road Map Semiconductor Industry 1995 1997 1999 2001 2004 2007 Minimum feature size (μm) 0.35 0.25 0.18 0.13 0.10 0.07 DRAM Bits/chip 64 M 256 M 1 G 4 G 16 G 64 G Cost/bits @ volume (millicents) 0.017 0.007 0.003 0.001 0.0005 0.0002 Microprocessor Transistors/cm 2 4 M 7 M 13 M 25 M 50 M 90 M Cost/Transistor @ volume (millicents) 1 0.5 0.2 0.1 0.05 0.02 ASIC Transistors/cm 2 2 M 4 M 7 M 13 M 25 M 40 M Cost/Transistor @ volume (millicents) 0.3 0.1 0.05 0.03 0.02 0.01 Wafer size (mm) 200 200 200-300 300 300 300 400 (?) 12

Feature Size and Wafer Size Chip made with 0.35 μm technology with 0.25 μm technology with 0.18 μm technology Chip or die 300 mm 200 mm 150 mm 13

Smallest Known Transistor Made by NEC in 1997 Source Lower gate Upper gate Dielectric Drain n + n + P-type substrate Ultra shallow junctions 0.014 micron lower gate width Photo courtesy: NEC Corporation 14

Limit of the IC Geometry Size of the atom 15

Limit of the IC device Atom size: several Å Need some atoms to form a device Likely the final limit is around 100 Å or 0.01 micron. About 30 silicon atoms 16

IC Design: First IC Photo courtesy: Texas Instruments 17

IC Design: CMOS Inverter V in V dd (a) NMOS PMOS V ss V out N-channel active region N-channel Vt N-channel LDD N-channel S/D Shallow trench isolation (STI) P-channel active region P-channel Vt P-channel LDD P-channel S/D (b) P-well Metal 1 Polycide gate and local interconnection N-well Contact Metal 1, AlCu W PMD n + P-Well n + P-Epi STI P-Wafer p + p + N-Well (c) 18

IC Design: Layout and Masks of CMOS Inverter CMOS inverter layout Mask 1, N-well Mask 2, P-well Mask 3, shallow trench isolation Mask 4, 7, 9, N-Vt, LDD, S/D Mask 5, 8, 10, P-Vt, LDD, S/D Mask 6, gate/local interconnection Mask 11, contact Mask 12, metal 1 19

Mask/Reticle Pellicle Chrome pattern Phase shift coating Quartz substrate 20

A Mask and a Reticle Photo courtesy: SGS Thompson 21

Wafer Process Flow Materials IC Fab Metallization CMP Dielectric deposition Test Wafers Masks Thermal Processes Implant PR strip Etch PR strip Packaging Photolithography Final Test Design 22