A Sub-0.75 RMS-Phase-Error Differentially-Tuned Fractional-N Synthesizer with On-Chip LDO Regulator and Analog-Enhanced AFC Technique Lei Lu, Lingbu Meng, Liang Zou, Hao Min and Zhangwen Tang Fudan University, Shanghai, China
Outline Motivation System Architecture Level Shifter for Symmetrical Tuning Curves High-PSR LDO Regulator Digital AFC with Monitor Measured Results Conclusions 2
Motivation Symmetrical tuning curves Level Shifters eliminate threshold voltage Large noise from power supply deteriorates VCO severely High-PSR LDO Regulator Frequency drift due to temperature variation Control Voltage monitor to restart AFC 3
Single-Ended Tuned Synthesizer f ref PFD Charge Pump N I cp Z F (s) Loop Filter K vco =Δf vco /ΔV c V c fvco VCO Divider DSM open-loop gain I cpz F (s)k vco 2πN Advantage: Single-ended CP and VCO Disadvantage: Susceptible to CM noise, large LPF area 4
Differentially Tuned Synthesizer f ref PFD Charge Pump N 0.5I cp 0.5I cp Z F (s) Loop Filter Loop Filter ZF (s) K vco =Δf vco /Δ(V cp V cn ) V cp V cn VCO fvco Divider DSM open-loop gain [0.5I cp ( 0.5I cp )]Z F (s)k vco 2πN Advantage: Immune to CM noise, small LPF area (differential LPF) Disadvantage: differential CP and VCO 5
Synthesizer Block Diagram Digital AFC 8 Band Shift up C 2 R 3 R f 1 ref upb s 1 V ref C 1 /2 f div PFD dn dnb s 1 R 1 C 2 R 3 C 3 C 3 Differential LPF V cp s 2 s 1 V ref s 1 s 2 V cn Level Shift Voltage Monitor Level Shift V cpo V cno LDO VCO f vco Differential CP N Divider DSM 6
Simplified differential LC-tank Differential tuning of VCO Inversion MOS transistors as varactors V op L V on V cn V cp n-type I-MOS varactors p-type I-MOS varactors fixed capacitors 7
Conventional Differentially Tuned Techniques V op V cn V on C n V ocm =(V op +V on )/2 V thn V thn V thn V ccm =(V cp +V cn )/2 V ocm V cn V cp C p V ocm =(V op +V on )/2 V op V on V thp V thp V thp V ocm V cp 8
Asymmetrical Tuning Curves Inversion MOS varactors have both p- type and n-type Better choice in differentially tuned VCO than accumulation transistors Lead to asymmetrical tuning curves even if V ccm is equal to V ocm [See Soltanian, et al., CICC 06] The middle point of tuning curves deviates from V ocm by V thn + V thp 9
Proposed Differentially Tuned Techniques with Level Shifters V op V cno V on C n V ocm V thn +V gsn =V ccm V thn V thn V cn V gsn Level Shifter V ocm V thn +V gsn V cn V cp V gsp C p V ocm + V thp V gsp =V ccm V op V on V thp V cpo V thp V ocm + V thp V gsp V cp 10
High-PSR LDO Regulator V DD Sense V DD variation to improve PSRR M 1 cancelled V in =1.5V folded cascode Pass Transistor VCO load with buffer add one zero to improve stability 15mA C L 11
Simulated Noise and PSR of LDO 12
AFC and Voltage Monitor (1) Flow chart 80 μs is enough for locking Digital AFC start Y >8 th Comp? Wait 80μs Count VCO clock and compare ε 2? Y N N Shift VCO band AFC finished V cl <V cp,v cn <V ch? N Y Digital AFC Voltage Monitor 13
AFC and Voltage Monitor (2) Set two boundary for control voltages Ensure control voltages fall between them Freq. V ch V cp Δf V cl AFC start V c V cl V ch Linear Range (ΔV c ) V cn 14
Other Circuits Details VCO Complementary cross-coupled transistors Two tail inductors to lower the phase noise Charge Pump Differentially configured Rail-to-rail CMFB Loop Filter On-chip MIM capacitor and high-res poly resistor Delta sigma modulator & P/S Counter Programmed using Verilog language 15
Die Micrograph 1.47mm 1mm 0.18μm CMOS process 1P6M 16
Measured Tuning Curves Tuning range: 1.2 ~ 2.1 GHz Coarse tuning: 8-bit control, 256 sub-bands Oscillation Frequency (GHz) 2.11 2.1 2.09 2.08 2.07 1.64 1.63 1.62 1.61 1.22 1.21 1.2 1.19-1.5-1 -0.5 0 0.5 1 1.5 Differential Control Voltages (V) 17
Measured Phase Noise Typical fractional-n case: 1.6135 GHz 18
Phase Noise With and Without LDO 19
Loop Bandwidth and Phase Error Phase error: Integrated from 100 Hz to 40 MHz 20
Measured Locking Process Locking time: 20 μs (6.4 μs for AFC) 21
Performance Summary Technology 0.18-μm CMOS Die Area 1.47 mm 1 mm Supply Voltage 1.8 V (VCO with 1.5 V) Current 16 ma Ref. Clock 25 MHz Output Freq. 1.2 GHz ~ 2.1 GHz Phase Noise (dbc/hz) Phase Error Locking Time Integer-N Fractional-N Integer-N Fractional-N 20 μs 100@10kHz 96@10kHz <0.5 RMS <0.75 RMS 22
Conclusions Have proposed level shifters to ensure symmetrical tuning curves Have demonstrated high-psr LDO regulator Have introduced voltage monitor to overcome frequency drift Have achieved superior phase noise and phase error performance across the whole wideband tuning range 23