EE520 VLSI esign Lecture 11: ombinational Static Logic Prof. Payman Zarkesh-Ha Office: EE ldg. 230 Office hours: Wednesday 2:00-3:00PM or by appointment E-mail: pzarkesh@unm.edu Slide: 1
eview of Last Lecture L-Edit emo Layout Techniques esign for density esign for performance esign for reliability Slide: 2
Today s Lecture ombinational Logic Logic esign Transistor Sizing elay nalysis Slide: 3
ombinational versus Sequential Logic ombinational Logic: Out=f(in) sequential Logic: Out=f(in,previous_in) In ombinational Logic ircuit Out In ombinational Logic ircuit Out State ombinational Logic: Output is a function of present inputs (delayed by the propagation delay) i.e., do not contain memory Implements logic functions like NN, NO, XO, Multiplex or any complex functions such as ecoder, adder, shifter Sequential Logic: Implement memory Stores past values Edge sensitive: Flip-flops Level sensitive: Latches Slide: 4
Static MOS Logic Gate V In1 In2 InN In1 In2 InN PUN PN PMOS only NMOS only F(In1,In2, InN) PUN and PN are dual logic networks Static Logic is a gate where the output is maintained at 0 or 1 as long as power is applied PUN and PN are dual (omplimentary) to drive the output from 0 to 1 and 1 to 0 full rail (VSS to V) Slide: 5
Static versus ynamic Logic Gate Static Logic ynamic Logic V In1 In2 PUN PMOS only lk M p Out InN In1 In2 InN PN NMOS only F(In1,In2, InN) In 1 In 2 In 3 lk PN M e L Unlike static logic, in dynamic logic the output may leak away The output is valid only after pre-charge when clock applies Slide: 6
PUN and PN Networks PUN V S V V 0 V V GS S 0 V -V Tn L L PN V 0 V V Tp V L V GS S L S NMOS is a good pull down device (PN) PMOS is a good pull up device (PUN) Slide: 7
Example: NN Gate PUN: += (onduction to V) PN: (onduction to GN) How do you size transistors to have approximately the same delay as an inverter? Slide: 8
Example: NO Gate PUN: = + (onduction to V) PN: + (onduction to GN) How do you size transistors to have approximately the same delay as an inverter? Which one is better to use often: NO or NN? Slide: 9
Example: More omplicated Gate onsider F=+(+) Stacks give the N function Parallel gates give the O function erive the PN in hierarchical fashion uild the complement for the PUN OUT = + ( + ) onvert stacks to parallel onvert parallel to stacks Slide: 10
Transistor Sizing of a omplex MOS Gate 4 8 8 4 OUT = + ( + ) 1 2 2 2 Size of transistors to have the same delay of an inverter when (W/L) P =2 and (W/L) N =1 Slide: 11
Example: OI and OI Gates N-O-Invert re used quite often in VLSI design elatively complex function in one stage an also be used as multiplexer OI Logic Gate OI Logic Gate b a b a c d c d a c a c b d b d Slide: 12
Gate ynamic ehavior (NN) elay is dependent on the pattern of inputs Low to high transition both inputs go low then delay is 0.69 p /2 L one input goes low then delay is 0.69 p L High to low transition both inputs go high then delay is 0.69 2 n L More accurate delay estimation is very complicated Internal capacitances ( int ) Effective load capacitance (depends on ON transistors and int ) ody effect of stacked transistors p n n p L int Slide: 13
Gate ynamic ehavior (NN) 3 2.5 ==10 Input ata Pattern elay (psec) Voltage [V] 2 1.5 1 0.5 =1, =10 =1 0, =1 ==01 =1, =01 = 01, =1 ==10 =1, =10 67 64 61 45 80 0-0.5 0 100 200 300 400 time [ps] = 10, =1 81 NMOS = 0.5m/0.25 m PMOS = 0.75m/0.25 m L = 100 ff Slide: 14
elay Estimation Using Elmore elay Model out int N int out Elmore delay model can be used to take int into account The total capacitance seen when discharging via the transistor controlled by input depends on the voltage applied to input This is that side branch capacitance Slide: 15
EE520 Lecture 11 Slide: 16 University of New Mexico L 3 2 1 nother Example L 3 2 1 PHL 0.69 t Using Elmore delay model the worst case delay is: Note that appears in all terms
Some Gate Inputs are Faster than Others Transistor with input is the slowest transistor It is also the furthest to the output Put the earliest arriving input there This gives time for the other series transistors to discharge the intermediate nodes before the latest input arrives Gate symbols should be labeled to show the fast vs. slow inputs This can be as simple as order, e.g., a, b, c, d Note that this means a is the bottom on a NO, top on NN Example 2 input NN gate with inputs a and b If input b arrives at 5.1ns and a arrives at 5.5ns the is just OUT rather than INT + ( + ) INT If the time to discharge the intermediate node is < 400 ps on t forget the upper transistor does not have appreciable V GS -V T until the source node drops Slide: 17
More on elay ependency to Input Pattern L 3 2 1 a=0, b=1, c=1, d=1 leaves the intermediate nodes predischarged ut a=1, b=1, c=1, d=0 leaves them at V - V Tn Therefore, when all inputs go to one the speed may vary Slide: 18