High-Current -State s Drive Bus Lines, Buffer Memory Address Registers, or Drive up to LSTTL Loads True s Package Options Include Plastic Small-Outline (D) and Ceramic Flat (W) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 00-mil DIPs description These hex buffers and line drivers are designed specifically to improve both the performance and density of -state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. The HC6 contain six independent buffers/drivers with dual-gated output-enable ( and ) inputs. When and are both low, the device passes noninverted data from the A inputs to the Y outputs. If either (or both) output-enable terminal(s) is high, the outputs are in the high-impedance state. The SN4HC6 is characterized for operation over the full military temperature range of C to 2 C. The SN74HC6 is characterized for operation from 40 C to 8 C. SN4HC6, SN74HC6 SN4HC6...J OR W PACKAGE SN74HC6... D OR N PACKAGE (TOP VIEW) SN4HC6... FK PACKAGE (TOP VIEW) Y A2 Y2 A Y A2 Y2 A Y GND 2 4 6 7 8 V CC 4 2 20 9 8 6 7 8 7 6 4 902 Y GND 6 4 2 0 9 Y4 A4 V CC A6 Y6 A Y A4 Y4 No internal connection A6 Y6 A Y FUTION TABLE (each buffer/driver) INPUTS OUTPUT A Y H X X Z X H X Z L L H H L L L L Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 997, Texas Instruments Incorporated POST OFFICE BOX 60 DALLAS, TEXAS 726
SN4HC6, SN74HC6 logic symbol & EN A2 A A4 A A6 2 4 6 0 2 4 7 9 Y Y2 Y Y4 Y Y6 This symbol is in accordance with ANSI/IEEE Std 9-984 and IEC Publication 67-2. Pin numbers shown are for the D, J, N, and W packages. logic diagram (positive logic) 2 Y To Five Other Channels Pin numbers shown are for the D, J, N, and W packages. absolute maximum ratings over operating free-air temperature range Supply voltage range, V CC.......................................................... 0. V to 7 V Input clamp current, I IK (V I < 0 or V I > V CC ) (see Note ).................................... ±20 ma clamp current, I OK (V O < 0 or V O > V CC ) (see Note )................................ ±20 ma Continuous output current, I O (V O = 0 to V CC ).............................................. ± ma Continuous current through V CC or GND................................................... ±70 ma Package thermal impedance, θ JA (see Note 2): D package.................................. C/W N package................................... 78 C/W Storage temperature range, T stg................................................... 6 C to 0 C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES:. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD, except for through-hole packages, which use a trace length of zero. 2 POST OFFICE BOX 60 DALLAS, TEXAS 726
SN4HC6, SN74HC6 recommended operating conditions SN4HC6 SN74HC6 MIN NOM MAX MIN NOM MAX Supply voltage 2 6 2 6 V = 2 V.. VIH High-level input voltage = 4. V.. V = 6 V 4.2 4.2 = 2 V 0 0. 0 0. VIL Low-level input voltage = 4. V 0. 0. V = 6 V 0.8 0.8 VI Input voltage 0 0 V VO voltage 0 0 V = 2 V 0 000 0 000 tt Input transition (rise and fall) time = 4. V 0 00 0 00 ns = 6 V 0 400 0 400 TA Operating free-air temperature 2 40 8 C electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS TA = 2 C SN4HC6 SN74HC6 MIN TYP MAX MIN MAX MIN MAX 2 V.9.998.9.9 IOH = 20 µa 4. V 4.4 4.499 4.4 4.4 VOH VI = VIH or VIL 6 V.9.999.9.9 V IOH = 6 ma 4. V.98 4..7.84 IOH = 7.8 ma 6 V.48.8.2.4 2 V 0.002 0. 0. 0. IOL = 20 µa 4. V 0.00 0. 0. 0. VOL VI = VIH or VIL 6 V 0.00 0. 0. 0. V IOL = 6 ma 4. V 0.7 0.26 0.4 0. IOL = 7.8 ma 6 V 0. 0.26 0.4 0. II VI = or 0 6 V ±0. ±00 ±000 ±000 na IOZ VO = or 0 6 V ±0.0 ±0. ±0 ± µa ICC VI = or 0, IO = 0 6 V 8 60 80 µa Ci 2 V to 6 V 0 0 0 pf POST OFFICE BOX 60 DALLAS, TEXAS 726
SN4HC6, SN74HC6 switching characteristics over recommended operating free-air temperature range, C L = 0 pf (unless otherwise noted) (see Figure ) PARAMETER FROM (INPUT) TO (OUTPUT) TA = 2 C SN4HC6 SN74HC6 MIN TYP MAX MIN MAX MIN MAX 2 V 0 9 4 20 tpd A Y 4. V 2 9 29 24 ns 6 V 0 6 2 20 2 V 00 90 28 28 ten OE Y 4. V 26 8 7 48 ns 6 V 2 2 48 4 2 V 0 7 26 240 tdis OE Y 4. V 2 48 ns 6 V 9 0 4 4 2 V 28 60 90 7 tt Any 4. V 8 2 8 ns 6 V 6 0 switching characteristics over recommended operating free-air temperature range, C L = 0 pf (unless otherwise noted) (see Figure ) PARAMETER FROM (INPUT) TO (OUTPUT) TA = 2 C SN4HC6 SN74HC6 MIN TYP MAX MIN MAX MIN MAX 2 V 70 20 80 0 tpd A Y 4. V 7 24 6 0 ns 6 V 4 20 2 2 V 40 20 4 28 ten OE Y 4. V 0 46 69 7 ns 6 V 28 9 9 48 2 V 4 20 26 tt Any 4. V 7 42 6 ns 6 V 6 4 operating characteristics, T A = 2 C PARAMETER TEST CONDITIONS TYP Cpd Power dissipation capacitance per buffer/driver No load pf 4 POST OFFICE BOX 60 DALLAS, TEXAS 726
PARAMETER MEASUREMENT INFORMATION SN4HC6, SN74HC6 PARAMETER RL CL S S2 From Under Test CL (see Note A) Test Point RL LOAD CIRCUIT S S2 ten tpzh tpzl tdis tphz tplz tpd or tt kω kω 0 pf or 0 pf 0 pf 0 pf or 0 pf Input 0 V tplh tphl In-Phase Out-of-Phase tphl 90% 90% 90% VOH VOL tf VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT TRANSITION TIMES tr tf tplh VOH 90% VOL tr Control (Low-Level Enabling) tpzl Waveform (See Note B) tplz 0 V VOL tpzh Input 90% 90% tr 0 V tf Waveform 2 (See Note B) 90% tphz VOH 0 V VOLTAGE WAVEFORM INPUT RISE AND FALL TIMES VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES FOR -STATE OUTPUTS NOTES: A. CL includes probe and test-fixture capacitance. B. Waveform is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR MHz, ZO = 0 Ω, tr = 6 ns, tf = 6 ns. D. The outputs are measured one at a time with one input transition per measurement. E. tplh and tphl are the same as tpd. F. tplz and tphz are the same as tdis. G. tpzl and tpzh are the same as ten. Figure. Load Circuit and Voltage Waveforms POST OFFICE BOX 60 DALLAS, TEXAS 726
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