Fabricating 2.5D, 3D, 5.5D Devices Bob Patti, CTO rpatti@tezzaron.com Tezzar on Semiconduct or 04/15/2013 1
Gen4 Dis-Integrated 3D Memory DRAM layers 42nm node 2 million vertical connections per lay per die I/O layer contains: I/O, interface logic and R&R control CPU. 65nm node Better yielding than 2D equivalent! Controller layer contains: senseamps, CAMs, row/column decodes and test engines. 40nm node Tezzar on Semiconduct or 04/15/2013 2
3 rd Si thinned to 5.5um 2 nd Si thinned to 5.5um SiO 2 1 st Si bottom supporting wafer Tezzar on Semiconduct or 04/15/2013 3
2.5/3D in Combination IME A-Star / Tezzaron Collaboration IME A-Star / Tezzaron Collaboration μbumps Die to Wafer Cu Thermal Diffusion Bond C4 Bumps 3 Layer 3D Memory FPGA (4Xnm) 2 Layer Processor level#4 C level#3 Active Silicon Circuit Board C level#2 Organic Substrate level#1 level#0 Solder Bumps Tezzar on Semiconduct or 04/15/2013 4
Tezzaron Dummy Chip C2C Assembly Memory die C2C sample X-ray inspection indicated no significant solder voids X-section of good micro bump CSCAN showed no underfill voids (UF: Namics 8443-14) Tezzar on Semiconduct or 04/15/2013 5
Near End-of-Line TSV Insertion M8 TM M7 M6 M5 M4 M4 M5 2x,4x,8x Wiring level ~.2/.2um S/W M3 SIN W M2 M1 poly STI TSV is 1.2µ Wide and ~10µ deep 5.6µ Tezzar on Semiconduct or 04/15/2013 6
Novati Heritage SEMATECH Austin site opens for business SEMATECH spins off the R&D wafer fab and associated labs as Advanced Technology Development Facility (ATDF) Tezzaron Semiconductor acquires the former SVTC facility. 1987 1988 1995 2004 2007 2012 2013 14 U.S.-based semiconductor manufacturers & U.S. government form consortium, called SEMATECH The International 300 mm Initiative (I300I) was formed as a subsidiary of SEMATECH. ATDF merges with former Cypress Semiconductor facility, SVTC Technologies. Tezzar on Semiconduct or 04/15/2013 7
Tezzaron/Novati 3D Technologies Volume 2.5D and 3D Manufacturing in 2013 Interposers Future interposers with High K Caps Photonics Passives Power transistors Wholly owned Tezzaron subsidiary Cu-Cu, DBI, Oxide, IM 3D assembly Tezzar on Semiconduct or 04/15/2013 8
Facility Overview Capabilities Over 150 production grade tools 68000 sq ft Class 10 clean room 24/7 operations & maintenance Manufacturing Execution Systems (MES) IP secure environments, robust quality systems ITAR registered Full-flow 200mm silicon processing, 300mm back-end (Copper/Low-k) Process library with > 25000 recipes Novel materials (ALD, PZT, III-V, CNT, etc) Copper & Aluminum BEOL Contact through 193nm lithography Silicon, SOI and Transparent MEMS substrates Electrical Characterization and Bench Test Lab Onsite analytical tools and labs: SIMS, SEM, TEM, Auger, VPD, ICP-MS, etc IN NOVATI ON TECHNOLOGIES ISO 9001:2008 13485:2013 TRUST 2013 Tezzar on Semiconduct or 04/15/2013 9
2.5 and 3D Opportunities & Goals Choices: Interposers Organic Silicon Glass Chip stacking Wafer to wafer Die to wafer What do we want from doing this? Performance Power Size Cost? Only from the system Tezzar on Semiconduct or 04/15/2013 10
Good ol Days Foundry Customer Assembly/Test Packaging/Test Tezzar on Semiconduct or 04/15/2013 11
Some Flows Foundry Wafer Test Dice Test Stack Test Package Test Test Bond Thin Backside process Test Dice Package Test Test Carrier Bond Thin Backside process Bump Test Remove Carrier * Dice Test Substrate Attach Stack Test Bond Thin Package Test Tezzar on Semiconduct or 04/15/2013 12
Mixing Fab, Packaging and Assembly?? Foundry? Packaging? Assembly?? Test what where when? Big hidden cost Customer Tezzar on Semiconduct or 04/15/2013 13
2.5D Alternatives Silicon Interposers 2-3um L/S/D Rs and Cs Active is the future Handling & handoff Organics 5-6 um Litho limits Material planarity limits Great cost structure TCE Challenges Large substrate Glass Large substrate Tezzar on Semiconduct or 04/15/2013 14
3D Choices Wafer-to-wafer Best cost structure Highest density interconnect It s a fab process A messy fab process Particles Materials Non-standard sizes Die-to-wafer Mixed fab and packaging flow Add TSVs Chip-to-chip Limited interconnect Cost Cost Complexity Tezzar on Semiconduct or 04/15/2013 15
New Data Needs Notch Orientation limitations Run out / street size / magnification Die location TCE matching / stress / warpage TCE zero match at what temperature? Materials Planarity Surface roughness Tezzar on Semiconduct or 04/15/2013 16
2.5D and 3D Fab Equipment Aligner/Bonder Throughput, uptime, MTTR Wafer id top side, bottom side, both, transfer Pick and place Speed/accuracy TSV plater Dedicated Deep hole liner, barrier, seed Bosch etcher Goldylocks sidewall roughness (scallops) Tezzar on Semiconduct or 04/15/2013 17
2.5D and 3D Fab Equipment Thin wafer handling - temporary carriers Bond/Debond Max temperature Size Material Shipping with/without carriers CMP Surface roughness, planarity local/global, material height(s) Low temperature oxides Metrology Profilometer Tezzar on Semiconduct or 04/15/2013 18
2.5D and 3D Fab Equipment Wafer Grinder Polish CMP Etch Tolerance & TTV Edge grinder Litho Field size especially for interposer Resolution Contamination Resist thickness Tezzar on Semiconduct or 04/15/2013 19
2.5D and 3D Fab Equipment Dicing RIE Saw Laser Bumping Equipment Testers? Tezzar on Semiconduct or 04/15/2013 20
Conclusions The requirements drive unique capabilities 2.5/3D Fab/OSAT A lot of vertical integration is required Flow optimization will be challenging Testing verses risk More vendors more testing Tezzar on Semiconduct or 04/15/2013 21