A 2.4GHz Fully Integrated CMOS Power Amplifier Using Capacitive Cross-Coupling JeeYoung Hong, Daisuke Imanishi, Kenichi Okada, and Akira Tokyo Institute of Technology, Japan
Contents 1 Introduction PA design Measurement results Conclusion
Introduction 2 PA (Power Amplifier) : A circuit used to convert a low-power RF signal into a larger signal of significant power at transmitter 2.4GHz the frequency band which require no license various wireless communication standards : WiMAX, WLAN, Bluetooth, etc.
Introduction 3 The reason for using capacitive cross-coupling High reliability of the voltage stress at output end Using self-biased cascode topology Area increase by bypass capacitor Using Cross-coupling Capacitor Reduce an area of bypass capacitor
Schematic 4 V DD =3.3V Out V DD 2 : 1 V DD V Bias1 V Bias2 V Bias1 V Bias3 In+ In- V Bias4 Class-A bias(1 st stage), Class-AB bias(2 nd stage) Differential topology for achieving 3dB larger P out Impedance matching by L, C, R
Proposed circuit To achieve a high output power 5 Differential topology 2-stage configuration Transformer Out Transformer V DD 2 : 1 V DD V Bias1 V Bias2 V Bias1 V Bias3 In+ In- V Bias4 The 1st stage The 2nd stage
Transformer 6 Relation between P sat & Z out P sat = VDD Z out 2 2 Theoretical maximum output power P sat Turn ratio=2:1 Z out (50Ω) ¼Z out (12.5Ω) P sat = 2 VDD 2 3 3. 2 2 = ( 1 Z ) ( 2 1 50) 4 out 4 = 0.8712[W] = 29.4[dBm] 2
Transformer 7 Maximum Available Gain [db] Coupling coefficient = 0.7 Maximum Available Gain(MAG) = -1.05 db ( -1.05dB 10 ) Conversion efficiency= 10 100 =78.5 % 0-2 -4-6 -8-10 0 1 2 3 4 5 Frequency [GHz] Sim. Meas. Measurement and simulation results agree with each other. Phase [degree] 180 120 60 0-60 -120-180 Phase(S31) meas. Phase(S31) sim. Phase(S32) meas. Phase(S32) sim. 0 2 4 6 8 10 Frequency [GHz]
Proposed circuit To sustain voltage stress 8 Cascode topology Thick gate-oxide transistors Out Self-biased topology V DD 2 : 1 V DD V Bias1 V Bias2 V Bias1 V Bias3 In+ In- V Bias4 Cascode Thick gate -oxide transistor Self-biased cascode
Self-biased cascode 9 at the 2 nd stage V dd V Bias C gd v d Voltage v g C bypass v s [ Conceptual diagram of voltage waveforms ] If C gs is neglected, v g = C C bypass gd + C gd v d Alleviation of voltage v gd Prevention of transistor s entering to triode region Loss of Gain Area increase by C bypass [1] T. Sowlati, et al., A 2.4-GHz 0.18-µm CMOS Self-Biased Cascode Power Amplifier, IEEE Journal of Solid- State Circuits, pp. 1318-1324, 2003
Amplitude adjustment 10 Voltage [V] Voltage waveform 8 7 6 5 4 3 2 1 Vd2 Vg2 Vd1 [Self-biased cascode] 0 0 0.2 0.4 0.6 0.8 1 Time [nsec] V g amplitude=19% of the V d amplitude C bypass =14.5pF
Gain degradation 11 Gain [db] 32 31 30 29 28 27 26 25 24 Standard cascode Using crosscoupling Self-Biased -35-25 -15-5 5 Pin [dbm] Self-biased cascode method degrades the gain compare with standard cascode method using fixed bias voltage.
Capacitive cross-coupling Self-biased cascode Using capacitive cross-coupling 12 v g = C C bypass gd + C gd v d v g = C bypass C gd C gd c + ( C C c v ) d C c is tuned to v g amplitude 18% of v d amplitude C gd is reduced, thus C bypass is decreased
Amplitude adjustment 2 13 V DD Pin=5dBm V Bias -v d Cc v g2 C bypass C gd v d2 v d1 [ Self-biased cascode with ] capacitive cross-coupling Voltage [V] 8 7 6 5 4 3 2 1 0 Vd2 Vg2 Vd1 0 0.2 0.4 0.6 0.8 1 Time [nsec] V g amplitude=18% of the V d amplitude 9 C bypass =8.6pF
Chip micrograph 14 DC pad 2nd stage Transformer 1:2 Using MIM capacitor (1fF/µm 2 ) Bypass capacitor C bypass = 14.5pF 8.6pF Cross-coupling capacitor C cc = 1.5pF
S-parameter measurement results 15 40 0-2 30-4 S21 [db] 20 S22 [db] -6-8 10 0 Sim. Meas. 0 1 2 3 4 5 Frequency [GHz] -10-12 -14 Sim. Meas. 0 1 2 3 4 5 Frequency [GHz] Measurement results are roughly in accordance with simulation results
Measuring system 16 Large signal measurement setup N-3.5mm adopter Input and output losses are measured separately, and are calibrated from results.
Large signal measurement result 17 Near 2.4 GHz PAEmax [%], Psat [dbm] 40 35 30 PAE max 31 % P sat 27 dbm 25 maxpae Psat 20 1.8 2 2.2 2.4 2.6 2.8 Freqency [GHz]
Large signal measurement result 18 2.4 GHz 40 Pout(Meas.) Gain(Meas.) PAE(Meas.) Pout(Sim.) Gain(Sim.) PAE(Sim.) 50 Pout [dbm], Gain [db] 30 40 20 30 10 20 0 10-10 0-30 -20-10 0 10 Pin [dbm] PAE [%] P 1dB = 25 dbm P sat = 27.7 dbm Gain = 26.5 db PAE 1dB = 26.8 % PAE max = 34.3 %
Comparison of CMOS PAs 19 [2] [3] [4] [5] This work Technology 90nm 130nm 180nm CMOS V DD 3.3 V 1.2 V 3.3 V 3.3 V 3.3 V Frequency 2.4 GHz P 1dB 27.7 dbm 24 dbm 24.5 dbm 27 dbm 25.2 dbm P sat 30.1 dbm 27 dbm - 31 dbm 27.7 dbm PAE peak 33 % *32 % 31 %@1dB 27 % 34.3 % Area 4.3 mm 2 1.7 mm 2 1.7 mm 2 2.0 mm 2 1.6 mm 2 * Drain efficiency [2] D. Chowdhury, et al., A Single-Chip Highly Linear 2.4GHz 30dBm Power Amplifier in 90nm CMOS, IEEE International Solid-State Circuits Conference, pp. 378-380, 2008 [3] G. Liu, et al., Fully Integrated CMOS Power Amplifier With Efficiency Enhancement at Power Back-Off, IEEE Journal Of Solid-State Circuits, vol. 43, No. 3, pp. 600-609, Mar. 2008 [4] J. Kang, et al., A Single-Chip Linear CMOS Power Amplifier for 2.4GHz WLAN, IEEE International Solid- State Circuits Conference, pp.761-769, 2006 [5] K. An, et al., A 2.4 GHz Fully Integrated Linear CMOS Power Amplifier With Discrete Power Control, IEEE Microwave and Wireless Components Letter, vol. 19, No. 7, pp. 479-481, July. 2009
Conclusion 20 Designing 2.4GHz PA with high output power Circuit design Using TSMC 0.18µm CMOS process High output power Differential topology, 2-stage configuration, Transformer Improvement of withstanding voltage Cascode, Thick gate-oxide transistor, Self-biased cascode Reduce of area for C bypass Capacitive cross-coupling Results P 1dB = 25.2dBm, P sat = 27.7dBm, PAE peak =34.3% Needed C bypass = 14.5pF 8.6pF(41% )