VLSI Design Lecture 1: Digital Systems and VLSI Shaahinhi Hessabi Department of Computer Engineering Sharif University of Technology Adapted with modifications from lecture notes prepared by the book author (from Prentice Hall PTR)
Overview Why VLSI? Moore s Law. The VLSI design process. IP-based design. Sharif University of Technology Slide 2 of 48
Features of Better Circuit 1. Lower cost t( (chip area, number of fic ICs, ) 2. Better performance (speed) 3. Lower power 4. Better reliability More integration less inter-chip connections better reliability Better testability 5. Better repeatability 6. Less design and fabrication time Sharif University of Technology Slide 3 of 48
Components of an Electronic System Chip (usually a small part of the total cost, but can influence the cost of other parts) Power supply Fan PCB (Printed Circuit Board) Bus Box Sharif University of Technology Slide 4 of 48
Why VLSI? Integration improves the design: lower parasitics = higher speed;» Shorter length of signal transfer is another reason for higher speed (3 cm wire 3*10-2 /3*10 8 = 0.1nsec) lower power (hence better reliability);» Power is a limiting factor for high integration. physically smaller. Integration reduces manufacturing cost -(almost) no manual assembly. Greatly reduces cost of parts other than chip (supply, fan, PCB, ) ASIC might be more expensive than standard IC, but system s cost will be lower. Sharif University of Technology Slide 5 of 48
Levels of Integration SSI MSI LSI VLSI Criteria: Gt Gate count t(2-20, 20 20-200, 200 200-2000, 2000 2000 +); you may see different numbers in literature Pin count Feature size (line widths, line spacing, size) Chip size Function (gate & FF, module, subsystem, system) Sharif University of Technology Slide 6 of 48
Levels of Integration (cont d) Where to go after VLSI? ULSI (Ultra Large Scale Integration - which is between 500,000 and 10,000,000 transistors), GSI (Gigantic Scale Integration - which is over 10,000,000 transistors). Who knows the next step? Maybe: UBSI (Unbelievably Big Scale Integration)! or YWBHLI (You Wouldn't Believe How Large the Integration is)!! Sharif University of Technology Slide 7 of 48
VLSI and you Microprocessors: personal computers; microcontrollers. DRAM/SRAM. Special-purpose processors. Sharif University of Technology Slide 8 of 48
Moore s Law Gordon Moore (co-founder of Intel) predicted that number of transistors per chip would grow exponentially (doubles every 18 months). Exponential improvement in technology is a natural ltrend: steam engines, automobiles. log(#dev) t Obstacles for Moore s law: 1. Quantity and variety of products which use ICs has had less progress. 2. Cost of design verification and test is large. 3. Complexity of design makes it difficult to manage it among design and engineering groups. Role of CAD tools. Sharif University of Technology Slide 9 of 48
Moore s Law plot Sharif University of Technology Slide 10 of 48
Transistors/Intel Microprocessors Sharif University of Technology Slide 11 of 48
Terminology Manufacturing node: technology at a particular channel length. Deep submicron technology: 250-100 nm. Nanometer technology: 100 nm and below. Sharif University of Technology Slide 12 of 48
The cost of fabrication Current cost: $4 billion. Typical fab line occupies about 1 city block, employs a few hundred people. Most profitable period is first 18 months-2 years. Sharif University of Technology Slide 13 of 48
Cost factors in ICs For large-volume ICs: packaging is largest cost; testing is second-largest cost. For low-volume ICs, design costs may swamp all manufacturing costs. IC manufacturing technology is remarkably versatile (h (change masks). k) Wafer size: 12 inch (moving to 18 inch) Chip size: 1.5 X 1.5 cm 2 (moving to 2 X 2) Sharif University of Technology Slide 14 of 48
Cost of design Design cost can be significant: $20 million for a large ASIC, $500 million for a large CPU. Cost elements: Architects, logic designers, etc. CAD tools. Computers the CAD tools run on. Sharif University of Technology Slide 15 of 48
Intellectual property Intellectual property (IP): pre-designed components. May come from outside vendors, internal sources. IP saves time, design cost. IP blocks must be designed to be reused. Sharif University of Technology Slide 16 of 48
Reliability Nanometer technologies require attention to reliability. Design-for-manufacturing (DFM) and design-for-yield (DFY) techniques adjust the design to improve yield. Circuit and architecture techniques can compensate for unreliable components. Sharif University of Technology Slide 17 of 48
The VLSI design process May be part of larger product design. Major levels of abstraction: specification; architecture; logic design; circuit design; layout. Sharif University of Technology Slide 18 of 48
Role oeof Each Level Specification: function, cost, etc. Architecture: large blocks. Logic: gates + registers. Circuits: transistor sizes for speed,,power. Layout: Layout size determines fabrication cost. Shapes determine parasitics; hence the circuit speed and power. Sharif University of Technology Slide 19 of 48
Challenges in VLSI design Multiple levels of abstraction: transistors to CPUs. Multiple and conflicting constraints: low cost and high performance are often at odds. Short design time: Late products are often irrelevant. 6 months delay losing 33% of the profit Sharif University of Technology Slide 20 of 48
Techniques to eliminate unnecessary detail 1. Hierarchical design (divide and conquer, i.e.; breaking the chip into a hierarchy of components, where each consists of a body and a number of pins) 2. Design abstraction (use multiple levels of abstraction) 3. Using CAD tools: tries to solve all 3 mentioned problems; 1. dealing with multiple levels of abstraction is easier when you are not absorbed in the details, 2. computer programs can analyze cost trade-offs much better (because they are methodical) 3. computers are much faster than humans. Sharif University of Technology Slide 21 of 48
CAD Tools Categories 1. Design entry tools (e.g., schematic capture) capture a design in machine-readable form for use by other programs, but don t do any real design work. 2. Analysis and verification tools (e.g., spice) ease the analysis task, but don t tell how to change the circuit for the desired function/spec. 3. Synthesis tools (e.g., Leonardo) create a design at a lower level of abstraction from a higher level description. Both hierarchical design and design abstraction are as important to CAD tools as they are to humans. Sharif University of Technology Slide 22 of 48
Dealing with complexity Divide-and-conquer: limit the number of components you deal with at any one time. Group several components into larger components: transistors form gates; gates form functional units; functional units form processing elements; etc. Sharif University of Technology Slide 23 of 48
Hierarchical name Interior view of a component: components and wires that make it up. Exterior view of a component = type: body; pins. cout a b Full adder cin sum Sharif University of Technology Slide 24 of 48
Instantiating component types Each instance has its own name: add1 (type full adder) add2 (type full adder). Each instance is a separate copy of the type: Add1.a a cout Add1(Full adder) sum Add2.a a Add2(Full adder) sum b cin b cin Sharif University of Technology Slide 25 of 48
A hierarchical logic design box1 box2 x z Sharif University of Technology Slide 26 of 48
Net lists and component lists Net list: net1: top.in1 in1.in net2: i1.out xxx.b topin1: top.n1 xxx.xin1 topin2: top.n2 xxx.xin2 botin1: top.n3 xxx.xin3 net3: xxx.out i2.in outnet: i2.out top.out Component list: top: in1=net1 n1=topin1 n2=topin2 n3=topine out=outnet i1: in=net1 out=net2 xxx: xin1=topin1 i 1 xin2=topin2 xin3=botin1 B=net2 out=net3 i2: in=net3 out=outnet Sharif University of Technology Slide 27 of 48
Component hierarchy top i1 xxx i2 Sharif University of Technology Slide 28 of 48
Hierarchical names Typical hierarchical name: top/i1.foo component pin Sharif University of Technology Slide 29 of 48
Design abstractions English specification Executable program behavior Throughput, h design time function Sequential machines Logic gates registertransfer logic Function units, clock cycles Literals, logic depth cost transistors circuit i nanoseconds rectangles layout microns Sharif University of Technology Slide 30 of 48
Layout and its abstractions Layout for dynamic latch: Sharif University of Technology Slide 31 of 48
Stick diagram V DD D Q' V SS φ φ' ' Sharif University of Technology Slide 32 of 48
Transistor schematic φ' + D Q' φ Sharif University of Technology Slide 33 of 48
Mixed schematic φ' ' D Q' φ inverter Sharif University of Technology Slide 34 of 48
Circuit abstraction Continuous voltages and dtime: Sharif University of Technology Slide 35 of 48
Digital abstraction Discrete levels, discrete time: a a cout sum b a t t b full sum adder cin t b t t a b cout full sum adder cin sum t Sharif University of Technology Slide 36 of 48
Register-transfer abstraction Abstract components, abstract data types: 0010 + 0001 + 0111 0100 Sharif University of Technology Slide 37 of 48
Top-down vs. bottom-up design Top-down design adds functional detail. Create lower levels of abstraction from upper levels. Bottom-up design creates abstractions from low-level level behavior. Good ddesign needs both top-down and dbottom-up efforts. Sharif University of Technology Slide 38 of 48
Design validation Must check at every step that errors haven t been introduced-the longer an error remains, the more expensive it becomes to remove it. Forward checking: compare results of less- and more- abstract stages. Back annotation: copy performance numbers to earlier stages. Sharif University of Technology Slide 39 of 48
Manufacturing test Not the same as design validation: just because the design is right doesn t mean that every chip coming off the line will be right. Must quickly check whether manufacturing defects destroy function of chip. Must also speed-grade. Sharif University of Technology Slide 40 of 48
IP-based design Almost every chip uses some form of IP: Standard cell libraries. Memories. IP blocks. Designers must know how to: Create IP. Use IP. Sharif University of Technology Slide 41 of 48
Types of IP Hard IP: Pre-designed layout. Allows more detailed characterization. Soft IP: No layout---logic l synthesis, etc. IP layout is created by the IP user. Sharif University of Technology Slide 42 of 48
Hard IP Must conform to many standards: Layout pin placement. Layer usage. Transistor sizing. Hard IP blocks are usually qualified on a particular process. Qualification: Component is fabricated and tested t to show that t the IP works on that fab line. Sharif University of Technology Slide 43 of 48
Soft IP Conformance of layout to local standards is easier since it is created by the user. Timing can only be estimated until the layout is done. Must conform to interface standards. A wrapper adapts a block to a new interface. Sharif University of Technology Slide 44 of 48
IP across the design hierarchy Standard cells. Pitch matched in rows, compatible drive. Register-transfer transfer modules. Memories. CPUs. Buses. I/O devices. Sharif University of Technology Slide 45 of 48
Specifying IP Hard or soft? Functionality. Performance, including process corners. Power consumption. Special process features required. Sharif University of Technology Slide 46 of 48
The I/O lifecycle specification HDL design IP creation dtb database extraction characterization ti documentation ti and validation design IP database qualification IP documentation IP modules chip design IP use Sharif University of Technology Slide 47 of 48
Using IP May come from vendor, open source, or internal group. Must identify candidate IP, evaluate for suitability. May have to pay for IP. May want to qualify IP before use, particularly if it pushes analog characteristics. Sharif University of Technology Slide 48 of 48