01 IEEE Proceedings of the 7th Applied Power Electronics Conference and Exposition (APEC 01), Orlando Florida, USA, Febrary 5-9, 01 SWISS Rectifier A ovel Three-Phase Bck-Type PFC Topology for Electric Vehicle Battery Charging T. Soeiro, T. Friedli, J. W. Kolar This material is pblished in order to provide access to research reslts of the Power Electronic Systems Laboratory / D-ITET / ETH Zrich. Internal or personal se of this material is permitted. However, permission to reprint/repblish this material for advertising or promotional prposes or for creating new collective works for resale or redistribtion mst be obtained from the copyright holder. By choosing to view this docment, yo agree to all provisions of the copyright laws protecting it.
SWISS Rectifier A ovel Three-Phase Bck-Type PFC Topology for Electric Vehicle Battery Charging T. B. Soeiro, T. Friedli and J. W. Kolar Power Electronic Systems Laboratory ETH Zrich, Switzerland Email: soeiro@lem.ee.ethz.ch Abstract This paper introdces a novel three-phase bck-type nity power factor rectifier appropriate for high power Electric Vehicle battery charging mains interfaces. The characteristics of the converter, named the SWISS Rectifier, inclding the principle of operation, modlation strategy, sitable control strctre, and dimensioning eqations are described in detail. Additionally, the proposed rectifier is compared to a conventional 6-switch bck-type ac-dc power conversion. According to the reslts, the SWISS Rectifier is the topology of choice for a bck-type PFC. Finally, the feasibility of the SWISS Rectifier concept for bck-type rectifier applications is demonstrated by means of a hardware prototype. I. ITRODUCTIO Charging of Electric Vehicle (EV) batteries inherently reqires conversion of energy from the ac mains into dc qantities. Several charging voltage and power levels have been defined by different standardization organizations (IEC 61851, IEC6196, SAE J177). Single-phase Power Factor Corrector (PFC) mains interfaces are commonly employed for low charging power levels (e.g. P < 5 kw), whereas for higher power levels, three-phase PFC mains interfaces have to be applied [1]. The EV chargers, typically implemented as two-stage systems, i.e. comprising a PFC rectifier inpt stage followed by a dc-dc converter, can be either integrated into the car (on-board) or accommodated in specially designed EV charging stations (off-board) []. In the particlar case of fast charging stations (off-board), the power electronic system shold be able to garantee voltage adaptation to cope with different specifications of several types of vehicles. Typically, for three-phase 400 V or 480 V (line-to-line rms voltage) ac mains, EV chargers with a dc-bs voltage in the range of 50 V to 450 V are sed [1]. Bck-type three-phase PFC rectifiers are appropriate for high power EV chargers (> 5 kw), as a direct connection to the dc-bs can be sed. If isolation of the dc-bs from the PFC rectifier is reqired for safety reasons, this can be facilitated by an isolated dc-dc converter connected in series, which can additionally be sed for voltage reglation. Compared to boost-type topologies, bck-type systems provide a wider otpt voltage control range, while maintaining PFC capability at the inpt, enable direct startp, and allow for dynamic crrent limitation at the otpt []- [7]. Three-phase boost rectifiers prodce an otpt voltage (typ. 700 V to 800 V) that is too high to directly feed the dcbs of EVs and ths reqire a step-down dc-dc converter at their otpt. This paper presents a novel three-phase bck-type PFC rectifier topology, referred to as the SWISS Rectifier (cf. Fig. 1), appropriate for high power EV battery charging systems. Other sitable applications inclde spplies for dc power distribtion systems in telecommnication, ftre more electric aircraft, variable speed ac drives, and high power lighting systems. The SWISS Rectifier was first introdced in [7] and [8], however, only a brief description of the rectifier concept was given. In this paper, after the explanation of the principle of operation of the new rectifier topology, which employs a three-phase active third harmonic injection rectifier, in Section II, the derivation of the inpt crrent space vectors and the calclation of the relative on-times of the active switches garanteeing PFC operation are presented in Section III. A PWM-control method sing trianglar carriers is proposed in Section IV. The analytical expressions for Fig. 1: Circit topology of the proposed three-phase SWISS Rectifier with LC inpt filter. Fig. : Circit topology of a three-phase 6-switch bck-type PFC rectifier with LC inpt filter and explicit freewheeling diode D FW. 978-1-4577-116-6/1/$6.00 01 IEEE 617
calclating the stresses of the main semicondctors and passive components in dependency on the inpt crrent amplitde and the voltage transfer ratio of the converter are given in Section V. A 7.5 kw SWISS Rectifier is designed to attest the feasibility of the proposed rectifier concept. Finally, in Section VI, the SWISS Rectifier is systematically compared with a 6-switch bck-type PFC rectifier, shown in Fig., which represents the standard three-phase bck-type topology. II. OVEL THREE-PHASE BUCK-TYPE PFC RECTIFIER A novel three-phase PFC rectifier soltion combining bck dc-dc converters and an active rd harmonic crrent injection circit, referred to here as the SWISS Rectifier, is shown in Fig. 1. Other rd harmonic injection topologies are described in [9]-[11], inclding the dal converter of the SWISS rectifier, a boost-type rectifier. The SWISS Rectifier allows the crrents in the positive and negative active switches, i T+ and i T-, to be formed proportionally to the two phase voltages involved in the formation of the otpt voltage of the diode bridge. If the difference of i T+ and i T- is fed back into the mains phase with the crrently smallest absolte voltage vale via a crrent injection network, formed with three for-qadrant switches gated at twice the mains freqency, a sinsoidal inpt crrent shape can be assred for all mains phases while the dc-dc converters garantee the otpt voltage reglation. A circit implementation with a single otpt indctor is feasible, however, in the proposed circit, shown in Fig. 1, the total dc indctance is split evenly between the positive and negative otpt bs in order to provide symmetric attenation impedances for condcted common mode noise. The condction losses in the freewheeling state cold be redced by implementation of an additional freewheeling diode D FW as is shown for the 6-switch bck-type PFC rectifier in Fig.. For the SWISS Rectifier, the otpt voltage range is limited by the minimal vale of the six-plse diode bridge otpt voltage, given by (1) and therefore is identical to the otpt voltage range for the 6-switch bck-type PFC rectifier, shown in Fig.. Contrary to the 6-switch bck-type PFC systems, the rectifier diodes of the SWISS Rectifier are not commted with switching freqency. Correspondingly, the condction losses can be redced employing devices with a low forward voltage drop (and a higher reverse recovery time). In addition, the mains commtated injection switches cold be implemented with an anti-parallel connection of RB- IGBTs with a low forward voltage drop. pn, l (1) l, rms III. CODUCTIO STATES, MODULATIO, AD DUTY CYCLE CALCULATIO For the analysis of the condction states, the derivation of the crrent space vectors and the calclation of the relative trn-on times, symmetric mains conditions are assmed. The mains crrents i a,b,c are considered to be eqal to the fndamental component of the rectifier inpt crrents i r,a,b,c,(1). Hence, the reactive crrents de to the filter capacitors are also neglected. Moreover, the filter capacitor voltages CF,a,b,c at the inpt of the rectifier are considered prely sinsoidally shaped and in phase with the mains voltages a,b,c. The crrent in the dc indctors I is assmed to be constant. Finally, all the analyses consider one of the twelve 0 -wide sectors of the mains period, i.e. 0 < φ < 0 with φ = ω t which is characterized by the mains phase relation a > b > c. For the remaining sectors, the calclations can be performed in a similar manner. The modlation of the crrent injection circit is performed at low freqency, following the rectifier inpt voltages CF,a,b,c in sch a way that the active crrent injection occrs always into only one mains phase as presented in Tab. I (cf. Fig. ). Accordingly, in each of the 0 -wide sectors of the mains period, for different condction states can be defined by the switches T + and T - within a plse period T P, where the dc crrent I impressed by the dc indctors is distribted to two of the inpt phases or is kept in a freewheeling state. The rectifying discrete converter inpt crrent space vector can be calclated by 600 400 00 0-00 -400 j j4 ir ira, e irb, e i. () rc, -600 0.5 0.6667 0.8 1 1.1666 1. 1.5 1.6666 1.8 1.9999.1666..5 x 10 5 Fig. : Mains sectors 1 to 1 defined by the different relations of the instantaneos vales of the mains phase voltages a,b,c. TABLE I: Modlation of the crrent injection circit (cf. Fig. 4). Sector S y1 S y S y Sector S y1 S y S y 0-0 0 1 0 180-10 0 1 0 0-60 0 1 0 10-40 0 1 0 60-90 1 0 0 40-70 1 0 0 90-10 1 0 0 70-00 1 0 0 10-150 0 0 1 00-0 0 0 1 150-180 0 0 1 0-60 0 0 1 Fig. 4(a) presents the for condction states of the SWISS Rectifier for the interval φ [0, 0 ]. For the switching state j = (O, O), where j = (T +, T - ) indicates a combination of the switching fnctions of the two fast switches (T + and T - ) and O means that the respective switch is trned on, while OFF indicates an off-state of the switch, the rectifier inpt crrents are i r,a = I, i r,b = 0, and i r,c = -I. Therefore, the rectifier inpt crrent space vector for this switching state reslts in i I e j 6 r,( O, O). () Analogosly, the three remaining space vectors can be calclated as 618
i I e j 6 r,( O, OFF), (4) i I e j r,( OFF, O), (5) i. (6) r,( OFF, OFF) 0 With these for space vectors, a reslting inpt crrent space vector i * r can be formed [cf. Fig. 4(b)] so that it is in phase with the mains voltage vector * r and has the reqired amplitde according to the actal power demand. The proper selection of the switching state seqences allows control over the crrent ripple i of the dc indctor crrent I and i y of the phase injection crrent i y. Accordingly, the converter can be modlated in order to minimize the crrent ripple of i y or that of the indctor crrent I. For the first mains sector (0 < φ < 0 ), the SWISS Rectifier can operate with minimal injection crrent ripple i y and conseqently lower ripple vales of the inpt capacitor voltages CF,a,b,c if a vector modlation with the switching seqence (O, O) - (O, OFF) - (OFF, OFF) - (O, OFF) - (O, O), arranged symmetrically arond the middle of the plse interval, is applied [cf. Fig. 5(a)]. As can be seen in Fig. 5(a), the inpt phase crrents are formed by segments of the dc crrent I defined by the relative on-times k i of the crrent vectors i I k k ; i I k ; i I k. (7) r, a 1 r, b r, c 1 The otpt voltage pn is formed by the line-to-line voltages ab and ac rated by the relative on-time of the respective crrent vectors k k. (8) pn 1 ac ab ote that the otpt voltage range is limited by the minimal vale of the six-plse diode bridge otpt voltage pn, l. (9) l, rms Finally, PFC operation in the first mains sector can be achieved with relative on-times k i, reliant on the modlation a) b) Fig. 5: Modlation scheme for a) minimal injection crrent ripple i y or b) minimal dc crrent ripple i for φ [0, 0 ]. index M, the instantaneos vales of a,b,c, and the amplitde of the mains phase voltages Û given by pn M, (10) Uˆ k1 M, k M, and k4 1 M. (11) U ˆc ˆb U ˆa U ote that the switch dty cycles α + (for transistor T + ) and α - (for transistor T - ) for symmetric mains ( a + b + c = 0) are defined according to pn pn a b c k1 k, (1) Uˆ Uˆ a) b) Fig. 4: a) Condction states and b) inpt crrent space vector diagram of the SWISS Rectifier for φ [0, 0 ]. 619
pn c k 1 Uˆ. (1) Alternatively, for the first mains sector (0 < φ < 0 ), the SWISS Rectifier can operate with minimized dc indctor crrent ripple i and conseqently redced ripple vales of the otpt low-pass filtering if a vector modlation with the switching seqence (O, OFF) - (O, O) - (OFF, O) - (O, O) - (O, OFF), arranged symmetrically arond the middle of the plse interval, is applied [cf. Fig. 5(b)]. As can be seen in Fig. 5(b), the (locale average) inpt phase crrents are defined by the dc crrent I and the relative on-times k i of the crrent vectors ir, a I k1k ; ir, b I kk ; ir, c I k1 k.(14) The otpt voltage pn is formed by the line-to-line voltages ab, bc, and ac, weighted by the relative on-times of the respective crrent vectors pn k 1 ac kab kbc. (15) Finally, PFC operation in the first mains sector can be achieved with relative on-times k i, dependent on the modlation index M, instantaneos inpt voltage vales a,b,c, and the amplitde of the mains phase voltages Û given by k 1 M, k 1 M, ac k11kkm 1. (16) U U U ˆ ˆc ˆa allows the system to work similarly as if it wold be controlled with the vector modlation described in Fig. 5(a), where the crrent ripple i y is minimized while i is maximized. On the other hand, operation sing carriers with a phase difference of 180 (interleaved carriers) permits the system to work similarly as if it wold be controlled with the vector modlation depicted in Fig. 5(b), where the dc crrent ripple i is minimized while i y is maximized. Simlation reslts, depicting the principle of operation of the SWISS Rectifier, are shown in Fig. 7. The converter specifications, given in Tab. II, are considered in the simlation where operation with in-phase or interleaved PWM carriers and a load step (from.75 kw to 7.5 kw) are presented. As can be observed, the reslts demonstrate that the line crrents i a,b,c can effectively follow the sinsoidal inpt phase voltages a,b,c even in case of load steps, attesting the feasibility of the proposed rectifier and PWM control. TABLE II: SWISS Rectifier prototype specifications. Inpt phase voltage a,b,c Mains freqency f Switching freqency f P Rated otpt power P 0 Otpt capacitor C indctor L 0 V rms ±10% 50 Hz 6 khz 7.5 kw 470 µf 05 µh PWM COTROL SCHEME IV. A possible implementation of a control scheme for the SWISS Rectifier is shown in Fig. 6. This feedback PWM control comprises a sperimposed otpt voltage controller R(s) and a sbordinate otpt crrent controller G(s). Finally, a feed-forward loop adds the normalized modlation fnctions defined by the positive and negative diode bridge otpt voltage and the system otpt voltage reference vale * pn to the dc crrent controllers in order to directly generate the inpt crrent forming voltage. In the proposed control strctre, setting the PWM modlator for T + and T - to operate with in-phase carriers Fig. 7: Simlation reslts of the SWISS rectifier operating with (I) in-phase or (II) interleaved PWM carriers; (III) load step from 50% to 100% of the rated otpt power (.75 kw to 7.5 kw). Fig. 6: PWM control strctre for the SWISS Rectifier. V. SWISS RECTIFIER SYSTEM DESIG In this section, in order to provide a clear and general gideline for the components selection for the SWISS Rectifier design, the stresses of the active and passive components of the converter are calclated analytically with dependence on the operating parameters of the rectifier. As an application 60
case, a 7.5 kw nity power factor rectifier system shall be dimensioned that shold provide a constant otpt voltage of pn = 400 V for operation at a mains with 0 Vrms phase voltage ( a,rms = 0 V ±10%) and a switching freqency of f P = 6 khz. A. Semicondctor Voltage and Crrent Stresses The maximm voltage stress on the line diodes, D + and D -, is defined by the line-to-line voltage,l-l,max 110% 60V. (17) D,max, l l,max a, rms All the remaining semicondctors (T +, T -, D F+, D F-, and S y ) have to block a maximm voltage which corresponds to the 60 sinsoidal progression of the maximm line-to-line inpt voltage,l-l,max DF,max T,max Sy,max, l l,max 57V. (18) ote that the selections of the blocking voltage capability of the power transistors and diodes have to consider a additional safety margin δ for ndesirable oscillations of the rectifier inpt voltage in case of low passive damping of the inpt filter. Therefore, 100 V power diodes and IGBTs (55% > δ > 48%) or 900 V MOSFETs (δ 40%) are sitable for the fll silicon implementation of the SWISS Rectifier. In order to determine the on-state losses of the semicondctors, the crrent rms and average vales have to be calclated and therefore, simple analytical approximations are derived. For the following calclations, it is assmed that the rectifier has a prely sinsoidal phase crrent shape, ohmic fndamental mains behavior, a constant dc crrent I, no low-freqency voltage drop across the inpt filter indctors, therefore C,a,b,c = a,b,c, and a switching freqency f P >> f. 1) Crrent Stress of the Bidirectional Switches S y and D y With a defined modlation index M, the average and rms crrents of the two transistors and diodes forming a bidirectional switch finally reslt in and I Dy I, avg M Sy I Dy I, rms M Sy. (19) ) Crrent Stress of the Rectifier Diodes D + and D - The average and rms crrents of the rectifier diodes can be calclated as and ID, avg IM I D, rms M I. (0) ) Crrent Stress of the Fast Diodes D F+ and D F- The average and rms crrents of the fast freewheeling diodes can be determined as IDF, avg I 1 M and IDF, rms I 1 M. (1) 4) Crrent Stress of the Power Transistors T + and T - The average and rms crrents of the PWM modlated power transistors are determined by ITavg, IM and M I T, rms I. () B. Passive Components: Voltage and Crrent Stresses 1) Indctor L The voltage across each of the dc indctors L is eqivalent to half of the vale of the maximm allowed lineto-line inpt voltage,l-l,max l, l,max L L, ll,maxl 10V. () The crrent flowing throgh L is defined by the fll dc (load) crrent I and a crrent ripple Δi L,pp,max which is limited to a given vale, i.e. 5% of I. The crrent ripple peak-to-peak vale and the rms vale of the dc indctor crrent, Δi L,pp and i L,rms, can be determined as follows P0 I, (4) pn pn 1 M ilpp,,max, (5) L fp i Lpp,,max ilrms, I. (6) 18 The indctance vale of the dc indctor can then be selected according to pn 1 M L. (7) ilpp,,max fp ) Otpt Capacitor C When selecting the otpt capacitor C, the vale of the controlled otpt voltage pn and an additional over-shoot margin to enable safe operation dring load transients (arond 10% of pn ), mst be taken into consideration C 1.1 440V. (8) pn The rms vale of the otpt capacitor crrent ripple Δi C,rms and the peak-to-peak vale of the otpt voltage ripple Δ C,pp are given by ilpp,,max pn icrms, and 1 M C, pp. (9) 18 L 8 fp C The capacitance vale of the dc otpt capacitor can then be determined according to pn 1 M C. (0) L 8 fp C, pp,max C. Simple DM and CM oise Models of the SWISS Rectifier The semicondctors of a power electronics converter are typically monted on a common heat sink which is sally connected to grond (PE). Therefore, parasitic capacitances to grond exist, leading to propagation of common-mode (CM) noise crrents in the circit (cf. Fig. 8). 61
De to the discontinos inpt crrent of the SWISS Rectifier, at least a single-stage differential mode (DM) inpt filter, i.e. L F,i and C F,i, is necessary. However, for fll compliance to EMC standards [1], the condcted DM and CM noise emissions propagating to the mains have to be attenated sfficiently. In order to design a proper EMI filter, the CM and DM noise levels of the SWISS Rectifier need to be determined. Accordingly, the modeling approach given in [1] and [1] is extended to this three-phase converter. The DM noise is generated by the plsating inpt crrents i r,a,b,c at switching freqency and is attenated by the inpt filter capacitors C F,a,b,c and the ac side filter indctors L F,a,b,c. The CM noise is cased within each plse period T P by the switched line-to-line voltages dring the formation of the otpt voltage and for the distribtion of the dc crrent to the mains phases. For the SWISS Rectifier, this plsed voltage CM has a maximm high freqency peak-to-peak amplitde U CM,pp,max of approximately UCM, pp, max. (1) a, rms 8 Fig. 8 defines the simplified circits to evalate CM and DM noise sorces for the SWISS Rectifier. There, the CM voltage CM, the DM crrent i DM, and the stray capacitances, C g and C Eq, model the power converter CM and DM noise circits. The capacitances C g and C Eq are lmped representations of all relevant stray capacitances inclded in the CM propagation path. C g represents mainly the capacitances of the positive and negative otpt voltage bs to grond C pn, and from the load to earth C 0, while C Eq models the stray capacitances from the semicondctors to the heatsink (C D, C Sy, C T, and C DF ) and the power connection terminals to earth, C XZ. a) b) c) Fig. 8: a) Model for the propagation of the common mode crrents in the SWISS Rectifier sed for deriving the CM noise model. Simplified highfreqency model for b) CM and c) DM emissions, inclding the highfreqency eqivalent circit of the LIS and a single stage DM inpt filter with parasitics of indctive and capacitive elements shown. A simplified time domain simlation of the system is sfficient to obtain the DM crrent and CM voltage sorces, i DM and CM. The CM voltage can be calclated by measring the voltages X,PE and Z,PE, X, PE Z, PE CM, () and the DM crrents are compted directly from the inpt crrents as long as no CM paths exist in the simlation circit. For simplicity, the crrent measred in phase a is sed so that i i. () DM r, a A simlation of the SWISS Rectifier in GeckoCIRCUITs [14] is sed for determining the CM and DM noise sorces. The converter specifications listed in Tab. II are sed to perform the simlation. The time behavior of the CM voltage CM and DM crrent i DM for both space vector modlations described in Section III are presented in Fig. 9, where it can be seen that the CM voltage is formed with combinations of the inpt voltages, while the DM crrent is formed by the switched dc crrent I. Finally, the low freqency component i DM,(1) shows a nearly ideal sinsoidal behavior, ths PFC at the inpt of the converter is obtained. It can be observed that the different modlation strategies reslt in different CM and DM waveforms which wold finally lead to different EMI filter reqirements. As an example, by comparing the calclated DM noise emissions for both modlations to the CISPR Class B limit at f = 180 khz (first mltiple of the switching freqency (f P = 6 khz) within the EMC measrement band), the reqired sppression for the EMI filter can be determined. As a reslt, with qasi-peak measrement (QP), the necessary attenation of noise for the modlation, which minimizes the ripple i y, is Att req = 75 db, while for the modlation, which minimizes the ripple i, the necessary noise sppression is slightly higher, i.e. Att req = 78 db. De to the high reqired filter attenations a second filter stage is recommended. For control stability reasons, the attenation of the first stage filter, L F,a,b,c and C F,a,b,c, has to be higher than for the second stage. As a design criteria, the sppression of the first DM filter stage will be considered as follows (cf. [1]) AttLF, CF[ db] 0.7,...,0.8 Attreq[dB]. (4) Additionally, the selection of needs to limit the voltage ripple peak-to-peak vale across C F,i to abot 5% to 10% in order to ensre correct detection of the inpt line-to-line voltages that is reqired for the system modlation [1]. On the other hand, high vales of C F,i lead to a low power factor at low load operation, therefore, as a compromise the vale of C F,i is defined in the range CFi, (μf,...,1μf). (5) Finally, the range of the indctance vale of the filter indctors can be determined for Att req [db] = 78 db L AttLF, CF [ db]/0 10 Fi, 4 CFi, f 180kHz (μh,...,44μh). (6) 6
500 a b c CM 0-500 0 0 10 0-10 i DM,(1) i DM CM,(1) 4 ms/div -0 4 ms/div -0 a) Time b) Fig. 9: Time behavior of the CM voltage CM and DM crrent i DM noise sorces of the SWISS Rectifier operating with modlation a) for minimal injection crrent ripple i y [cf. Fig. 5(a)] and b) for minimal dc indctor crrent ripple i [cf. Fig. 5(b)]. D. Swiss Rectifier Model Accracy In order to verify the accracy of the derived eqations modeling the voltage and crrent stresses of the SWISS Rectifier, an appropriate switching freqency and the vales of the passive components according to (7), (0), (5), and (6) have been selected. A switching freqency of f P = 6 khz is designated as it constittes a good compromise between high efficiency, high power density, and high control bandwidth. Advantageosly, the forth switching freqency harmonic is fond near, bt still below the beginning of the considered the EMC measrement range at 150 khz. With f P = 6 khz, the vales for the otpt filter L = 05 µh and C = 470 µf are selected. The component vales of the first inpt filter stage is L F,i = 85 µh and C F,i = 4.4 µf. In Tab. III, the vales of the average and rms component stresses calclated with the respective expressions are compared to the reslts obtained with a simlation performed in GeckoCIRCUITs [14] and show a very good accracy. TABLE III: SWISS Rectifier: comparison of active and passive component stresses determined by analytical calclations and digital simlations. Analytical Calclations Simlation Deviation [%] I Sy,avg 0.66 0.68 -.94 I Sy,rms.51.57-1.68 I D,avg 4.4 4. +0.47 I D,rms 8.91 8.91 0.00 I T,avg 1.71 1.68 +0.4 I T,rms 15.44 15.44 0.00 I DF,avg 6.04 6.06 +0. I DF,rms 10.64 10.67 +0.8 i L,rms 18.78 18.78 0.00 Δi L,pp,max 4.66 4.57 +1.97 Δi C,rms 1.10 1.1 -.65 E. 7.5 kw Hardware Demonstrator A laboratory prototype of the SWISS Rectifier according to the specifications given in Tab. II has been bilt. The implemented prototype is shown in Fig. 10. The overall dimensions of the system are 10 mm x 1 mm x 9 mm, hence leading to a power density of.94 kw/dm. For nominal operation, the total efficiency is approximately 96.5%. ote that for the selection of the 7.5 kw SWISS Rectifier components, the analytical eqations (17)-(6) were tilized, considering the worst case operating condition for each specific component. For instance, the semicondctors have to cope with the highest crrent stress which occrs at the maximm modlation index (M 0.91). According to (17) and (18), IGBTs and diodes with a blocking voltage capability of 100 V have been chosen. In respect of the operating principle of the converter, the injection switches S y,i are implemented with latest generation Trench and Fieldstop (T&FS) IGBTs (100 V / 5 A, IKW510, Infineon) with an anti-parallel freewheeling diode that are optimized for low condction losses as they are switched with only twice the mains freqency. For the transistors T + and T -, high-speed T&FS IGBTs (100 V / 40 A, IGW4010H, Infineon) are sed in combination with SiC MPS diodes (100 V / 0 A, CD010A, CREE) for D F+ and D F to enable low switching losses at the selected switching freqency of f P = 6 khz (cf. Fig. 11). A list of the employed semicondctor devices and passive components is given in Tab. IV along with the key design parameters. Fig. 10: Implemented 7.5 kw SWISS Rectifier hardware prototype, sing 100 V Trench and Fieldstop IGBTs and 100 V SiC MPS freewheeling diodes. (Mechanical dimensions: 10 mm x 1 mm x 9 mm; power density:.94 kw/dm = 48 W/in, switching freqency: f P = 6 khz.). 6
TABLE IV: Selected main components of the SWISS Rectifier hardware prototype (cf. Fig. 10). Component Device Description S y / D y Si T&FS IGBTs, 100 V / 5 A, IKW510, Infineon T + / T - Si HighSpeed T&FS IGBTs, IGW4010H, Infineon D + / D - Si fast recovery diode, DSEP060-1AR, IXYS D F+ / D F- SiC Schottky diodes, 100 V / 0 A, CD010A, CREE L 05 µh, x E64-50-10 cores, C91 ferrite, Ferrox Cbe L = 16 trns, C wire cross section A w,l = 8.5 mm C 10 x 47 µf / 450 V, electrolytic capacitors, EPCOS L F,abc 85 µh, High Flx 5854 powder core, Magnetics Lf = trns, C wire cross section A w,lf =.1 mm x. µf, 05 V X, MKP foil, Arcotronics C F,abc VI. COMPARATIVE EVALUATIO In order to evalate and compare the SWISS Rectifier, specified according to Tab. II with a standard bck-type acdc converter, i.e. the 6-switch bck-type PFC rectifier (cf. Fig. ), several normalized performance indices are defined according to [7, 8]. Based on these performance metrics, a comparative evalation of the proposed systems is performed graphically, as illstrated in Fig. 11. The power devices listed in Tab. IV are sed for the assessment. An advantageos system wold preferably cover the smallest area in the selected graphical representation. DM oise [dbµv] 1-η [%] CM oise [dbµv] 4.8 4.0 Transistor Condction Loss [W]..4 1.6 0.8 145 140 15 10 15 10 144 147 150 Transistor Switching Loss [W] Diode Condction Loss [W] 0.8 Capacitor I n 0.0 Crrent Stress I Rated Indctor Power 70 65 60 55 50 45 15 18 0. 141 0.4 0.6 0.01 0.0 0.0 0.0 LILIL, pkpk fs Po 110 95 0 40 170 155 140 15 60 0.04 0.05 0.06 80 100 10 6-Switch Bck Rectifier Swiss Rectifier Crmsn,, Fig. 11: Comparative evalation of the Swiss Rectifier with the 6-switch bck-type rectifier. (The more advantageos system covers the smaller area in the diagram.) The main advantage of the SWISS Rectifier is not only seen in the slightly higher achievable efficiency bt also that the system can be controlled similar to a dc-dc converter. Accordingly, basic knowledge of the fnction of a bck-type dc-dc converter and a three-phase passive diode rectifier is sfficient to implement a three-phase PFC rectifier with sinsoidal inpt crrents and a controlled otpt voltage. VII. COCLUSIO This paper proposes a novel three-phase nity power factor bck-type PFC rectifier, named the SWISS Rectifier, appropriate not only for high power EV battery charging systems, bt also for power spplies for telecommnication, o ftre more electric aircraft, variable speed ac drives, and high power lighting systems. The complete design procedre of this system based on analytical expressions of the crrent stresses of the active and passive power components, inclding a simplified EMI DM/CM modeling for condcted emission and filter design, as well as the control analysis, has been described. Additionally, a 7.5 kw SWISS Rectifier hardware prototype has been implemented. Finally, the new rectifier concept has been compared with a conventional 6-switch bck-type PFC rectifier. According to the reslts, the SWISS Rectifier is a very sitable topology for the implementation of a bck-type PFC mains interface for an EV battery charger. REFERECES [1] D. Aggeler, F. Canales, H. Zelaya, A. Coccia,. Btcher, and O. Apeldoorn, Ultra-Fast -Charger Infrastrctres for EV-Mobility and Ftre Smart Grids, in Proc. Innovative Smart Grid Techn. Conf. Erope (ISGT 010), 010. [] A. Kperman, U. Levy, J. Goren, A. Zafranski and A. Savernin, High Power Li-Ion Battery Charger for Electric Vehicle, in Proc. 7th Int. Conf. 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