DATE 2006 Special Session: DFM/DFY Design for Manufacturability and Yield - Influence of Process Variations in Digital, Analog and Mixed-Signal Circuit Design DATE 06 Munich, March 8th, 2006 Presenter Dept Titel presentation Date Page 1
Outline Trouble in Chipmaker s Paradise Mismatch Impact on Circuit Design for Advanced Technologies Circuit Simulation and Yield Optimization Methods History of Requirements from Circuit Designers Sizing and Yield-Optimization Flow Inway 5.x/Powerflow Summary and Outlook Page 2
The Major Drivers of Chip Design Performance Yield Power Chip Design Time-to-Market Area Page 3 thanks to E. Barke
Trouble in Chipmaker s Paradise Data from 4 logic companies show initial yield has not improved from the 0.5 µm to 180 nm generation Yield learning rates also have not improved and mature yields have declined Page 4 Thanks to Uwe Gäbler
Trouble in Chipmaker s Paradise: Yield Ramp and Final Yields 1 0,9 0,8 0,7 Page 5 Yield [%] 0,6 0,5 0,4 0,3 0,2 0,1 250nm 250nm technology 180nm 180nm technology Initial yield decreasing 130nm 130nm technology 1998 2004 90nm < 90nm technology? 0 0 10 20 30 40 50 60 70 time Yield history for several logic manufacturers Mature yield decreasing
Where We Have To Go High mature yield Yield [%] Higher initial yield Steeper ramp-up Page 6 Time [Months]
On-Chip Variation Technology Node 180 nm 130 nm 90 nm (to be validated) 65 nm (estimated) On-Chip- Variation (*) 8 13 % 22 % 30 40 % 45 55 % Page 7 (*) 3-σ limits of V th
Limits: Mismatch Impact on Circuit Design for Advanced Technologies 160 3 σ Vth Local Variations Gate Area: minimum / relaxed (4fold min.) 3 Voltage Supply and Threshold Voltage 3 σ (Vth) [ mv ] 120 80 40 Voltage [ V ] 2 1 Vdd / V Vth / V 0 250nm 180nm 130nm 90nm 65nm 0 250nm 180nm 130nm 90nm 65nm Technology Technology Page 8 Reduction of available voltage range Reduction (scaling) of transistor area Increasing transistor mismatch High effort to maintain circuit accuracy Thanks to Ulrich Schaper
Circuit Simulation and Yield Optimization Methods EDA Method Tools Complexity expenses & influence on design process; statistical background know how needed SPICE Models expenses & completeness of device models; Design Centering Special statistical Tools high high Monte-Carlo Simulation Sensitivity / Tolerance Analysis Worst- / Best-Corner Analysis Page 9 Nominal Simulation Analog Simulator low low Thanks to B. Lemaitre
Circuit Simulation and Yield Optimization Methods EDA Method Tools Complexity expenses & influence on design process; statistical background know how needed SPICE Models expenses & completeness of device models; Design Centering (parametric yield optimization) Monte-Carlo Simulation (simulation of parameter distributions local & global variations) Sensitivity / Tolerance Analysis (automatic or by discrete differences) Special Statistical Tools high parametric yield optimization process & circuit distributions process & circuit sensitivities; robust design high all MC models physical meaningful device models Page 10 Worst- / Best-Corner Analysis (distribution outside simulator) Nominal Simulation Analog Simulator low process & circuit margins; under- overestimation nominal point low worst case nominal Thanks to B. Lemaitre
Developments of Compact Models 1000 BSIM4v4 No. of Model Parameters 100 10 earlyekv BSIM3v3 MM11v2 BSIM3v2 HiSIM 1.2.0 BSIM2 HSP28 PSP BSIM3v3 BSIM BSIM3v2 BSIM4 BSIM2 PCIM HSP28 SP BSIM3v1 MM9 LEVEL2 BSIM EKV3 EKV2.6 LEVEL3 EKV LEVEL1 Including L,W,P scaling Without scaling 1 1960 1970 1980 1990 2000 2010 Years Page 11 Number of DC model parameters vs. year of introduction of the model Significant growth of parameter number that includes geometry (W/L) scaling How can we handle the complexity (without tools)? Thanks to W. Grabinski
History of Requirements from Circuit Designers (cont.) Corner analysis not suited for analog behavior and mismatch-dominated effects Monte-Carlo analysis (without & with operating conditions) no information on how to tune design parameters to improve yield Contributor identification Note: Contributor identification does not necessarily describe the impact on yield! Restricted to statistical parameters (and not designables, operating parameters, bias-currents,...) Page 12
Monte Carlo: Effort of Yield Estimation Verification of a yield Y > Y min with 95% confidence: Y min 98% 99.9% 99.997% 1 Y min 2% 0.1% 0.003% β w 2σ 3σ 4σ Rem.: for 99% confidence, about 1.7 N simulations are needed N 150 3 000 100 000 # Simulations 10 Mrd 100 Mio 1 Mio 10.000 100 N c 2 / (1 Y min ) 2 3 4 5 6 7 β w Page 13 Better methods needed for very robust circuits: Deterministic tolerance analysis and worst-case points Importance sampling / stratified sampling MunEDA GmbH
DfM: Why Non-Monte-Carlo-Methods? Cost Comparison: Yield Analysis with WCDs vs. Monte-Carlo 10 Mrd Highly-robust circuits Basics MC WCD Sizing Apps Page 14 # Simulations 100 Mio 1 Mio 10.000 Note: 3σ means that for a 100Mio 100 transistor design 100000 (!!!) transistors may fail! Monte-Carlo Yield analysis using WCDs 2 3 4 5 6 7 97.7% 99.9% 99.997% Advantage Worst-Case-Distances (WCDs): More efficient and accurate than MC for yield > 3σ (99,9%) often asked for β w resp. σ MunEDA GmbH
History of Requirements from Circuit Designers (cont.) Page 15 Corner analysis not suited for analog behavior and mismatch-dominated effects Monte-Carlo analysis (without & with operating conditions) no information on how to tune design parameters to improve yield Contributor identification Note: Contributor identification does not necessarily describe the impact on yield! Restricted to statistical parameters (and not designables, operating parameters, bias-currents,...) Yield sensitivities Worst-case points, distances and circuit performance linearization Yield optimization Nominal sizing
Methodology Development (IFX-DfY & public R&D projects): Sizing and Yield-Optimization Flow Inway 5.x/Powerflow Page 16 Constraints Part I: Schematic Preparation Constraints Part II: Testbench Setup Constraints Part III: Setup of Performance Extraction Constraints Part IV: Performance Specification and Sizing Constraints Backannotation Design Centering and Analysis Nominal Sizing and Analysis Statistical Setup for Mismatch and Process Parameters
Selected References from >200 WiCkeD Optimization Projects within Infineon RF Design, High-Speed Analog, High-Speed Digital, Automotive Power, Embedded Memory, Enhanced Digital Cell Library Modeling Application Field RF Design High-Speed Analog High-Speed Digital Automotive Power Circuit Design Task (IFX-Project) Coilless LNA for GSM Power supply for RF circuits RF input amplifiers (LNA) and comparators for) High-speed serial memory interface Bias chain for A/D conversion 4GHz Master-Slave Flip-Flop of Advanced Memory Buffer Interface Digital Carry Select Adder Comparator in SMART5 Technology Page 17 Embedded Memory Enh. Digital Cell Library Modeling 6T SRAM - 6sigma design Statistical static timing analysis for L90 logic (SSTA)
Testbench and Schematic of the Comparator Circuit Operating conditions: Performances: Supply Voltage U_LH: from 6.0 V to 7.0 V (nominal 6.6 V) Temperature Range: from 0 C to 80 C (nominal 27 C) Offset upper: 2 mv Offset lower: -2 mv Page 18 19 MOSFETs, 2 bipolar transistors: Current Mirror Level Shifter Differential-pair
WiCkeD Reference Projects Design Problem & Consequences Solution & Results using WiCkeD Comparator circuit in SMART5 technology Initial design: Performances too low (offset, temperature sensitive, matching problem) Overall design yield: < 5% WiCkeD Using WiCkeD s optimization engines: Feasibility, Nominal Sizing and Yield Optimization Total setup & optimization time using 4 hosts: 3 hours Yield improvement after Nominal Optimization: <5% 78% Yield optimization with design centering: 78% 92,6% yield Verified with Monte-Carlo Significant performance improvements for offset, gain (35dB 57dB) and others Page 19 Yield ramp-up from <5% 92 % in 3 hours
Overview: Circuit Analysis and Optimization Steps Simulation Node (& MC: initial yield 5%) Feasibility Optimization: all constraints fulfilled Nominal Optimization: constraints and performances fulfilled & performances optimized Yield Optimization Monte-Carlo Analysis (yield verification) total yield = 78% Page 20 Monte-Carlo Analysis total yield = 92.6% Simulation with rounded design parameters
Design for [X] Umbrella - Df[X] Source: Semiconductor International, June 2005 DFY P DFY S DFY R DFR DFD DFT Page 21 Parametric Systematic Examples: Performance Leakage Misalignment... Random Reliability Example: Library optimization Diagnostics Test Example: Fault Coverage / Models
Yield as the 4 th Design Target Chip behavior in Face of Environmental and Manufacturing Variations Functional / Systematic Yield Yield Parametric (digital & analog) Yield Page 22 Functional Yield Analysis Critical Area, Printability Layout, design style & litho dependent performance DfM-Aware Physical Design Redundant via insertion Wire bending / spreading OPC (Optical proximity correction) / PSM (Phase Shift Mask) aware routing Layout Restrictions Transistor orientation restricted to improve manufacturing control Address Process and Environmental Variations Digital Statistical timing/power (SSTA) Timing aware OPC & PSM Statistical Physical Design Adaptive Chip design Analog Design Centering by Statistical Analog Simulation, Monte-Carlo & Non-Monte-Carlo (e.g. WiCkeD) Thanks to B. Lemaitre
Summary and Outlook Page 23 Monte-Carlo analysis is suited for yield estimation. Computational effort to ensure high yields is considerable enormous (is the better word) Extensions of MC-analysis allow for handling operating conditions as well as to perform a contributor identification Worst-Case methods are superior to MC-methods with respect to efficiency, post processing possibilities e.g. for design centering Structural constraints help to obtain better results from the optimization, especially e.g. robustness (performances w.r.t. variation of operating parameters) and computational effort for the optimization loop No push-button solution available, but we are working towards improvement of user-friendliness
Summary and Outlook Page 24 Design and technology are in equal measure responsible for yield. Close collaboration is more and more crucial for business success. Systematic yield loss is a big problem. Combined efforts of design and manufacturing groups are necessary for improvements here. First time right is essential. Don t throw a design over the fence and look if it works. Every carelessness will cost valuable ramp-up time. Yield maximization should have higher priority than pure cost optimization. Cost reduction measures are only effective in a mature situation. Simulator costs and resources: Methodology training mandatory & use your brain to avoid computational pain! (i.e. before you activate thousands of simulations) Thanks to R. Schledz
Outlook: Design Abstraction Levels Challenges for DfY SYSTEM + DfY methodology and tools future challenge MODULE Page 25 Digital SSTA and Analog/Mixed-Signal ( SABM ) S n+ G GATE CIRCUIT DfY methodology and tools available today DEVICE D n+