Experiment 6 Electrnic Switching Purpse: In this experiment we will discuss ways in which analg devices can be used t create binary signals. Binary signals can take n nly tw states: high and lw. The activities in this experiment shw hw we can use analg devices (such as p-amps and transistrs) t create signals that take n nly tw states. This is the basis fr the digital electrnics cmpnents we will examine in this experiment. Backgrund: Befre ding this experiment, students shuld be able t Analyze simple circuits cnsisting f cmbinatins f resistrs, inductrs, capacitrs and p-amps. Measure resistance using a Multimeter and capacitance using a cmmercial impedance bridge. D a transient (time dependent) simulatin f circuits using Capture/PSpice D a DC sweep simulatin f circuits using Capture/PSpice. Determine the general cmplex transfer functin fr circuits. Build simple circuits cnsisting f cmbinatins f resistrs, inductrs, capacitrs, and p-amps n prtbards and measure input and utput vltages vs. time. Review the backgrund fr the previus experiments. Learning Outcmes: Students will be able t Set-up and use a transistr as an electrical switch and identify when and why it is ON and OFF. Demnstrate that transistrs can be used t amplify electrical signals. Set-up and use an p-amp as a cmparatr and identify when and why it changes utput state. Set-up and use an p-amp as a Schmitt Trigger and identify when and why it changes utput state. Demnstrate the peratin f cmmercial Cmparatr and Schmitt Trigger integrated circuits. Set-up and perate a circuit that includes a cntrl signal, a digital device and a transistr t cntrl a mechanical relay. Equipment Required: DMM (Optinal) Analg Discvery (with Wavefrms sftware) Oscillscpe (Analg Discvery) Functin Generatr (Analg Discvery) 2N2222 (Transistr), 7414 (Schmitt Trigger), 7404 (Inverter), LED, & the usual cmpnents. Helpful links fr this experiment, including required reading, can be fund n the links page fr this curse. Of particular imprtance is the dcument n Electrnic Switching (the tpic f this experiment). Pre-Lab Required Reading: Befre beginning the lab, at least ne team member must read ver and be generally acquainted with this dcument and the ther required reading materials listed under Experiment 6 n the EILinks page. Hand-Drawn Circuit Diagrams: Befre beginning the lab, hand-drawn circuit diagrams must be prepared fr all circuits either t be analyzed using PSpice r physically built and characterized using yur Analg Discvery bard. K.A. Cnnr, S. Bnner, P. Schch - 1 -
Part A Transistr Switches Backgrund Transistrs: A transistr, pictured in Figure A-1, is an electrically cntrlled semicnductr switch. The switch cnnects the Cllectr t the Emitter. The signal at the Base clses and pens the switch. Nte: Pay attentin t the cnnectin marked with the red arrw. Placing the transistr in the wrng rientatin is a cmmn errr. Figure A-1. In an ideal transistr mdel, the signal at the Base is nt part f the circuit; it simply pens r clses the cnnectin between the Cllectr and the Emitter. In an npn transistr like the ne pictured, when the switch is pen, n current flws frm the Cllectr t the Emitter and, when the switch is clsed, a current flws frm the Cllectr t the Emitter. Hence, the transistr needs t be riented in the circuit s that the Cllectr pints twards the surce and the Emitter pints twards grund. Nte that the black arrw in the transistr symbl, lcated inside the circle n the Emitter leg shws the directin f current flw. T get the switch t pen, we place a lw vltage at the base (less than abut 0.7V). T get the switch t clse, we place a high vltage at the Base (greater than abut 0.7V). There are different kinds f transistrs that have slightly different characteristics. In this curse, we use the npn. Transistrs have three perating regins. When the vltage acrss the base-emitter is lw, the current is nt allwed t flw frm cllectr t emitter. This regin is called the cutff regin. When the base-emitter vltage is high, the current flws freely frm cllectr t emitter. This is called the saturatin regin. There is als a third regin that ccurs when the input vltage t the base is arund 0.7V. In this regin, the transistr is changing state between allwing n current t flw and allwing all current t flw. At this time, the current between cllectr and emitter is prprtinal t the current at the base. The regin is called the active regin. Over this small range f vltages, the transistr can be used as a current amplifier. Experiment The Transistr: In this part f the experiment, we will use PSpice t lk at the behavir f a transistr when it is being used as a switch. Using PSpice, set up the circuit shwn in Figure A-2. Nte that there are tw vltage surces. V1 cntrls the base vltage and V2 prvides vltage at the cllectr s that current can flw when the switch is clsed. Make sure yu use the Q2N2222 and nt the 2N2222 transistr in yur PSpice parts library. K.A. Cnnr, S. Bnner, P. Schch - 2 -
Figure A-2. Figure A-3. Run a DC sweep simulatin. Set up a DC SWEEP fr V1 frm 0.2 t 9V (step = 0.005V). Place vltage markers at Vin, Vb, Vc and Ve. The transistr Q1 is acting as a switch in the lp with resistr R2 and vltage V2. The vltage V1 and resistr R1 are used t turn the switch ON r OFF. The transistr switch will nt wrk exactly like an ideal, simple switch. Hwever, it can be a gd apprximatin t such a switch and, mre imprtantly, it will switch states based n an applied vltage rather than a mechanical act (like turning a switch n and ff). Identify n the plt where the transistr is in the cutff regin (OFF) and in the saturatin regin (ON). Include this plt in yur reprt. Nw we will cnsider this switch in a cnfiguratin that switches the vltage acrss a lad. Add the resistr R3 as shwn in Figure A-3 t yur circuit. The transistr switch, when pen, allws the maximum vltage t ccur acrss R3. When the switch is clsed, the vltage acrss R3 ges t near zer. Run yur simulatin again and print yur utput. Include this plt in yur reprt. What is a typical vltage acrss R3 when the switch is OFF? What is a typical vltage acrss R3 when the switch is ON? Frm what yu knw abut vltage dividers, d yu think that these values make sense? Nw we want t take a clser lk at the range f V1 fr which the transistr is in the active regin and the switch is neither ON nr OFF. Remve the vltage markers frm yur circuit. Place current markers n the cllectr, emitter, and base leads f the transistr. Rerun yur PROBE result but change the sweep fr V1 t range frm 0.2V t 0.9V. Use traces t nrmalize all three currents by dividing them by the current at the base I(Q1:b) r IB(Q1). Als, negate the nrmalized emitter current s that all three traces are psitive. Yu shuld be able t identify a small range f vltages fr which the nrmalized magnitude f the cllectr and emitter currents are apprximately cnstant at arund 170 times the base current. Use the cursrs t find this range. Indicate the range n yur plt. Generate the plt and include it with yur reprt. This is the active regin fr which the transistr circuit acts like a very gd amplifier. Here it has a current gain f much mre than 100. The gain is nt a simple cnstant, nr is it as large as we can btain with an p-amp. Summary By lking at the peratin f a simple transistr circuit, we have seen that there 3 ranges f input vltages fr which it lks like: 1) a switch that is OFF, 2) an amplifier, and 3) a switch that is ON. K.A. Cnnr, S. Bnner, P. Schch - 3 -
Part B Cmparatrs and Schmitt Triggers Backgrund Cmparatrs: An p-amp can be used t create a binary signal with nly tw states. An p-amp has an extremely high intrinsic gain (f abut 10 6 ). With n negative feedback t stabilize its behavir, the utput f an p-amp is this huge intrinsic gain multiplied by the difference between the tw inputs. If the nn-inverting input is slightly higher than the inverting input, the p-amp will saturate in the psitive directin. If the inverting input is slightly higher than the nn-inverting input, it will saturate negative. The p-amp with n feedback has tw states, and therefre, it is a binary device. The value f the utput is limited by V CC. Thus, the utput shuld g t abut +V CC whenever the net input is psitive and t -V CC whenever the net input is negative. The net input is determined by cmparing the vltage at the psitive (+) terminal t the vltage at the negative (-) terminal. When V + > V - then V ut = V CC and when V + < V - then V ut = -V CC. We call this p-amp cnfiguratin a cmparatr because its state is determined using a cmparisn f the tw inputs. In this experiment, cmparatrs are used t cmpare an input t sme reference vltage, V ref. If the net difference between the input and V ref switches sign, then the cmparatr will switch state. A cmparatr can be inverting (when V ref is cnnected t the nn-inverting input) r nninverting (when V ref is cnnected t the inverting input). Schmitt Triggers: Cmparatrs d nt give a reliable signal in the presence f nise because the utput vltage swings between psitive and negative whenever the net input crsses the reference vltage, V ref. It wuld be mre useful t have a cmparatr-type circuit that switches utput state when the net input exceeds sme finite threshld buffer arund V ref rather than the reference vltage itself. The Schmitt trigger makes this pssible. In a Schmitt trigger, T upper and T lwer are the upper and lwer threshlds that define the buffer area arund V ref, and B upper and B lwer are cnstants that define the size f the buffer area. The utput f the trigger will switch when the input exceeds T upper = V ref + B upper r is less than T lwer = V ref - B lwer. The size f the buffer area is called the hysteresis and it is given by T upper - T lwer. We can mdel a Schmitt trigger using an p-amp circuit. In this mdel, the tw threshlds, T upper and T lwer, are determined using a vltage divider in the psitive feedback path f the Schmitt trigger mdel. Because Schmitt triggers use feedback frm the utput t create the hysteresis, they are always inverting. PSpice Experiment The Cmparatr: First we will examine the behavir f a simple cmparatr that changes state when the input ges abve r belw a cnstant vltage. Build the circuit in Figure B-1 using PSpice. Use Vsin fr V1, set it fr Hz and an amplitude f 5V. 5Vdc V3 U1 3 + OS2 Vin V1 2 - ua741 7 V+ V- 4 OUT OS1 5 6 1 Vut -5Vdc V2 RL Figure B-1. Run a transient simulatin. K.A. Cnnr, S. Bnner, P. Schch - 4 -
Run the simulatin frm 0 t 3ms with a time step f 1us. Generate a plt f yur utput, shwing the surce vltage V1 and the lad vltage (pin 6 f the p-amp). Include this plt in yur reprt. Nte that the pint at which the input and utput signals crss is nt the pint in time when the cmparatr starts t switch states. Yu can see by clsely examining the plt that the p-amp starts t change state when the input signal crsses zer. The saturatin vltage is the vltage level that the utput reaches when the p-amp is saturated. What are the psitive and negative saturatin vltages f the p-amp? Add a 1V reference vltage t the cmparatr as shwn in Figure B-2 belw. 5Vdc V3 Vin V1 3 2 ua741 U1 + - 7 V+ V- OS2 OUT OS1 5 6 1 Vut 1Vdc V4-5Vdc 4 V2 RL Figure B-2. Run a transient simulatin. Rerun the simulatin frm 0 t 3ms with a time step f 1us. Generate a plt f yur utput, shwing the surce vltage V1 and the lad vltage (pin 6 f the p-amp). Include this plt in yur reprt. Nte the value that the input signal is crssing when the cmparatr starts t change state. Is it at a different input vltage than circuit B1? Hw des it cmpare t the reference vltage f 1V? Nw lk at the saturatin vltages f the utput. Are they the same as in circuit B1? Saturatin vltages are a characteristic f the p-amp itself, s these shuld nt change. Schmitt Trigger: Nw we will examine a mdel f a Schmitt trigger. Build the circuit in Figure B-3 using PSpice. R5 R4 4k 5Vdc V3 Vin 3 2 ua741 U1 + - 7 V+ V- OS2 OUT OS1 5 6 1 Vut V1-5Vdc 4 V2 RL Nw simulate this circuit. Figure B-3. K.A. Cnnr, S. Bnner, P. Schch - 5 -
Use the same transient analysis as abve. Generate ne plt, again shwing the surce vltage V1 and the utput vltage (pin 6). Include this plt in yur reprt. The reference vltage fr this circuit is zer. Des the utput change when the input crsses the reference vltage? What is the value f the input vltage when the utput starts t change state frm high t lw? What is the value f the input vltage when the utput starts t change state frm lw t high? These are the values f the threshld vltages fr the circuit, T upper and T lwer. What is the hysteresis? Yu can calculate the threshlds, T upper and T lwer, frm the circuit diagram by using the vltage divider frmed by R4 and R5. If the utput is saturated psitive, at +5V, what will be the vltage at the nninverting input f the p-amp? The p-amp is cmparing the input vltage, V1, t this value. This must be the psitive threshld, T upper. What happens when the utput is saturated negative, at -5V? This is the negative threshld, T lwer. A Schmitt Trigger can be further generalized by adding a reference vltage t the vltage divider at the nninverting input. Mdify the Schmitt trigger mdel by adding a 1V surce as shwn belw: 1Vdc R5 V5 R4 4k 5Vdc V3 Vin 3 2 ua741 U1 + - 7 V+ V- OS2 OUT OS1 5 6 1 Vut V1-5Vdc 4 V2 RL Figure B-4. Simulate this circuit. Use the same transient analysis as abve. Generate ne plt, again shwing the surce vltage V1 and the utput vltage (pin 6). Include this plt in yur reprt. What is the reference vltage fr this circuit? Des the utput switch states when the input crsses the reference vltage? What are the values f the upper and lwer threshlds f this circuit? Are they the same as circuit B-3? Why nt? What is the hysteresis? Yu can use a vltage divider t calculate the upper and lwer threshlds f this circuit as well. Use the methd described in the class ntes t d s. Summary An p-amp can be used t create binary devices. The cmparatr, a single p-amp with n feedback, is the simplest f these. The cmparatr can be used t cmpare a signal t zer r t any reference vltage. The cmparatr des nt wrk well in the presence f nise. A mre cmplicated p-amp circuit, that slves this prblem, can be created by adding a vltage divider t the nn-inverting input f the p-amp. This creates a threshld abve and belw the reference vltage arund which the p-amp will nt switch state. Such an p-amp cnfiguratin is called a Schmitt trigger. K.A. Cnnr, S. Bnner, P. Schch - 6 -
Part C Digital Switching Digital chips: Digital chips are electrnic devices that perfrm lgic peratins n binary signals. This type f chip frms the basis fr all digital cmputers. There are digital chips that are designed using the same principals as bth the Schmitt trigger and the cmparatr. A Schmitt trigger inverter is a digital versin f the Schmitt trigger and an inverter is a digital versin f the cmparatr. These chips are slightly mre restrictive than the p-amp mdels because they are based n digital cnventins. Therefre, by cnventin, the high pwer vltage, +Vcc, is 5V and the lw pwer vltage, Vcc, is 0V. The switching vltage lies at a pint between lw and high. We will examine where this pint is in this part f the experiment. Just like p-amps, all digital chips must be supplied with tw pwer vltages, +5V and 0V. By cnventin, these cnnectins are always made at the lwer left hand crner (0V) and the upper right hand crner (5V) f the chip. In fact, these cnventins are s cmmn in digital chips, that PSpice des nt require that yu make them. It just assumes they are made. On yur prtbard, hwever, yu must make the cnnectins. The SN7414: The SN7414 chip pictured in Figure C-1 cntains six Schmitt trigger inverters. The inputs are designated by na and the crrespnding utput by ny, where n is an integer frm 1 t 6. By cnventin, pin 7 is attached t grund and pin 14 is attached t Vcc = 5V. Figure C-1. The purpse f the Schmitt trigger inverter is t cnvert an analg vltage int a binary digital vltage. When the input vltage f the SN7414 exceeds a threshld, V T+, the device utput switches t LOGIC 0 (0V); the input vltage must drp belw a secnd threshld, V T-, fr the utput t switch back t LOGIC 1 (5V). The difference in threshlds (called hysteresis) is very imprtant in preventing false triggering n nise. The device is als inverting, but the Schmitt trigger inverter des nt behave in the same manner as the inverter. Yu can find mre infrmatin abut this chip n the spec sheets fr the 7414 lcated n the links page fr the curse. The SN7404: This chip cntains six inverters. The purpse f the chip is t invert a binary signal. The pinut is exactly the same as the Schmitt trigger inverter, but this chip is nt designed t handle analg signals. It assumes the input takes n ne f tw distinct values: LOW (smewhere near 0V) and HIGH (smewhere near 5V). There is a grey area between a cutff fr LOW, V IL, and a secnd cutff fr HIGH, V IH. The inverter is nt designed t functin crrectly in this area. Yu can find mre infrmatin abut this chip n the spec sheet fr the 7404 lcated n the links page fr the curse. The VPULSE surce: In this experiment, yu will need t understand a new type f surce in PSpice. It is used t create trapezidal pulses, as pictured in Figure C-2. It can als mdel specialized versins f the trapezid, such as square waves and triangular waves. The VPULSE surce has several parameters. V1 is the lwest pint n the pulse (the vltage at the base f the trapezid). V2 is the highest pint n the pulse (the vltage at the tp f the trapezid). TD is an initial time yu can set t delay the start f the wave. (This is usually 0.) TR and TF stand fr rise time and fall time. These indicate hw much time shuld be spent transitining frm V1 t V2 and frm V2 t V1, respectively. These determine the slpe f the sides f the trapezid. The PW parameter, pulse width, is the time spent at the cnstant high vltage, V2. This defines the width f the tp f the trapezid. The final K.A. Cnnr, S. Bnner, P. Schch - 7 -
parameter, PER, is the perid f the whle signal. The amunt f time between trapezidal pulses is PER - (TR+PW+TF). Figure C-2. Fr example, in the pulse abve, the perid is 3ms, the rise and fall times are 0.5ms and the pulse width is 1ms. The VPULSE surce is lcated in the SOURCE library in PSpice. PSpice Experiment Cmparing the Schmitt Trigger and the Cmparatr in the presence f nise: Nw we will use Pspice t simulate a circuit that uses the SN7404 and the SN7414 t cmpare the behavir f the inverter t the Schmitt trigger inverter in the presence f nise. We will use tw vltage surces t simulate a nisy signal. Create the circuit in Figure C-3 in Pspice. U1A 1 2 7404 R1 V V U2A 1 2 0 VOFF = 1.5 VAMPL = 1.5 FREQ = VOFF = 0 VAMPL = 0.2 FREQ = 100k V3 V2 7414 V R2 0 0 Figure C-3. Simulate this circuit. Fr V3, use an ffset f 1.5V, an amplitude f 1.5V and a frequency f Hz. Fr V2, use n ffset, an amplitude f 0.2V and a frequency f 100kHz. Run the simulatin fr 1.5ms using a step size f 1us. Plt bth utputs alng with the input signal. Include this plt in yur reprt. Determine what the input vltage is when the utput f the inverter changes state. This is V ref fr the digital cmparatr. Yu will need t chse a new time scale arund each f the transitin pints r use the magnifier t find the exact vltage. What is the simulated nise ding t the utput f the inverter? Is there any hysteresis arund V ref at all? Check t be sure that the inverter perfrms as it shuld by lking up the characteristics f the SN7404 n the links page. (See page 5: V IH and V IL.) Fr what range f vltages shuld the device nt invert crrectly? Determine the value f the input vltage when the utput f the Schmitt trigger changes state. (Find T upper and T lwer.) Yu will need t chse a new time scale arund each f the transitin pints r use the magnifier t find the exact vltages. What is the hysteresis f the Schmitt trigger? K.A. Cnnr, S. Bnner, P. Schch - 8 -
Check t be sure that the Schmitt trigger device perfrms as it shuld by lking up the characteristics f the SN7414 n curse links page. (See page 4: V T+, V T-, and hysteresis). What are the typical switching threshlds and hysteresis fr this device? Des the PSpice simulatin wrk as expected? Using the Schmitt trigger and the inverter t cntrl a transistr switch: In the fllwing simulatin, we will use the cmparatr and the Schmitt trigger t pen and clse a transistr switch. Wire the circuit in Figure C-4 in PSpice. Nte that there are tw identical circuits in this diagram: ne cntaining an inverter and the ther a Schmitt trigger inverter. The VPULSE pulse shuld range between 0 and 5V. The rise and fall times shuld be 0.5ms. The pulse width shuld be 1ms. The ttal perid shuld be 3ms. R5 U4A 1 2 R6 Q2 V R4 7414 Q2N2222 V1 = 0 V2 = 5 TD = 0 TR = 0.5m TF = 0.5m PW = 1m PER = 3m V1 0 V U3A 1 2 7404 R3 Q1 Q2N2222 0 V R1 R2 5v V2 0 Figure C-4. 0 Run a simulatin. Create a simulatin fr this circuit. Use a run time f 3ms and a step size f 3us. This shuld shw a single input pulse. Run the simulatin. Mark the lcatins n the plt where the Schmitt trigger causes transistr Q2 t switch. Mark the lcatins n the plt where the inverter causes the transistr Q1 t switch. Generate this plt and include it in yur reprt. What is the vltage at the utput vltage marker when transistr Q2 is pen? Why is it at this vltage? Alter the values f the resistrs t change the magnitude f the utput vltage. Change R2 and R5 t 100Ω. Als change R1 and R4 t 10kΩ. Rerun the simulatin. What happened t the magnitude f the utput vltage when transistr Q2 is pen? Why did this happen? Summary The Schmitt trigger and the cmparatr are bth used in digital circuitry. The Schmitt trigger inverter is used t cnvert an analg signal t a digital signal. It als inverts the signal. The inverter is used t invert a digital signal. Whereas the Schmitt trigger wrks as expected in the presence f nise, the inverter des nt wrk well in the area between the range f vltages crrespnding t LOGIC 1 and the range f vltages crrespnding t LOGIC 0. K.A. Cnnr, S. Bnner, P. Schch - 9 -
Part D Relay Circuit Relays: A relay is an electrically perated switch. (See Wikipedia http://en.wikipedia.rg/wiki/relay.) A PSpice mdel f a cmmn cnfiguratin is shwn in Figure D-1 When n current is flwing thrugh the inductr between the pins cnnected t the cil, the switch remains in the nrmally clsed (NC) psitin. Hwever, when current flws thrugh the inductr, it frces the switch t change t the nrmally pen (NO) psitin. The switch itself is attracted by the electrmagnet created by the inductr. When the relay switches state, yu can hear a little click. Figure D-1. Figure D-2. The pinuts fr tw f the relays we use are shwn in Figure D-2 (Tyc T7C & Ct 8L series). Depending upn the brand f relay yu have, the pinut may be different. All relay manufacturers prvide pinut infrmatin n their device spec sheets. The Ct is a reed relay, which is als perated by a magnetic field, but generally much smaller than fr typical electrmechanical relays like the Tyc. Experiment Building a switching circuit: T see hw practical transistr switches can be, we will use the circuit yu simulated in PSpice t shw hw it can cntrl a relay. NOTE: Yu will initially nt build the circuit with the relay. Rather, an LED will be filling in fr the relay. LEDs, like all dides, nly wrk when cnnected with the crrect rientatin (see figure D-3). Figure D-3 Figure D-4.1 shws the mst standard cnfiguratin fr a simple relay circuit. There is n need fr the resistr usually used t cnnect between the transistr cllectr and the +5V surce because relay cils have significant resistance. The T7C relay shwn abve has a cil resistance f 70Ω. The relay cil is als an inductr, s it is necessary t add the dide t prtect the rest f the circuit. Recall that anytime di we try t rapidly change the current in an inductr, we get a large vltage spike V = L. The dide prvides a dt path fr the current t ramp dwn r up mre slwly. See http://electrnicsclub.inf/dides.htm. Build the circuit in Figure D-4.2 n yur prtbard. Nte that this is half f the circuit yu built using PSpice in part C with an LED added and n lad resistr. The value f the 510Ω resistr is chsen t limit the LED current. Yu will learn mre abut this in a future experiment. Instead f building the circuit twice, we can use the fact that bth types f inverters have the same pinut and swap the chips in and ut t bserve their prperties. This circuit uses V+ = 5V pwer frm Analg Discvery. It als requires a variable input vltage. Here we will use ne f the functin generatrs, W1, running at a frequency f 1Hz, fr the variable vltage. Set up W1 t prduce the same vltage used in the PSpice simulatin (triangular wave varying frm 0V t 3V). Bth the input vltages fr PSpice and Analg Discvery are shwn at the end f this sectin. K.A. Cnnr, S. Bnner, P. Schch - 10 -
+5V LED D R2 510 D1 V1 = 3 V2 = 0 TD = 0 A B U1A R4 1 2 V1 7414 Q1 C Q2N2222 5Vdc V2 TR = 0.5s TF = 0.5s PW = 0 PER = 1s 0 Figure D-4.1 Figure D-4.2 When the transistr switch is pen, there is n current thrugh R2 r D1 and the LED will be ff. When the transistr switch is clsed, there will be current thrugh R2 and D1 and the LED will be n. What level f input vltage at pint A will turn the transistr n and ff? (Recall that bth the 7414 and 7404 are inverters) At what input vltage V1 did the LED turn ff? This gives us T upper. At what input vltage V1 did the LED turn n? This gives us T lwer. Are the switching vltages yu fund cnsistent with yur knwledge f Schmitt triggers? T understand better what it means t be abve the upper threshld and belw the lwer threshld, we will fill ut the table belw. Fr an input vltage f 3V (chsen t be abve T upper ), recrd the vltage levels at pints A, B, C and D in the table belw. There are nt enugh scillscpe inputs t recrd all f these vltages simultaneusly. Yu shuld measure the vltage at A using channel 1+ and then mve the cnnectin fr channel 2+ t pints B, C and D in turn t measure the ther vltages. Be sure t cnnect the Analg Discvery grund and the negative cnnectins fr the tw channels (1- & 2-) t yur circuit. Save the plts f bth channel vltages fr each f the three cases and include them in yur reprt. Fr an input vltage f 0V (chsen t be belw T lwer ) recrd the vltage levels at pints A, B, C, and D in the table. abve upper threshld belw lwer threshld A B C D Nw take ut the Schmitt trigger inverter and replace it with a SN7404 inverter chip. What d yu think will happen t the relay nw? Repeat the three measurements (A&B, A&C, A&D) and save the plts fr yur reprt. Yu d nt have t fill ut a table fr the inverter. Hw are the results different than fr the Schmitt trigger inverter? Finally, take ut the inverter and put back the Schmitt trigger. Remve the 510Ω resistr (R2) and the LED and replace them with the cil frm a Ct Reed Relay (8L01-05-001). This must als be signed ut fr the day like the accelermeters were fr Exp5, Prj 2. Place a 1N4148 dide acrss the relay as shwn abve. When everything is turned n again, yu shuld be able t hear the relay quietly click. Demnstrate t a TA and btain a signature verifying that the relay is wrking. Return the relay when yu are finished. K.A. Cnnr, S. Bnner, P. Schch - 11 -
PSpice & Analg Discvery Plts fr Figure D-4.2: Fr cmpleteness, the input vltages fr PSpice (D-4.2.1) and Analg Discvery (D-4.2.2) are shwn belw. Remember that digital devices (lgic gates, etc.) wrk with input and utput vltages between 0V and V CC. Thus, the input vltages shuld nt g negative. Fr the PSpice results, the net alias feature was used s that the measured vltages can have well-defined and easy t recgnize names. It is a gd idea t use this feature if yu can. Figure D-4.2.1 Figure D-4.2.2 Reminder: Be sure t read the dcument n Electrnic Switching fund under Experiment 6 n the curse website. Identifying Lgic Chips: The numbering f chips is nt always bvius. Smetimes the numbers are cntinuus; smetimes they are separated by letters. Summary In this part f the experiment we built a circuit using three electrical switches: an inverter, a Schmitt trigger and a transistr. We als cnsidered a mechanical switch: a relay that uses an electrmagnet t pen and clse its cntacts. K.A. Cnnr, S. Bnner, P. Schch - 12 -
Checklist and Cnclusins The fllwing shuld be included in yur experimental checklist. Everything shuld be labeled and easy t find. Credit will be deducted fr pr labeling r unclear presentatin. ALL PLOTS SHOULD INDICATE WHICH TRACE CORRESPONDS TO THE SIGNAL AT WHICH POINT AND ALL KEY FEATURES SHOULD BE LABELED. Hand-Drawn Circuit Diagrams fr all circuits that are t be analyzed using PSpice r physically built and characterized using yur Analg Discvery bard. Part A Transistr Switches (20 pints) Include the fllwing plts: 1. PSpice DC sweep f transistr circuit with cutff and saturatin indicated. (3 pt) 2. PSpice DC sweep f transistr circuit with vltage divided. (3 pt) 3. PSpice plt f nrmalized currents with active regin marked. (3 pt) Answer the fllwing questins: 1. Draw a simplified circuit diagram fr plt 1 abve that includes just V2, R2 and a simple switch t represent the transistr. (2 pt) 2. Fr yur simplified circuit, when the switch is pen (OFF), hw much vltage will there be at Vc? When the switch is clsed (ON), hw much vltage will be at Vc? (2 pt) 3. What is a typical vltage acrss R3 in plt 2 abve when the switch is OFF? What is a typical vltage acrss R3 in plt 2 abve when the switch is ON? (2 pt) 4. Why d yu think that the values in the previus questin 3 make sense? (2 pt) 5. Fr what range f input vltages did the transistr act like a current amplifier? (Where was there a direct relatinship between base current and the current frm cllectr t emitter?) Abut what was the amplificatin? (3 pt) Part B Cmparatrs and Schmitt Triggers (20 pints) Include the fllwing plts: 1. PSpice transient fr the cmparatr with 0V reference vltage. (1 pt) 2. PSpice transient fr the cmparatr with 1V reference vltage. (1 pt) 3. PSpice transient fr Schmitt trigger with 0V reference vltage. (1 pt) 4. PSpice transient fr Schmitt trigger with 1V reference vltage. (1 pt) Answer the fllwing questins: 1. At what input vltage level des the cmparatr in plt 1. abve switch states? (1 pt) 2. At what input vltage level des the cmparatr in plt 2. abve switch states? (1 pt) 3. What are the switching threshlds f the input fr the Schmitt trigger in plt 3. abve? What is the hysteresis? (3 pt) 4. Use a vltage divider t prve that the values in the previus questin 3. make sense. (4 pt) 5. What are the switching threshlds f the input fr the Schmitt trigger in plt 4. abve? What is the hysteresis? (3 pt) 6. Use a vltage divider t prve that the values in the previus questin 5. make sense. (4 pt) Part C Digital Switching (20 pints) Include the fllwing plts: 1. PSpice transient f Schmitt trigger and inverter in the presence f nise. (1 pt) 2. PSpice transient f Schmitt trigger and inverter switching transistrs with transitin pints marked. (3 pt) Answer the fllwing questins: 1. Frm plt 1, between what input vltages des the inverter seem t be unable t find a stable utput? (2 pt) K.A. Cnnr, S. Bnner, P. Schch - 13 -
2. Hw d the values yu fund fr the perating regin f the inverter cmpare t the values f V IH and V IL yu fund n the spec sheet fr the device? (2 pt) 3. Frm plt 1, at what input vltage level des the Schmitt trigger switch frm lw t high? Frm plt 1, at what input vltage level des the Schmitt trigger switch frm high t lw? What is the hysteresis? (3 pt) 4. Hw d the values yu fund fr the threshlds and hysteresis f the Schmitt trigger cmpare t the values f V T+, V T-, and hysteresis yu fund n the spec sheet fr the device? (2 pt) 5. At what input vltage des the transistr switch in plt 2 abve clse and pen when using the inverter? (2 pt) 6. At what input vltage des the transistr switch in plt 2 abve clse and pen when using the Schmitt trigger? (2 pt) 7. What effect did changing the values f the resistrs R1, R2, R4 and R5 have n the utput vltage? Why? (2 pt) 8. Why d yu think the Schmitt trigger is preferable t an inverter in the presence f nise? (1 pt) Part D Relay Circuit (12 pints) Include the fllwing plts (5 pt): 1. Table f data pints A, B, C & D. 2. The vltages vs time at pints A & B, A & C, A & D fr bth the Schmitt Trigger and Inverter. Answer the fllwing questins: 1. At what input vltage did the Schmitt trigger tggle the LED as yu increased the vltage? (2 pt) 2. At what input vltage did the Schmitt trigger tggle the LED as yu decreased the vltage? (2 pt) 3. Is the range fund in questins 1 and 2 cnsistent with yur PSpice results? (1 pt) 4. When the LED is replaced by the relay, did yu bserve the same tggle vltages? (1 pt) 5. At what input vltage did the inverter tggle the LED? (1 pt) Frmat (8 pints) 1. Organizatin and cmpleteness f reprt, infrmatin in rder f experiments. (6 pt) 2. List member respnsibilities (see belw) (2 pt) List grup member respnsibilities. Nte that this is a list f respnsibilities, nt a list f what each partner did. It is very imprtant that yu divide the respnsibility fr each aspect f the experiment s that it is clear wh will make sure that it is cmpleted. Respnsibilities include, but are nt limited t, reading the full write up befre the first class; cllecting all infrmatin and writing the reprt; building circuits and cllecting data (i.e. ding the experiment); setting up and running the simulatins; cmparing the thery, experiment and simulatin t develp the practical mdel f whatever system is being addressed, etc. K.A. Cnnr, S. Bnner, P. Schch - 14 -
Summary/Overview (0 t -10 pts) There are tw parts t this sectin, bth f which require revisiting everything dne n this experiment and addressing brad issues. Grading fr this sectin wrks a bit differently in that the verall reprt grade will be reduced if the respnses are nt satisfactry. 1. Applicatin: Identify at least ne applicatin f the cntent addressed in this experiment. That is, find an engineered system, device, prcess that is based, at least in part, n what yu have learned. Yu must identify the fundamental system and then describe at least ne practical applicatin. 2. Engineering Design Prcess: Describe the fundamental math and science (ideal) picture f the system, device, and prcess yu address in part 1 and the key infrmatin yu btained frm experiment and simulatin. Cmpare and cntrast the results frm each f the task areas (math and science, experiment, simulatin) and then generate ne r tw cnclusins fr the practical applicatin. That is, hw des the practical system mdel differ frm the riginal ideal? Be specific and quantitative. Fr example, all systems wrk as specified in a limited perating range. Be sure t define this range. Ttal: 80 pints fr experiment packet 0 t -10 pints fr Summary/Overview 20 pints fr attendance 100 pints Attendance (20 pssible pints) 2 classes (20 pints), 1 class (10 pints), 0 class (0 pints) Minus 5 pints fr each late. N attendance at all = N grade fr this experiment. K.A. Cnnr, S. Bnner, P. Schch - 15 -
Experiment 6 Sectin: Reprt Grade: Name Name Checklist w/ Signatures fr Main Cncepts Fr all plts that require a signature belw, yu must explain t the TA r instructr: the purpse f the data (using yur hand-drawn circuit diagram), what infrmatin is cntained in the plt and why yu believe that the plt is crrect. Any member f yur grup can be asked fr the explanatin. PART A: Transistr Switches 1. PSpice DC sweep f transistr circuit with cutff and saturatin indicated 2. PSpice DC sweep f transistr circuit with vltage divided 3. PSpice plt f nrmalized currents with active regin marked Questins 1-5 PART B: Cmparatrs and Schmitt Triggers 1. PSpice transient fr the cmparatr with 0V reference vltage 2. PSpice transient fr the cmparatr with 1V reference vltage 3. PSpice transient fr Schmitt trigger with 0V reference vltage 4. PSpice transient fr Schmitt trigger with 1V reference vltage Questins 1-6 PART C: Digital Switching 1. PSpice transient f Schmitt trigger and inverter in the presence f nise 2. PSpice transient f Schmitt trigger and inverter with transitin pints Questins 1-8 PART D: Relay Circuit (with an LED filling in fr the relay) 1. Table f data pints A,B,C and D 2. Input and utput vltages fr bth the Schmitt Trigger and Inverter Questin 1-4 Member Respnsibilities Summary/Overview K.A. Cnnr, S. Bnner, P. Schch - 16 -