WLP Probing Technology Opportunity and Challenge
Founded Capital PTI Group Overview : May/15/97 : USD 246 Millions PTI HQ Total Assets : USD 2.2B Employees Major Services : 11,100 (Greatek included) : Chip Probing, Bumping, Packaging, Final Test & Module Assembly IPO : 4/3/03 in Taiwan
Group Overview- Global Network China Suzhou Plant Hsinpu Plant HSIP Plant Chung-Li Plant Xi an Plant Payton in China 4 hrs by air 15 min drive HuKou Industrial Park Headquarter B 30 min drive Greatek Electronic Southeast Asia Singapore Plant Customer Success!!
Put more resource for next technology! 2012 SWTW ASE_SV 50um Pitch Array 2014 SWTW FFI 80um Pitch CPB 4
Probing at 2G Wide I/O Bump Pad Source : 2011 IEEE _ Samsung 5
WLP(Wafer Level Packages) Wafer-level-packages have emerged in many different varieties that can be categorized into different advanced packaging technology platforms Source : 2013 SEMI _ Yole 6
Map of WLP manufacturing companies 7 Companies 7 Companies 27 Companies Source : 2015 Yole 7
WLP Key Connection Technology Wafer Level Package Bump RDL TSV CPB 8
From Kid View! Wafer Level Package Bump like RDL like TSV like CPB like 9
Electrical Tests for WLP Connectivity Fault Model Source : 2010 IEEE 3D IC Workshop _TSMC 10
Fault Model for different test items WLP Probing Supplier A Supplier B Supplier A or C Supplier B or D Source : 2010 IEEE 3D IC Workshop _TSMC 11
WoW! Source : Taipei 101 12
Challenge? Opportunity? Cost? New Model? Technology? Cooperation? Source : NTHU 13
Case1: Tools Short Delivery Cycle Time? Design Type Out Wafer Process Wafer Test 4~10 Weeks MP card Gap Design Type Out WLP Process WLP Test Early Plan?? Eng Card?? 2~3 Weeks MP card?? 14
[Ex] WLCSP 256DUT Probe card Bump Type: WLCSP a. Diameter: 300um b. Height: 170um ± 10%. c. Pitch: 500um d. TD : 10 f. Total Pin Count 2560 Pins Delivery Time 8 Weeks 15
Case2: Process Change for more Chip Probing? Exist Process Wafer Process Wafer Test Assembly Finial Test Process X Wafer Process Wafer Test(KGD) WLP WLP Test Assembly Process Y Wafer Process WLP WLP Test (KGD) Assembly 16
More WLP Test or More Finial Test? WLP Test Finial Test Fine Pitch Contact Force Silicon Base um mm Pitch Limit Clean/10K Cleanness Package Base Pictures Source : Mitsubishi 17
Wafer Test or Finial Test Vender @ WLP Testing? Wafer Test Vender Finial Test Vender Cycle Time Challenge Cost Challenge New Process Challenge Gap Cooperation Model Challenge Wafer Level Requirement and Quality 18
WLCSP / WLCPB Probe Card Speed <500 Mhz <3G Mhz >3G Mhz Source : SWTW
Bump Process & WLP Probing Roadmap Bump Process Mature Production Gap 400um 200um 100um 80um 60um 40um 20um Mature Production WLP Test Production / Pilot Run R&D 20
Ideal Probe Force v.s Over Drive Probe Force Depend on Material @ WLP Probing Electrical All Pass Point Low Force Keep No Damage Over Drive Slope Depend on Material 21
Case 3: Probe mark analysis Technology AOI Probe Mark Analysis Challenge Different Layer Bump RDL CPB 22
What Expect data from those Probe mark? Data Mining: (1) Prober Performance (2)Probe card Performance AOI Probe mark Analysis User Expect Data [Keep Under Development] 23
Case 4: Business or Process Change? Chip Design Wafer Process WL Test A.P Finial Test Customer Foundry OSAT Chip Design Wafer Process WLP Design WLP Process WLP Test Tech Cost Yield 24
Same Issue but different site? Foundry A OSAT A Customer Foundry B OSAT B Foundry C OSAT C ATE Vender Prober Vender A Prober Vender B Probe card Vender A Probe card Vender B Cooperation AOI Vender Gap Clean Vender Cont act Align ment Recipe 25
Conclusion Cooperation from Customer to Supplier (Design House /Foundry/OSAT/Vender). New opportunity for Wafer/Finial Test I/F vender. The Evolution Business Model will start change something. 26