February 23, 2007 Powerchip Semiconductor Corporation A3R12E3GEF G6E 635BLC4M Structural Analysis For comments, questions, or more information about this report, or for any additional technical needs concerning semiconductor technology, please call Sales at Chipworks. 3685 Richmond Road, Suite 500, Ottawa, ON K2H 5B7, Canada Tel: 613.829.0414 Fax: 613.829.0515 www.chipworks.com
Structural Analysis Table of Contents 1 Overview 1.1 List of Figures 1.2 List of Tables 1.3 Company Profile 1.4 Introduction 1.5 Device Summary 1.6 Process Summary 2 Device Overview 2.1 Package and Die 2.2 Die Features 3 Package Analysis 3.1 Package Cross Section 3.2 Stitch Bonds and Ball Bonds 3.3 BGA Solder Bumps 4 Process Analysis 4.1 General 4.2 Dielectrics 4.3 Intermetal Dielectrics 4.4 Metallization 4.5 Vias and Contacts 4.6 MOS Transistors 4.7 DRAM Cell Array Stacked Capacitors 4.8 Wells and Substrate 4.9 Fuses 5 Memory Blocks and Cells 5.1 Memory Blocks 5.2 Memory Cells 6 Material Analysis 6.1 Package 6.2 Metals and Contacts 6.3 Dielectrics 6.4 Transistor Gate Stack 6.5 Capacitor Layers
Structural Analysis 7 Critical Dimensions 7.1 Horizontal Dimensions 7.2 Vertical Dimensions 8 Statement of Measurement Uncertainty Report Evaluation
Overview 1-1 1 Overview 1.1 List of Figures 2 Device Overview 2.1.1 Package Top 2.1.2 Package Bottom 2.1.3 Die Photograph 2.1.4 Die Markings 2.2.1 Left Bottom Die Corner 2.2.2 Left Top Die Corner 2.2.3 Right Top Die Corner 2.2.4 Right Bottom Die Corner 2.2.5 Typical Bond Pad and Minimum Bond pad Spacing 2.2.6 Fuse Bank 2.2.7 Fuses 3 Package Analysis 3.1.1 Package Plan View X-Ray Radiograph 3.1.2 Package Cross Section 3.1.3 SEM Image of Package Cross Section 3.1.4 SEM Image of Die Edge Cross Section 3.2.1 Optical Image of Stitch Bond Cross Section 3.2.2 SEM Image of Stitch Bond Cross Section 3.2.3 Bond Ball Cross Section 3.2.4 Bond Pad Window Edge 3.3.1 BGA Solder Bump Cross Section 4 Process Analysis 4.1.1 General Structure in DRAM Array Parallel to Bitline 4.1.2 General Structure in DRAM Array Parallel to Wordline 4.1.3 General Structure in Peripheral Region 4.1.4 Die Edge Seal 4.2.1 Passivation Metal 3 4.2.2 Passivation Metal 3 Sidewall 4.3.1 Intermetal Dielectric IMD 2 4.3.2 Intermetal Dielectric IMD 1 Top Layers 4.3.3 Intermetal Dielectric IMD 1 Bottom Layers 4.3.4 Pre-Metal Dielectric 4.4.1 General Metallization Structure 4.4.2 TEM Image of Metal 3 4.4.3 TEM Image of Metal 2 4.4.4 TEM Image of Metal 1 Bitline and Bitline Contact 4.4.5 TEM Image of Metal 1 Layer 4.4.6 Metal 1 Bitlines 4.4.7 Metal 1 Lines in Periphery Region 4.5.1 Minimum Pitch Via 2
Overview 1-2 4.5.2 Deep and Shallow Via 1s 4.5.3 Multiple Via 1s 4.5.4 Contacts to Diffusion and to Polycide 4.5.5 TEM Image of Contact to Diffusion 4.5.6 Contacts to Access Transistor in DRAM Cell Array 4.6.1 Cell Array Region Access Transistor 4.6.2 Cell Array Region Access Transistor Gate Oxide 4.6.3 Minimum Size Periphery Region Transistor 4.6.4 Periphery Transistor Sidewall Spacer 4.6.5 Periphery Transistor Gate Oxide 4.6.6 Periphery Transistor Gate Oxide Thinning 4.7.1 Stacked Capacitors Bottom Portion 4.7.2 Stacked Capacitors Top Portion 4.7.3 Stacked Capacitor Internal Layers 4.7.4 Planar Cross Section of the Capacitors 4.8.1 Scanning Capacitance Image of Cell Array 4.8.2 SRP Profiling Locations 4.8.3 Impurity Profile in Cell Array Region 4.8.4 Impurity Profile in Periphery Region P-Well 4.8.5 Impurity Profile in Periphery Region N-Well 4.9.1 Fuse and Its Connections 5 Memory Blocks and Cells 5.1.1 Capacitor Common Plates 5.1.2 Corner of a Capacitor Common Plate 5.2.1 Cell Array Plan View at Extension Plug Level 5.2.2 Cell Array Plan View at Bitline Level 5.2.3 Cell Array Plan View at Upper Poly Plug Level 5.2.4 Cell Array Plan View at Wordline Level 5.2.5 Cell Array Plan View at Silicon Level 5.2.6 Cell Array Cross Section 6 Material Analysis 6.1.1 BGA Solder Bump EDS Spectrum 6.1.2 BGA Solder Bump and Stitch Bond Pad Bottom EDS Spectrum 6.1.3 BGA Solder Ball Pad Top and Stitch Bond Pad Top EDS Spectrum 6.1.4 Bond Wire and Stitch Bond Pad Plating EDS Spectrum 6.2.1 Metal 3 Barrier EDS Spectrum 6.2.2 Metal 2 Barrier EDS Spectrum 6.2.3 Metal 1 EDS Spectrum 6.2.4 Metal 1 Contact Liner EDS Spectrum 6.2.5 Metal 1 Contact Silicide 6.3.1 Top Passivation Layer EDS Spectrum 6.3.2 Bottom Passivation Layer EDS Spectrum 6.3.3 IMD 2-2 Layer EDS Spectrum 6.3.4 IMD 2-1 Layer EDS Spectrum
Overview 1-3 6.3.5 IMD1 Between Metal 2 and Capacitor Common Plate EDS Spectrum 6.3.6 IMD 1-5 Layer EDS Spectrum 6.3.7 IMD 1-4 Layer EDS Spectrum 6.3.8 IMD 1-3 EDS Spectrum 6.3.9 PMD 1-4 Layer EDS Spectrum 6.3.10 PMD 1-2 Layer EDS Spectrum 6.4.1 Periphery NMOS Gate Cap Top EDS Spectrum 6.4.2 Transistor Gate Cap Bottom EDS Spectrum 6.4.3 Transistor Gate Metal EDS Spectrum 6.4.4 Transistor Gate Metal Pad EDS Spectrum 6.4.5 Transistor Gate Silicide EDS Spectrum 6.4.6 Transistor Gate Bottom Layer EDS Spectrum 6.5.1 Capacitor Common Plate EDS Spectrum 6.5.2 Capacitor Inside Electrode EDS Spectrum 6.5.3 Capacitor Dielectric Layer EDS Spectrum 6.5.4 Capacitor Outside Electrode EDS Spectrum
Overview 1-4 1.2 List of Tables 1 Overview 1.4.1 Package and Die Markings 1.5.1 Process Summary 1.6.1 Major Findings 4 Process Analysis 4.3.1 Dielectric Composition and Thickness 4.4.1 Metallization Vertical Dimensions 4.4.2 Metallization Horizontal Dimensions 4.5.1 Via and Contact Dimensions 4.8.1 Wells and Epi Layer 7 Critical Dimensions 7.1.1 Metals Horizontal Dimensions 7.1.2 Vias and Contacts Horizontal Dimensions 7.1.3 Transistors, Poly, and Isolation 7.2.1 Vertical Dimensions
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