RFIC2014, Tampa Bay June 1-3, 2014 Insights Into Circuits for Frequency Synthesis at mm-waves Andrea Mazzanti Università di Pavia, Italy
High data rate wireless networks MAN / LAN PAN ~7GHz of unlicensed bandwidth available around ~60GHz Intense standardization activity WiGig, 802.11ad, WirelessHD, 802.15.3c, ECMA-387 W141: Frequency Synthesis for 60 GHz and Beyond RFIC2014, Tampa Bay, 1-3 June, 2014 2
Outline Frequency synthesizer for a sliding-if mmwave Receiver in 65nm CMOS Inductor-less CMOS frequency divider operating up to 70GHz A low-noise wide tuning-range mmwave VCO in 32nm CMOS For more refer to: F. Vecchi et al., A Wideband Receiver for Multi-Gb/s Communications in 65nm CMOS, JSSC, march 2011 W141: Frequency Synthesis for 60 GHz and Beyond RFIC2014, Tampa Bay, 1-3 June, 2014 3
PHY for Gb/s wireless communications High Rate 60GHz PHY Proposal 2.16 GHz 1 2 3 4 57 58.32 60.48 62.64 64.8 66 f GHz Large RF bandwidth (~9GHz minimum) RX Minimum Sensitivity: from -60dBm (1Gb/s) to -50dBm (4Gb/s) RX Maximum Noise Figure < 10dB Large LO tuning range required Very stringent phase noise at maximum data rate Source: ECMA International, High Rate 60 GHz Phy, MAC and HDMI PAL, Standard ECMA-387, 1st Edition, Dec. 2008 [Online] W141: Frequency Synthesis for 60 GHz and Beyond RFIC2014, Tampa Bay, 1-3 June, 2014 4
Phase noise requirements 2Gbps 16-QAM Phase noise rotates signal constellation and impairs BER Phase noise <-113dBc/Hz @10MHz is required in most stringent cases, assuming 1MHz PLL bandwidth Source: IEEE 802.15-06-0477-01-003c [Online] W141: Frequency Synthesis for 60 GHz and Beyond RFIC2014, Tampa Bay, 1-3 June, 2014 5
Sliding-IF RX architecture RF Mixer I IF Mixers Buffer LNA / 2 0 Fref VCO 40GHz PLL LO Buffer / 2 90 Q Buffer First down-conversion to 1/3 of the received frequency Only one PLL at 38.9 43.2 GHz Integrated PN: < -20dBc Dividers by 2 to generate I/Q IF signals W141: Frequency Synthesis for 60 GHz and Beyond RFIC2014, Tampa Bay, 1-3 June, 2014 6
PLL architecture 36 MHz 27 30 PFD CMOS 5 CP CML to CMOS CML 4 VCO ILFD 2 To RF Mixer To IF Mixers CP contribution to In-band phase noise: L CP SIcp = ICP 2 2π N 1 2 Design strategy Increase CP current (2mA) But reduce VCO gain (500MHz/V) And optimize LPF to ensure stability Increasing I CP reduces L CP but stability becomes an issue W141: Frequency Synthesis for 60 GHz and Beyond RFIC2014, Tampa Bay, 1-3 June, 2014 7
40GHz VCO and Dividers 16% Tuning Range ~ 30% Locking Range W141: Frequency Synthesis for 60 GHz and Beyond RFIC2014, Tampa Bay, 1-3 June, 2014 8
Phase Noise Measurements RF MIXER IF MIXER BUFFER PN + 3.5 db LNA 60.1 f GHz 40.1 PN f GHz 40 GHz VCO 40GHz PLL /2 20 GHz 0.1 0.2 f GHz VCO Phase Noise: -118.5dBc/Hz @10MHz from 40 GHz carrier Integrated Phase Noise: -22.5dBc [10kHz-10MHz] from 60GHz carrier W141: Frequency Synthesis for 60 GHz and Beyond RFIC2014, Tampa Bay, 1-3 June, 2014 9
mmwave receiver 40 10 LNA RF & IF MIX. DIV. I VCO DIV. Q SYNTHESIZER Gain (db) 35 30 25 20 15 10 5 57-66 GHz 9 8 7 6 5 4 3 Noise Figure (db) 0 2 55 60 65 70 Frequency (GHz) Technology: STM 65nm CMOS Area: 2.4mm 2 Power Consumption> 44mW PLL, 40mW RX front-end External LO Integrated PLL W141: Frequency Synthesis for 60 GHz and Beyond RFIC2014, Tampa Bay, 1-3 June, 2014 10
Outline Frequency synthesizer for a sliding-if mmwave Receiver in 65nm CMOS Inductor-less CMOS frequency divider operating up to 70GHz A low-noise wide tuning-range mmwave VCO in 32nm CMOS For more, refer to: A. Ghilioni et al., mm-wave frequency dividers analysis and design based on dynamic latches with load modulation JSSC August 2013 W141: Frequency Synthesis for 60 GHz and Beyond RFIC2014, Tampa Bay, 1-3 June, 2014 11
Injection locked LC dividers Many examples demonstrated on bulk CMOS Limited tunability due to the LC resonance Trade off between bandwidth (tank Q) and power consumption Large area due to the inductor W141: Frequency Synthesis for 60 GHz and Beyond RFIC2014, Tampa Bay, 1-3 June, 2014 12
CML static dividers for mmw PLLs Very wide operating range Small area (no inductors) Large power consumption to reach mm-waves W141: Frequency Synthesis for 60 GHz and Beyond RFIC2014, Tampa Bay, 1-3 June, 2014 13
Brief review on static CML latch M 1-2 sense the input when E is High M 3-4 regenerative pair stores the sampled data during hold W141: Frequency Synthesis for 60 GHz and Beyond RFIC2014, Tampa Bay, 1-3 June, 2014 14
Diff. pair as dynamic CML latch Regenerative pair is removed The sampled date is temporarily stored on the load (parasitic) capacitors A. Ghilioni et al., ISSCC 2011 W141: Frequency Synthesis for 60 GHz and Beyond RFIC2014, Tampa Bay, 1-3 June, 2014 15
Diff. pair as a dynamic CML latch Design trade-off for selection of the load resistance Read phase: Hold phase: Small load resistance desirable to speed-up sensing phase Large load resistance desirable to extend hold phase A. Ghilioni et al., ISSCC 2011 W141: Frequency Synthesis for 60 GHz and Beyond RFIC2014, Tampa Bay, 1-3 June, 2014 16
Dynamic latch with load modulation READ no load modulation Small R and high current for faster read phase HOLD no load modulation Large R for longer hold phase W141: Frequency Synthesis for 60 GHz and Beyond RFIC2014, Tampa Bay, 1-3 June, 2014 17
Synchronous divider by four ~2x wider bandwidth with load modulation no load modulation load modulation W141: Frequency Synthesis for 60 GHz and Beyond RFIC2014, Tampa Bay, 1-3 June, 2014 18
Simulated Waveforms Output waveforms of a latch at min and max operating frequency of the version without load modulation: @ fmin no load modulation with load modulation @ fmax W141: Frequency Synthesis for 60 GHz and Beyond RFIC2014, Tampa Bay, 1-3 June, 2014 19
Test chip photomicrograph Technology: 32nm bulk CMOS Core area: 18 x 55 µm 2 Supply voltage: 1V W141: Frequency Synthesis for 60 GHz and Beyond RFIC2014, Tampa Bay, 1-3 June, 2014 20
Meas vs. sim: sensitivity curves W141: Frequency Synthesis for 60 GHz and Beyond RFIC2014, Tampa Bay, 1-3 June, 2014 21
Measured phase noise W141: Frequency Synthesis for 60 GHz and Beyond RFIC2014, Tampa Bay, 1-3 June, 2014 22
Comparison with state of the art [6] [7] [8] [9] [10] [11] [12] W141: Frequency Synthesis for 60 GHz and Beyond RFIC2014, Tampa Bay, 1-3 June, 2014 23
Outline Frequency synthesizer for a sliding-if mmwave Receiver in 65nm CMOS Inductor-less CMOS frequency divider operating up to 70GHz A low-noise wide tuning-range mmwave VCO in 32nm CMOS For more, refer to: E. Mammei et al., A 33.6-to-46.2GHz 32nm CMOS VCO with 177.5dBc/Hz minimum noise FOM using inductor splitting for tuning extension ISSCC 2013 W141: Frequency Synthesis for 60 GHz and Beyond RFIC2014, Tampa Bay, 1-3 June, 2014 24
Issues of mmwave - VCOs Tuning Range [%] 35 30 25 20 15 10 5 0 20 30 40 50 60 Center frequency [GHz] Tuning Range reduces dramatically at mmwave High Tuning Range leads to poor phase noise FoM Achieving state of the art FoM and wide tuning range is challenging W141: Frequency Synthesis for 60 GHz and Beyond RFIC2014, Tampa Bay, 1-3 June, 2014 25
Improvement from tech. scaling? 0.13 um 6 layers IEDM 2010, S. Francisco Continuous scaling driven by complex Systems on Chip ~ 20-30% f T improvement only per generation aggressive scaling of BEOL: large impact of routing parasitic (layout) passive components penalty W141: Frequency Synthesis for 60 GHz and Beyond RFIC2014, Tampa Bay, 1-3 June, 2014 26
CMOS 65nm vs 32nm: BEOL Top Level Metal High Level Metals Low Level Metals High Level Vias Low Level Vias 32nm H.L.M closer to substrate (~85%) but same thickness 32nm L.L.M. closer to substrate and thinner (~50% ) 2x resistivity of 32nm VIAs CMOS65nm CMOS32nm W141: Frequency Synthesis for 60 GHz and Beyond RFIC2014, Tampa Bay, 1-3 June, 2014 27
Performance of switches Switch On Switch Off rsw csw r SW 1 g M c SW C GS 650 600 550 FOM = c r SW SW SW 1 f T FOM[fs] 500 450 400 Considering post-layout, mild advantage beyond 45nm 350 300 70 60 50 40 30 20 Gate Length [nm] W141: Frequency Synthesis for 60 GHz and Beyond RFIC2014, Tampa Bay, 1-3 June, 2014 28
Quality Factor 30 20 10 CMOS65nm CMOS32nm L=100pH 0 0 20 40 60 80 40 Frequency [GHz] MOM Q in 32nm ~70% than 65nm due to half thickness of LLM and 2x via resistance 65nm vs 32nm: passives Quality Factor 30 20 10 0 CMOS65nm Slightly lower dielectric constant in 32nm compensates lower metal distance to substrate CMOS32nm C=250fF 20 30 40 50 60 Frequency [GHz] W141: Frequency Synthesis for 60 GHz and Beyond RFIC2014, Tampa Bay, 1-3 June, 2014 29
Q of switched MOM Quality Factor 10 9 8 7 6 CMOS32nm CMOS65nm 5 1.5 1.6 1.7 1.8 1.9 2.0 Cmax/Cmin 32nm switched MOM slightly worse than 65nm W141: Frequency Synthesis for 60 GHz and Beyond RFIC2014, Tampa Bay, 1-3 June, 2014 30
Review of switched capacitor tuning -r CFIX csw CT LT C FIX : parasitic cap of buffer and core devices C FIX equal or greater than C T at mmwave SW ON: f MIN = 2π 1 ( + ) L C C T FIX T SW OFF: f MAX determined by C FIX f MAX 1 csw << CT, CFIX 1 = Cc 2π LC T SW T 2π LT CFIX + CT + csw FIX W141: Frequency Synthesis for 60 GHz and Beyond RFIC2014, Tampa Bay, 1-3 June, 2014 31
Proposed switched capacitor tuning LT c SW in series with C T +C FIX -r CFIX CT csw Much higher frequency jump SW ON: f MIN as in switched cap. oscillator SW OFF: C FIX no more limiting f MAX f MAX 1 csw << CT, CFIX 1 = ( C + ) 2π T CFIX c Lc SW T 2π LT C + C + c T FIX SW SW W141: Frequency Synthesis for 60 GHz and Beyond RFIC2014, Tampa Bay, 1-3 June, 2014 32
Comparison with same frequency jump Assuming: C FIX =C T =100fF, L T =100pH, FOM SW =550fs f MIN =35.6GHz, f MAX /f MIN =1.2 W sw =41µm, c SW =50fF W sw =330µm,c SW =400fF Switch off -r CFIX CT csw LT -r CFIX CT csw LT r SW =11Ω, Q=8 r SW =1.37Ω, Q=16 Switch on -r CFIX CT LT rsw -r CFIX CT LT rsw W141: Frequency Synthesis for 60 GHz and Beyond RFIC2014, Tampa Bay, 1-3 June, 2014 33
Q vs f max /f min with finite components Q Proposed tank Traditional switched capacitor Advantage increase for higher frequency step and/or larger C fix W141: Frequency Synthesis for 60 GHz and Beyond RFIC2014, Tampa Bay, 1-3 June, 2014 34
VCO Design Inductor splitting with M SW for the largest tuning step Variable tank capacitance (C T ) with switched digital MOMs and varactor L T =100pH, C T =140fF, C FIX 120fF Tank Q ranges from 4 to 5.5 Transformer feedback avoids latching when M SW is off R b instead of current mirrors lowers 1/f noise W141: Frequency Synthesis for 60 GHz and Beyond RFIC2014, Tampa Bay, 1-3 June, 2014 35
Test Chip CMOS 32nm LP from STMicroelectronics Core Area 70um x 120um 40GHz center frequency Phase Noise measured after divider by 4 in X-Band (8-12GHz) 9.8mW from 1V supply W141: Frequency Synthesis for 60 GHz and Beyond RFIC2014, Tampa Bay, 1-3 June, 2014 36
Phase Noise & FoM 10 MHz offset W141: Frequency Synthesis for 60 GHz and Beyond RFIC2014, Tampa Bay, 1-3 June, 2014 37
Summary and Comparison REF FREQ [GHz] TR [%] POWER [mw] PN @10MHz [dbc/hz] FOM [dbc/hz] TECH CICC12 57.5/90.1 44.2 8.4/10.8-104.6/-112.2 172/180 65nm RFIC11 11.5/22 59 20/29-107/-127* 158.6/177.4 130nm RFIC10 34.3/39.9 15 14.4-118/-121* 178.4/180.1 65nm JSSCC11 43.2/51.8 22.9 16-117/-119* 179/180 65nm ISSCC11 21.7/27.8 24.8 12.2-121 177.5 45nm This Work 33.6/46.2 31.6 9.8-115.2/-118 177.5/180 32nm W141: Frequency Synthesis for 60 GHz and Beyond RFIC2014, Tampa Bay, 1-3 June, 2014 38
Conclusions A 65nm PLL proves suitable to satisfy the stringent requirements of a wideband mmw receiver, exploiting the advantages of a sliding IF RX architecture. Key PLL building blocks have been investigated to improve synthesizer performances in ultra-scaled CMOS nodes: a compact divider by-4 based on dynamic latches with > 60% fractional bandwidth, < 5mW power, 55x18µm 2 a 40GHz VCO with 31% T.R, 10mW power and a remarkable phase noise FOM > 177.5dBc/Hz. W141: Frequency Synthesis for 60 GHz and Beyond RFIC2014, Tampa Bay, 1-3 June, 2014 39
W141: Frequency Synthesis for 60 GHz and Beyond RFIC2014, Tampa Bay, 1-3 June, 2014 40
References [1] F.Vecchi et al.: A Wideband Receiver for Multi-Gbit/s Communications in 65 nm CMOS IEEE Journal of Solid State Circuits, Vol.46 no. 3, pp.551-561, March 2011 [2] A.Ghilioni, et al.: A 6.5mW Inductorless CMOS Frequency Divider-by-4 Operating up to 70GHz IEEE International Solid State Circuit Conference (ISSCC-2011), Digest of Technical Papers, pp. 282 284, San Francisco (California, USA), February 2011 [3] A.Ghilioni et al.: A 4.8mW inductorless CMOS Frequency Divider-by-4 with more than 60% Fractional Bandwidth up to 70GHz in Proceedings of the IEEE Custom Integrated Circuits Conference (CICC), San Jose (California, USA), September 2012 [4] A.Ghilioni et al.: Analysis and Design of mm-wave Frequency Dividers Based on Dynamic Latches With Load Modulation IEEE Journal of Solid State Circuits, Vol.48 no.8, pp.1842-1850, August 2013 [5] E.Mammei et al.: A 33.6-to-46.2GHz 32nm CMOS VCO with 177.5dBc/Hz Minimum Noise FOM Using Inductor Splitting for Tuning Extension IEEE International Solid State Circuit Conference (ISSCC-2013), Digest of Technical Papers, pp. 350 351, San Francisco (California, USA), Feb. 2013 [6] H.-H. Hsieh et al.: A V-band divide-by three differential direct injection-locked frequency divider in 65-nm CMOS, in Proc. 2010 IEEE Custom Integr. Circuits Conf. (CICC), Sep. 19 22, 2010, pp. 1 4. [7] X. P. Yu et al.: A 3 mw 54.6 GHz divide-by-3 injection locked frequency divider with resistive harmonic enhancement, IEEE Microw. Wireless Compon. Lett., vol. 19, no. 9, pp. 575 577, Sep. 2009. [8] P. Mayr et al.: A 90 GHz 65 nm CMOS injection-locked frequency divider, in Proc. 2007 IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 11 15, 2007, pp. 198 596. [9] K. Yamamoto and M. Fujishima, 70 GHz CMOS harmonic injection-locked divider, in Proc. 2006 IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 6 9, 2006, pp. 2472 2481. W141: Frequency Synthesis for 60 GHz and Beyond RFIC2014, Tampa Bay, 1-3 June, 2014 41
References [10] C.-C. Chen et al.: Design and analysis of CMOS frequency dividers with wide input locking ranges, IEEE Trans. Microw. Theory Tech., vol. 57, no. 12, pp. 3060 3069, Dec. 2009. [11] C.-A. Yu et al.: A V-band divide-by-four frequency divider with wide locking range and quadrature outputs, IEEE Microw. Wireless Compon. Lett., vol. 22, no. 2, pp. 82 84, Feb. 2012 [12] L. Wu and H. C. Luong, A 0.6 V 2.2 mw 58-to-73 GHz divide-by-4 injection-locked frequency divider, in Proc. 2012 IEEE Custom Integr. Circuits Conf. (CICC), Sep. 9 12, 2012. [13] J.Yin, H.C.Luong, A 57.5-90.1GHz Magnetically-Tuned Multi-Mode CMOS VCO, IEEE Custom Integrated Circuits Conf., Sept. 2012. [14] S.Saberi, J.Paramesh, A 11.5-22GHz Dual-Resonance Transformer-coupled Quadrature VCO, IEEE Radio Frequency Integrated Circuits Conf., pp. 1 4, June 5 6, 2011. [15] M.Nariman, R.Rofougaran, F.D.Flaviis, A Switched-Capacitor mm-wave VCO in 65 nm Digital CMOS, in Proc. RFIC Conf. 2010, May. 23 25,2010, pp. 157 160. [16] D.Murphy et al., A Low Phase Noise, Wideband and Compact CMOS PLL for Use in a Heterodyne 802.15.3c Transceiver, IEEE J. Solid-State Circuits, vol. 46, no. 7, pp. 1606 1617, July 2011. [17] J.Osorio et al., A 21.7-to-27.8GHz 2.6-degrees-rms 40mW Frequency Synthesizer in 45nm CMOS for mm-wave Communication Applications, ISSCC Dig. Tech. Papers, pp. 278 280, Feb. 2011. W141: Frequency Synthesis for 60 GHz and Beyond RFIC2014, Tampa Bay, 1-3 June, 2014 42