EE 2110A Electronic Circuits Week 7: Common-Collector Amplifier, MOS Field Effect Transistor ecture 07-1
Topics to coer Common-Collector Amplifier MOS Field Effect Transistor Physical Operation and I-V Characteristics of n-channel deices Non-ideal effects P-channel deices and other types Reading Assignment: Chap 14.1 14.5 of Jaeger and Blalock, or Chap 5.7 of Sedra & Smith And Chap 4.1 4.4 of Jaeger and Blalock or Chap 5.1-5.2 of Sedra & Smith ecture 07-2
Common-Collector Amplifier Input AC ground Output Source oad AC/Small signal equialent Also called Emitter follower R R B = = R R 4 1 R R 7 2 ecture 07-3
Terminal Voltage Gain A CC t A CC t ( β + 1) R = o = r R b π + ( β + 1) g m R for 1+ g m R β >>1 In most C-C amplifiers, A CC 1 t g m R >>1 Output oltage at emitter follows input oltage, hence the circuit is named Emitter Followers. ecture 07-4
ecture 07-5 Input Resistance and Oerall Voltage Gain Input resistance looking into the base terminal is gien by R r i b R CC in +( +1) = = β π + = = = = R CC in B R I R R CC in B R A CC t i b t A i b b o i o A CC Oerall oltage gain is
Example 1 Problem: Find oerall oltage gain. Gien data: β=100, Q-point alues: I C =245uA, V CE =3.64V, g m =9.8mΩ 1, r π =10.2kΩ. Assumptions: Small-signal operating conditions. Analysis: AC ground R B = R R = 104kΩ 1 2 R = R R = 115. kω 4 7 R = r π + (β + 1)R = 102. kω+ 101(10. 2kΩ) = 1.17MΩ in g R A m t = = 0991. R CC R B in A 0. 956 1+ g m R = A t R R I B R CC = + in ecture 07-6
ecture 07-7 Input Signal Range For small-signal operation, magnitude of be < 5 mv. If, b can be increased beyond 5 mv limit. Emitter followers can be used with relatiely large input signals! π r R R m g b )R (β π r π r b ir π be + + = + + = = 1 1 )V g m R (. β R R m g. b + + + 1 0005 0005 1 >>1 g m R
Output Resistance i = = x x x i βi β R + r R + r th π th π R + r π r R R CC th = π + th out β + 1 β + 1 β + 1 R CC out = α g m R 1 R + th + th β + 1 g m β + 1 R CC out 1 g m + R connected to base β + 1 R = R th I R B Small output resistance! ecture 07-8
Problem: Find output resistance. Example 2 Gien data: β=100, Q-point alues: I C =245uA, V CE =3.64V, g m =9.8mS, r π =10.2kΩ, r ο =219kΩ. Assumptions: Small-signal operating conditions. Analysis: R CC out α R = + th 0.990 1.96kΩ = + = 120Ω g m β + 1 9.80mS 101 ecture 07-9
Current Gain i Terminal current gain A CC = 1 = β + 1 it i ecture 07-10
Summary of Emitter Follower Voltage gain: Close to unity. Input resistance: arge Output resistance: Small Input signal range: relatiely large Terminal current gain: arge (β+1) Excellent for use as a oltage buffer ecture 07-11
Voltage Buffer Without buffer: Vs Rs R Vo R o = s << Rs + R s if R << R s With buffer: o = R A S s Ri + R = s i R s A R + RO for R >> R and i S R O << R Requirement of oltage buffer: - High input resistance - ow output resistance - Unity oltage gain ecture 07-12
Summary of Single Stage BJT Amplifiers C-E (R E =0) Emitter Degenerated C-E C-C C-B Terminal Voltage Gain Inerting & large Inerting & moderate 1 Non-inerting & arge Input Resistance Moderate arge arge ow Output Resistance Moderate arge ow arge Input Voltage Range Small Moderate arge Moderate Terminal Current Gain Inerting & arge Inerting & arge Noninerting & arge 1 ecture 07-13
More Complicated Amplifier??? 741 Op-amp - Built from single stage amplifiers ecture 07-14
Topics to coer Common-Collector Amplifier MOS Field Effect Transistor Physical Operation and I-V Characteristics of n-channel deices Non-ideal effects P-channel deices and other types ecture 07-15
Introduction Metal-Oxide Semiconductor Field-Effect Transistor (MOSFET) is the primary component in high-density chips such as memories and microprocessors Compared with BJT, MOSFET has Higher integration scale ower manufacturing cost Simpler circuitry for digital logic and memory Inferior analog circuit performance in general Recent trend: more and more analog circuits are implemented in MOS technology for lower cost integration with digital circuits in a same chip (mixed-signal IC) ecture 07-16
Microphotograph of a state-of-the-art CPU chip ecture 07-17
Structure of MOSFET Four terminals: Gate, Source, Drain and body Two types n-channel (NMOS) p-channel (PMOS) The minimum alue of is referred as the feature size of the fabrication technology. E.g., 45nm is used for Intel s Core 2 processors. symbol ecture 07-18
ow Gate Voltage Body is commonly tied to ground When the gate is at a low oltage (V GS ~ 0): P-type body is at low oltage Source-body and drain-body diodes are OFF (reerse bias) i G =0 (always), i DS = 0 Depletion region between n+ and p-type bulk No current can flow, transistor is said in Cutoff mode ecture 07-19
Increase Gate Voltage Vertical electric field established Under the gate-oxide: Holes (positie charges) repelled Depletion region under gate oxide formed ecture 07-20
Further Increase Gate Voltage Electrons (minorities in the p region) attracted by the electric field towards the gate, and stopped by the gate oxide A n-type inersion layer formed underneath the gate oxide when V GS reaches a certain alue, called threshold oltage (V t, or V TN for NMOS) The channel connects the S and D and now currents can flow between them ecture 07-21
inear (Triode) Mode of Operation When GS > V t and a small DS is applied Current flows from D to S (Electrons flow from S to D) i DS DS Increasing GS aboe V t increases the electron density in the channel, and in turn increases the conductiity between D & S Such deices are called enhancement-type MOSFET In this mode, transistor = a oltage controlled resistor ecture 07-22
Increase Drain Voltage: Channel Pinch-Off G D S Increase DS Decrease GD less electrons at the drain side of the channel When DS GS V t V GD V t no channel exists at the drain side. The channel pinches-off ecture 07-23
Saturation Mode of Operation G D S When channel pinches off, electrons still flows from S to D Electrons are diffused from the channel to the depletion region near D, where they are drifted by the lateral E-field to the D Similar to a reerse-biased B-C junction in a BJT Further increase of DS no effect on the channel current is saturated and the transistor is in Saturation Mode In this mode, transistor = a oltage controlled current source ecture 07-24
Qualitatie I-V Characteristic Pinch Off ecture 07-25
I-V Characteristics In the inear region, drain current depends on How much charge is in the channel How fast the charge is moing I dq dt = amount of charge in the channel time it takes the carriers to get across the channel ecture 07-26
Amount of Channel Charge MOS structure looks like a parallel plate capacitor V GC is composed of two components V t to form the channel (V GC -V t ) to accumulate negatie charges in the channel Q C V channel = ε = V ox GC = CV W t ox V t = C = ox W where C ( GS DS / 2 ) Vt 14243 4 ox = ε Aerage gate-channel oltage ox / t ox Ref: G.-Y. Wei, notes ES154, Harard Uniersity ecture 07-27
Charge is carried by electrons. Carrier Velocity Carrier elocity is proportional to the lateral E-field between source and drain = µ ne where µ n is E = / DS Time for carriers to cross the channel is the mobility t = / = = µ E n µ n 2 DS ecture 07-28
I-V Behaior: inear Mode Combine the channel charge and elocity to find the current flow Current = amount of charge in the channel / time it takes the carriers to get across the channel i D = Q = µ C = K channel n n t ox ( GS = C W ( V t ox µ n W( GS Vt DS / 2) 2 GS V DS t / 2) / 2) = µ C ( µ C n ox ) is a constant determined by the processing technology, and is denoted by K n W/ is a main design parameter in integrated circuit design. DS DS DS where W 1 2 i D = ( µ ncox ) ( GS Vt ) DS DS 2 K n DS n ox W ecture 07-29
I-V Behaior: Saturation Mode If GD V t, channel pinches off near the drain When DS V dsat = GS V t Now, drain oltage no longer increases with DS Putting DS = GS V t to the equation: 1 2 i D independent of DS. W 1 2 i D = ( µ ncox ) ( GS Vt ) DS DS 2 i W 2 for V D = ( µ ncox) ( GS Vt ) GS > V t and V DS GS -V t ecture 07-30
Summary of NMOS I-V Characteristics Region Cutoff Triode Saturation Conditions GS < V t DS GS V t V < GS Vt DS GS t I-V relation i D = 0 i D = K ' n W ( GS V ) t DS 1 2 2 DS i D = 1 2 K ' n W ( GS V t 2 ) Cutoff region Triode region GS DS < V t GS GS < V t and V t K ' = µ C n n ox Saturation region GS DS V t GS and V t ecture 07-31
Ideal Square aw Model: I D s V GS In saturation mode: i D 1 = ( µ nc 2 ox W ) ( GS V ) t 2 MOS s. BJT Current is quadratic with oltage in MOS s. exponential relationship in BJT Saturation mode of MOS corresponds to actie mode of BJT ecture 07-32
Ideal Square-aw Model: I D s V DS NMOS ecture 07-33
Topics to coer Common-Collector Amplifier MOS Field Effect Transistor Physical Operation and I-V Characteristics of n-channel deices Non-ideal effects P-channel deices and other types ecture 07-34
Non-ideal Effects Channel length modulation Body effect Temperature influence Breakdown ecture 07-35
Channel-ength Modulation where gate-to-channel oltage = V TN At DS = GS -V TN =V DSsat, Channel pinch-off As DS increases beyond DSsat, the pinch off point moes away from D towards S The effectie channel length is reduced by I D increases An effect similar to Early effect in BJT i D = ' K n W 2 GS V TN 2 ecture 07-36
Channel-ength Modulation This effect is modeled by adding a term (1+λ DS ) to the I-V equation: ' K = n W 2 i V 1+ λ D GS TN 2 DS λ = channel length modulation parameter ecture 07-37
Body Effect Channel-body can be regarded as a pn junction If channel-body junction is reerse-biased, Depletion layer beneath the gate oxide becomes wider Since the amount of negatie charges in the ( channel + depletion ) layer = amount of positie charges in the gate (Constant for a fixed gate-source oltage) Channel depth is reduced This is equialent to an increase in the threshold oltage ecture 07-38
Body Effect Non-zero SB changes threshold oltage: V TN = V + γ + 2φ 2φ TO SB F F where V TO = zero substrate bias for V TN (V) γ= body-effect parameter ( V) 2Φ F = surface potential parameter (V) (source-body oltage) It follows that the body oltage controls i D. This phenomenon is known as the body effect. ecture 07-39
Effects of Temperature V t and mobility µ are sensitie to temperature: V t decreases by 2mV for eery 1ºC rise in temperature mobility µ decreases with temperature Oerall, increase in temperature results in lower drain currents ecture 07-40
Aalanche Breakdown As V D is increased, the drain-body junction becomes reersed biased Breakdown occurs at oltages of 20 to 150V Rapid increase in the drain current Normally, no permanent damage to the deice ecture 07-41
Punch-through Breakdown Whe V D is increased to a point, the depletion region surrounding D extends to the S Punch-through breakdown (about 20 V) Occurs in deices with short channels Normally, no permanent damage to the deice ecture 07-42
Gate Oxide Breakdown When V GS exceeds about 30 V (or lower in modern IC technology) Gate oxide breaks down like in the case of a capacitor Results in permanent damage to the deice ecture 07-43
Input Protection Input Pin to gates Since the MOSFET has a ery small input capacitance and a ery high input resistance, a small amount of static charges accumulating on the gate can cause the gate oltage to exceed the breakdown leel e.g., Electrostatic Discharge (ESD) from human body Clamping diodes can be used in the I/O pins to protect the circuit from gate-oxide breakdown ecture 07-44
Topics to coer Common-Collector Amplifier MOS Field Effect Transistor Physical Operation and I-V Characteristics of n-channel deices Non-ideal effects P-channel deices and other types ecture 07-45
P-channel MOSFET (PMOS) Similar to NMOS, but doping and oltages reersed Body tied to highest oltage (Vdd) to preent forward-biasing pn junctions Source typically tied to Vdd too Gate oltage high: transistor is OFF Gate oltage low: transistor is ON when V GS < V t (threshold oltage) Inerted channel of positiely charged holes GS and DS are negatie and V t is also negatie Symbols ecture 07-46
PMOS I-V Characteristics Cutoff region GS < Vt V t, GS and DS are negatie. Triode region GS DS V < GS Saturation region GS DS V t t GS and V t and V t i D Cutoff = 0 where K p = K p ' W, i D = K ' = µ C p K p Triode/inear p ox V 1 2 2 ( GS t ) DS DS i D = 1 2 K Saturation p ( GS V t 2 ) µ p is 2 or 3-times lower than µ n ecture 07-47
Complementary MOS (CMOS) Technology PMOS transistor is fabricated in the n well Complementary MOS or CMOS integrated-circuit technologies proide both NMOS and PMOS on a same IC ecture 07-48
Depletion-mode MOSFET A depletion-type MOSFET has a built-in channel by fabrication It is ON when no gate-source oltage is applied Must apply a negatie GS to turn off deice V t is negatie for NMOS enhancement depletion ecture 07-49
MOSFET Circuit Symbols (g) and(i) are the most commonly used symbols in VSI logic design. MOS deices are symmetric. In NMOS, n + region at higher oltage is the drain. In PMOS p + region at lower oltage is the drain ecture 07-50