IJSTE - International Journal of Science Technology & Engineering Volume 2 Issue 12 June 2016 ISSN (online): 2349-784X Design and Analysis of Double Gate MOSFET Operational Amplifier in 45nm CMOS Technology Avinash Kadam PG Student Department of VLSI Design & Embedded System CPGS, Visvesvaraya Technological University, Belagavi Dr. Meghana Kulkarni Professor Department of VLSI Design & Embedded System CPGS, Visvesvaraya Technological University, Belagavi Abstract This paper describes the design and analysis of double gate operation amplifier (op-amp) using the two different biasing techniques of the double gate MOSFET. The double gate MOSFET is configured in Symmetrically Driven Double Gate (SDDG) & Independently Driven Double Gate (IDDG) configuration based on the biasing of the back gate. The op-amps are designed in 45nm technology in Cadence for analog application and analysed with active & passive load for gain and power dissipation as the key performance parameters. The two double gate configurations are compared to find the better topology. The IDDG op-amp with active load is found to be the better among the compared design with 27 db gain and 157.8 uw of power dissipation. The gain of the IDDG based op-amps can be easily tuned by varying the back gate voltage, hence a better option of double gate topology that can be used in analog circuits. Keywords: Double Gate MOSFET, IDDG, SDDG, Tunable Gain, Op-Amp and Active Load I. INTRODUCTION THE operational amplifier is one of the most versatile and widely used amplifiers in the analog circuit design. The amplifier is used in various applications and can perform various operation by just varying the feedback topology. With the need to have devices with low power consumption and the effects of reduced channel length in bulk device, the double gate (DG) MOSFET provides a novel option. The double gate MOSFET can be configured in two topology based on the biasing of the back gate, symmetrical driven (SDDG) and independently driven (IDDG). The IDDG provides an option to tune the circuit s performance [2]. While implementing the circuit, passive load or resistor takes large area. In this work, we have designed and analysed the opamp with SDDG and IDDG configuration with active and passive load in Cadence Virtuoso 45nm technology. II. DESIGN OF OP-AMP WITH DG MOSFET The op-amp is designed using the differential amplifier and common source amplifier. The differential amplifier and common source amplifier are designed with the MOSFET in the two DG configuration based on back gate biasing. The two configuration of DG is showed in fig. 1. The topology of fig. 1(a) has both the front gate and back gate tied together, hence operating at same bias, i.e. symmetrically driven, whereas the one in fig. 1(b) is having the front and back gate independent to each other, i.e. independently driven. We have used the planar geometry or equivalent approach of the DG MOSFET in this work [3]. Fig. 1: (a) SDDG configuration; (b) IDDG configuration IDDG topology can be used for tuning the performance of analog circuit. These two configuration is used for designing the differential and common source amplifier. All rights reserved by www.ijste.org 117
The basic circuit of the op-amp is shown in fig. 2. The left side is differential and right side is having the common source amplifier respectively. The back gates are having V bg as bias voltage which can be equal to front gate or different from front gate for SDDG and IDDG topology respectively. Fig. 2: DG op-amp with differential and common source amplifier III. THE SDDG OP-AMP The SDDG op-amp is designed by tying the front and back gate together at same potential. We did the analysis for the op-amp in open loop configuration and with active & passive load. The open loop has no load attached. The fig. 3(a) shows the designed differential amplifier and fig. 3(b) shows the common source amplifier in Cadence Virtuoso. Fig. 3(c) shows the SDDG op-amp in open loop configuration. The circuit is simulated for a sinusoidal input of 50 mv. Fig. 3(a): SDDG differential amplifier Fig. 3(b): SDDG common source amplifier The obtained output waveform is shown in fig. 4(a) and the gain over in fig. 4(b). The gain curve suggests that the amplifier has fairly stable gain over a large frequency of operation, nearly in 100 MHz range. The circuit of op-amp using various feedback topologies can be broadly classified into inverting and non-inverting based on the terminal where input is applied. The non-inverting amplifier has input applied at its positive terminal and inverting to its, negative terminal. The SDDG op-amp is simulated with active load (nmos) and passive load (resistor). The active load has many advantages over the passive load in terms of power dissipation and area required during the implementation on chip [4]. All rights reserved by www.ijste.org 118
Fig. 3(c): SDDG op-amp in open loop configuration Fig. 4(a). SDDG op-amp open loop output Fig. 4(b). SDDG op-amp open loop gain curve SDDG op-amp with Active Load: We simulated the SDDG op-amp using active and passive load. The fig. 5 shows the designed op-amp with active load. The nmos is used as active load. The gate of the nmos is biased with 0.3 V. The load works similar to the passive load. Simulation is done after applying 50 mv sinusoidal signals. Fig. 6(a) and fig. 6(b) shows the output waveform and the obtained gain curve. The gain curve is similar to the one obtained for open loop configuration, having large bandwidth. All rights reserved by www.ijste.org 119
Fig. 5: SDDG op-amp with active load Fig. 6(a): SDDG op-amp active load output Fig. 6(b): SDDG op-amp active load gain curve SDDG op-amp with Passive Load: The passive load op-amp has resistors in place of the nmos and circuit is similar to fig. 5. We simulated the circuit with 50 mv sinusoidal input. The gain and power consumption were the performance parameter used for comparison with other design. We found that the gain curve for the passive load, active load and open loop are similar in bandwidth. This large bandwidth can be attributed to the better current controlling capability of DG MOSFET. Obtained output waveform and gain curve is shown in fig. 7(a) & fig. 7(b) resp. All rights reserved by www.ijste.org 120
Fig. 7(a): SDDG op-amp resistive load output Fig. 7(b): SDDG op-amp resistive load gain curve IV. THE IDDG OP-AMP The IDDG op-amp is designed by independently biasing the front and back gate. Consider fig. 2. The back gates of each DG MOSFET is having independent bias V bg with nmos and pmos having potential V bgn, V bgp respectively, with V bgn = -V bgp. This independency provides the tunability. We did the analysis for the op-amp in open loop configuration and with active & passive load, similar to the SDDG based op-amp. Fig. 8 shows the IDDG op-amp in open loop configuration. The circuit is simulated for a sinusoidal input of 50 mv. Fig. 8: IDDG op-amp in open loop We designed and simulated the IDDG op-amp with active and passive load. The designed circuits are similar to the SDDG opamp with load, with only difference of independently biased back gate. IDDG op-amp with Active Load: We simulated the IDDG op-amp using active with input of 50 mv sinusoidal signal. The gate of the nmos is biased with 0.3 V. The circuit is similar to the SDDG op-amp with active load, with only addition of back gate driven independently. IDDG op-amp with Passive Load: The passive load op-amp has resistors in place of the nmos, similar to SDDG op-amp with resistive load. We simulated the circuit with 50 mv sinusoidal input. The gain curve suggests that the amplifier has fairly stable gain over a large frequency of operation, nearly in 100 MHz range, similar to the one obtained for SDDG op-amp. IDDG makes the MOSFET tunable [2]. Hence, to perform the tunability for the IDDG op-amp, we varied the back gate biasing and simulated the design. The observed values for gain and power dissipation are tabled in table 1. All rights reserved by www.ijste.org 121
Table 1 IDDG op-amp output after varying Vbgn/p Input (mvp-p) Vdd=-Vss (V) Vbgp=-Vbgn(V) Power Consumed (uw) Gain (db) 5 1.091 0.75 160.2 24 50 1.091 0.75 162.3 24 The comparison of all the designed op-amp is shown in table 2. We observed that the IDDG op-amp with active load is better performing and is tunable. Table 2 Comparison of different op-amp configurations Op-Amp Input (mvp-p) Gain (db) Power Consumed (uw) SDDG (open loop) 50 28 165.4 SDDG (NMOS load) 50 26.8 170 SDDG (Passive load) 50 26 169.6 IDDG (open loop) 50 28 153.2 IDDG (NMOS load) 50 27 157.8 IDDG (Passive load) 50 26 158.4 V. CONCLUSION The op-amp with different DG topology is designed and analysed in 45nm CMOS technology using Cadence Virtuoso. From the comparison of different op-amp configuration, we can conclude that the performance of IDDG based op-amp is better than the SDDG based op-amp. Using NMOS load, the power consumed can be bought down and also the active resistance will take less area when implemented than the passive load. Also the gain curve shows that the bandwidth of operation for all the op-amps is high. The IDDG MOSFET provides the ability to tune the circuit as per the requirement easily and the results are encouraging. REFERENCES [1] Handbook of Operational Amplifier Applications, Texas Instruments, Bruce Carter and Thomas R. Brown, 2001 [2] Ravindra Singh Kushwah & Shyam Akashe, Design and Analysis of Tunable Analog Circuit Using Double Gate MOSFET at 45nm CMOS Technology, in 3rd IEEE International Advance Computing Conference (IACC), 2013. pp. 1589-1594 [3] Ruchika, Tripti Sharma & Krishna Gopal Sharma, Double Gate MOSFET Circuit Design, in IEEE International Conference on Recent Advances and Innovations in Engineering (ICRAIE-2014), Jaipur, India, May 09-11, 2014. [4] Manish Goswami, Smriti Khanna, DC Suppressed High Gain Active CMOS Instrumentation Amplifier for Biomedical Application, in Proceedings of ICETECT, 2011, pp. 747-751 [5] James Bryant, Walt Jung & Walt Kester, OP-AMPS BASIC and APPLICATIONS, Analog Devices [6] www.wikipedia.com All rights reserved by www.ijste.org 122