Applyig MOSFETs i Aplifier esig Microelectroic Circuits, 7 th Editio Sedra/Sith Copyright 010 by Oxford Uiersity Press, Ic.
oltage Trasfer Characteristics (TC) i 1 k ( GS t ) S i R Microelectroic Circuits, 7 th Editio Sedra/Sith Copyright 010 by Oxford Uiersity Press, Ic.
Biasig the MOSFET to Obtai Liear Aplificatio ( t) ( t) GS GS + gs S 1 k Biasig the MOSFET aplifier at a poit Q located o the seget AB of the TC. Microelectroic Circuits, Sixth Editio Sedra/Sith Copyright 010 by Oxford Uiersity Press, Ic. R ( GS t )
Sall sigal oltage gai Microelectroic Circuits, Sixth Editio Sedra/Sith Copyright 010 by Oxford Uiersity Press, Ic.
Sall sigal oltage gai S 1 k R ( GS t ) A d d S GS GS GS A I O R / 1. The gai is egatie (180 O ) phase shift betwee iput ad output.. The gai is proportioal to the load resistace R, trascoductace paraeter k, ad the oerdrie oltage O. Microelectroic Circuits, 7 th Editio Sedra/Sith Copyright 010 by Oxford Uiersity Press, Ic.
Graphical costructio to deterie the oltage Trasfer Characteristic of the aplifier i S R fro : 1 R i R S Microelectroic Circuits, 7 th Editio Sedra/Sith Copyright 010 by Oxford Uiersity Press, Ic.
Locatig the Bias Poit Q Figure 5.33 Two load lies ad correspodig bias poits. Bias poit Q 1 does ot leae sufficiet roo for positie sigal swig at the drai (too close to ). Bias poit Q is too close to the boudary of the triode regio ad ight ot allow for sufficiet egatie sigal swig. Microelectroic Circuits, Sixth Editio Sedra/Sith Copyright 010 by Oxford Uiersity Press, Ic.
Sall-Sigal Operatio C Bias Poit: 1 I k( GS t ) 1 k O S I R To esure saturatio-regio operatio: S > O Microelectroic Circuits, 7 th Editio Sedra/Sith Copyright 010 by Oxford Uiersity Press, Ic.
Sall-sigal operatio of the MOSFET aplifier. MOSFET trascoductace: g i k( GS t ) gs k O i GS GS GS Microelectroic Circuits, 7 th Editio Sedra/Sith Copyright 010 by Oxford Uiersity Press, Ic.
Trascoductace g ' W ' W g k ( )( GS t ) k ( ) L L g g k ' I GS W L t I I O O 1. For a gie MOSFET, g is proportioal to the square root of C bias curret. At a gie bias curret, g is proportioal to square root of W/L Microelectroic Circuits, 7 th Editio Sedra/Sith Copyright 010 by Oxford Uiersity Press, Ic.
Separate C ad Sigal aalysis A g A ds gs i gs ds gs ir gs g oltage Gai R Microelectroic Circuits, 7 th Editio Sedra/Sith Copyright 010 by Oxford Uiersity Press, Ic.
Sall-Sigal Equialet-Circuit Models I 1 k O g i gs A ds gs g ( R // r0 ) r 0 I A Microelectroic Circuits, 7 th Editio Sedra/Sith Copyright 010 by Oxford Uiersity Press, Ic.
Exaple 5.10: (a) aplifier circuit; (b) circuit for deteriig the dc operatig poit; (c) the aplifier sall-sigal equialet circuit; (d) a siplified ersio of Microelectroic Circuits, Sixth Editio the circuit Sedra/Sith i (c). Copyright 010 by Oxford Uiersity Press, Ic.
The T Equialet- Circuit Models Figure 5.40 eelopet of the T equialet-circuit odel for the MOSFET. For siplicity, r o has bee oitted; howeer, it ay be added betwee ad S i the T odel of (d). Microelectroic Circuits, Sixth Editio Sedra/Sith Copyright 010 by Oxford Uiersity Press, Ic.
The T Equialet- Circuit Models Figure 5.41 (a) The T odel of the MOSFET augeted with the drai-to-source resistace r o. (b) A alteratie represetatio of the T odel. Microelectroic Circuits, 7 th Editio Sedra/Sith Copyright 010 by Oxford Uiersity Press, Ic.
Figure 7.18 (a) Aplifier circuit for Exaple 7.4; (b) Sall-sigal equialet circuit of the aplifier i (a). Microelectroic Circuits, 7 th Editio Sedra/Sith Copyright 010 by Oxford Uiersity Press, Ic.
Sall-Sigal Equialet-Circuit Models for the MOSFET 1. NMOS trasistors - Trascoductace: - Output resistace: π-model g r W W µ Cox O µ Cox I L L A 0 I 1 λi T-Model I O. PMOS trasistors - Sae forulas as for NMOS except usig O, A, ad replace µ with µ p Microelectroic Circuits, 7 th h Editio Sedra/Sith Copyright 010 by Oxford Uiersity Press, Ic.