WITH LEAR AND PRESET SDFS0A MARH 197 REVISED OTOBER 199 Package Optio Include Plastic Small-Outline Packages, eramic hip arriers, and Standard Plastic and eramic 00-mil DIPs description These devices contain two independent positiveedge-triggered D-type flip-flops. A low level at the preset (PRE) or clear (LR) inputs sets or resets the outputs regardless of the levels of the other inputs. When PRE and LR are inactive (high), data at the data (D) input meeting the setup time requirements is traferred to the outputs on the positive-going edge of the clock pulse. lock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input may be changed without affecting the levels at the outputs. The SNF7 is characterized for operation over the full military temperature range of to 12. The SN7F7 is characterized for operation from 0 to 70. FUNTION TABLE INPUTS OUTPUTS PRE LR LK D L H X X H L H L X X L H L L X X H H H H H H L H H L L H H H L X 0 0 The output levels are not guaranteed to meet the minimum levels for VOH. Furthermore, this configuration is notable; that is, it will not persist when PRE or LR retur to its inactive (high) level. SNF7...J PAKAGE SN7F7...D OR N PAKAGE (TOP VIEW) 1LK N N 1LR 1LK GND 1 2 7 SNF7... FK PAKAGE (TOP VIEW) 1LR N V 2LR 2 1 20 19 1 7 17 1 1 1 9 10 11 12 1 GND N 1 1 12 11 10 9 N No internal connection V 2LR 2LK N 2LK N PRODUTION DATA information is current as of publication date. Products conform to specificatio per the terms of Texas Itruments standard warranty. Production processing does not necessarily include testing of all parameters. opyright 199, Texas Itruments Incorporated POST OFFIE BOX 0 DALLAS, TEXAS 72 2 1
WITH LEAR AND PRESET SDFS0A MARH 197 REVISED OTOBER 199 logic symbol 1LK 1LR 2 1 S 1 R 2LK 2LR 10 11 12 1 9 This symbol is in accordance with ANSI/IEEE Std 91-19 and IE Publication 17-12. Pin numbers shown are for the D, J, and N packages. logic diagram, each flip-flop (positive logic) PRE LK D LR absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, V.......................................................... 0. V to 7 V Input voltage range, V I (see Note 1).................................................. 1.2 V to 7 V Input current range.............................................................. 0 ma to ma Voltage range applied to any output in the high state.................................. 0. V to V urrent into any output in the low state..................................................... 0 ma Operating free-air temperature range: SNF7.................................... to 12 SN7F7........................................ 0 to 70 Storage temperature range....................................................... to 10 Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditio beyond those indicated under recommended operating conditio is not implied. Exposure to absolute-maximum-rated conditio for extended periods may affect device reliability. NOTE 1: The input voltage ratings may be exceeded provided the input current ratings are observed. 2 2 POST OFFIE BOX 0 DALLAS, TEXAS 72
WITH LEAR AND PRESET SDFS0A MARH 197 REVISED OTOBER 199 recommended operating conditio SNF7 SN7F7 MIN NOM MAX MIN NOM MAX V Supply voltage.... V VIH High-level input voltage 2 2 V VIL Low-level input voltage 0. 0. V IIK Input clamp current 1 1 ma IOH High-level output current 1 1 ma IOL Low-level output current 20 20 ma TA Operating free-air temperature 12 0 70 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST ONDITIONS SNF7 SN7F7 MIN TYP MAX MIN TYP MAX VIK V =. V, II = 1 ma 1.2 1.2 V VOH V =. V, IOH = 1 ma 2.. 2.. V =.7 V, IOH = 1 ma 2.7 VOL V =. V, IOL = 20 ma 0. 0. 0. 0. V II V =. V, VI = 7 V 0.1 0.1 ma IIH V =. V, VI = 2.7 V 20 20 µa IIL Data, LK PRE or LR V =V. V, VI =0V 0. 0. 0. 1. 1. IOS V =. V, VO = 0 0 10 0 10 ma I V =. V, See Note 2 10. 1 10. 1 ma All typical values are at V = V, TA = 2. Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second. NOTE 2: I is measured with D, LK, and PRE grounded then with D, LK, and LR grounded. timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) V = V, TA = 2 SNF7 SN7F7 F7 MIN MAX MIN MAX MIN MAX fclock lock frequency 0 100 0 0 0 100 MHz tw tsu th Pulse duration Setup time, data before LK LK high, PRE or LR low LK low High 2 2 V ma Low Setup time, inactive-state before LK PRE or LR to LK 2 2 Hold time, data after LK Inactive-state setup time is also referred to as recovery time. High 1 2 1 Low 1 2 1 POST OFFIE BOX 0 DALLAS, TEXAS 72 2
WITH LEAR AND PRESET SDFS0A MARH 197 REVISED OTOBER 199 switching characteristics (see Note ) PARAMETER FROM (INPUT) TO (OUTPUT) V = V, L = 0 pf, RL = 00 Ω, TA = 2 V =. V to. V, L = 0 pf, RL = 00 Ω, TA = MIN to MAX F7 SNF7 SN7F7 MIN TYP MAX MIN MAX MIN MAX fmax 100 1 0 100 MHz tplh tphl tplh LK PRE or LR or or.9... 7.... 10.. 9.2 2..2.1.2 2. 7.1 tphl For conditio shown as MIN or MAX, use the appropriate value specified under recommended operating conditio. NOTE : Load circuits and waveforms are shown in Section 1. 2.7. 9. 11. 2.7 10. 2 POST OFFIE BOX 0 DALLAS, TEXAS 72
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