Functionally Equivalent to AMD s AM2982 Improved I OH Specificatio Multiple Output Enables Allow Multiuser Control of the Interface Outputs Have Undershoot-Protection Circuitry Power-Up High-Impedance State Buffered Control Inputs Reduce dc Loading Effects Package Optio Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (NT) and Ceramic (JT) 00-mil DIPs description SN4AS82A... JT PACKAGE SN74AS82A... DW OR NT PACKAGE (TOP VIEW) OE D 4D D 6D 7D 8D GND 2 4 6 7 8 9 0 2 24 2 2 20 9 8 7 6 4 V CC 2Q Q 4Q Q 6Q 7Q 8Q EN These 8-bit flip-flops feature -state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. These devices are particularly suitable for implementing multiuser registers, I/O ports, bidirectional bus drivers, and working registers. With the clock-enable (EN) input low, the eight D-type edge-triggered flip-flops enter data on the low-to-high traitio of the clock () input. Taking EN high disables the clock buffer, latching the outputs. These devices have noninverting data (D) inputs. Taking the clear () input low causes the eight Q outputs to go low independently of the clock. Multiuser buffered output-enable (OE,, and ) inputs can be used to place the eight outputs in either a normal logic state (high or low logic level) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The highimpedance state and increased drive provide the capability to drive bus lines without interface or pullup components. D 4D D 6D 7D SN4AS82A... FK PACKAGE (TOP VIEW) OE V C C 4 2 28 27 26 6 7 8 9 0 2 24 2 2 20 9 2 4 6 7 8 8D GND EN 8Q No internal connection The output enables do not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. The SN4AS82A is characterized for operation over the full military temperature range of C to 2 C. The SN74AS82A is characterized for operation from 0 C to 70 C. 2Q Q 4Q Q 6Q 7Q PRODUCTION DATA information is current as of publication date. Products conform to specificatio per the terms of Texas Itruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 99, Texas Itruments Incorporated POST OFFICE BOX 60 DALLAS, TEXAS 726
FUTION TABLE (each flip-flop) INPUTS OUTPUT OE EN D Q L L X X X L L H L H H L H L L L L H H X X Q0 H X X X X Z OE = H if any of OE,, or are high. OE = L if all of OE,, or are low. logic symbol OE EN 2 2 4 & R G C2 EN D 4D D 6D 7D 8D 4 6 7 8 9 0 2 20 9 8 7 6 2Q Q 4Q Q 6Q 7Q 8Q This symbol is in accordance with ANSI/IEEE Std 9-984 and IEC Publication 67-2. Pin numbers shown are for the DW, JT, and NT packages. 2 POST OFFICE BOX 60 DALLAS, TEXAS 726
logic diagram (positive logic) OE 2 2 EN 4 R C Pin numbers shown are for the DW, JT, and NT packages. To Seven Other Channels absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, V CC........................................................................ 7 V Input voltage, V I............................................................................ 7 V Voltage applied to a disabled -state output................................................... V Operating free-air temperature range, T A : SN4AS82A............................. C to 2 C SN74AS82A................................. 0 C to 70 C Storage temperature range....................................................... 6 C to 0 C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditio beyond those indicated under recommended operating conditio is not implied. Exposure to absolute-maximum-rated conditio for extended periods may affect device reliability. POST OFFICE BOX 60 DALLAS, TEXAS 726
recommended operating conditio SN4AS82A SN74AS82A MIN NOM MAX MIN NOM MAX VCC Supply voltage 4.. 4.. V VIH High-level input voltage 2 2 V VIL Low-level input voltage 0.7 0.8 V IOH High-level output current 24 24 ma IOL Low-level output current 2 48 ma tw* Pulse duration low 7 4 high or low 9. 8 inactive 8 8 tsu* Setup time before Data 7 6 EN high or low 0 6 th* Hold time after EN low or data 0 0 TA Operating free-air temperature 2 0 70 C * On products compliant to MIL-STD-88, Class B, this parameter is based on characterization data but is not production tested. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS SN4AS82A SN74AS82A MIN TYP MAX MIN TYP MAX VIK VCC = 4. V, II = 8 ma.2.2 V VCC = 4. V to. V, IOH = 2 ma VCC 2 VCC 2 VCC =4V 4. VOL VCC =4V 4. IOH = ma 2.4.2 2.4.2 V IOH = 24 ma 2 2 IOL = 2 ma 0. 0. IOL = 48 ma 0. 0. IOZH VCC =. V, VO = 2.7 V 0 0 µa IOZL VCC =. V, VI = 0.4 V 0 0 µa II VCC =. V, VI = 7 V 0. 0. ma IIH VCC =. V, VI = 2.7 V 20 20 µa IIL VCC =. V, VI = 0.4 V 0. 0. ma IO VCC =. V, VO = 2.2 V 0 2 0 2 ma Outputs high 4 7 4 7 ICC VCC =. V Outputs low 6 90 6 90 ma Outputs disabled 9 9 9 9 All typical values are at VCC = V, TA = 2 C. The output conditio have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS. UNIT UNIT V 4 POST OFFICE BOX 60 DALLAS, TEXAS 726
switching characteristics (see Figure ) PARAMETER tplh tphl FROM (INPUT) TO (OUTPUT) Any Q VCC = 4. V to. V, CL = 0 pf, R = 00 Ω, R2 = 00 Ω, TA = MIN to MAX SN4AS82A SN74AS82A MIN MAX MIN MAX. 9. 7.... tphl Any Q. 6... tpzh 4 2 4 OE Any Q tpzl 4 4 2 tphz 0. 8 OE Any Q tplz 0. 8 For conditio shown as MIN or MAX, use the appropriate value specified under recommended operating conditio. UNIT POST OFFICE BOX 60 DALLAS, TEXAS 726
PARAMETER MEASUREMENT INFORMATION SERIES 4ALS/74ALS AND 4AS/74AS DEVICES VCC 7 V RL = R = R2 S RL From Output Under Test CL (see Note A) RL Test Point From Output Under Test CL (see Note A) Test Point From Output Under Test CL (see Note A) R R2 Test Point LOAD CIRCUIT FOR BI-STATE TOTEM-POLE OUTPUTS LOAD CIRCUIT FOR OPEN-COLLECTOR OUTPUTS LOAD CIRCUIT FOR -STATE OUTPUTS Timing Input High-Level Pulse Data Input tsu th Low-Level Pulse tw SETUP AND HOLD TIMES PULSE DURATIONS Output Control (low-level enabling) Waveform S Closed (see Note B) Waveform 2 S Open (see Note B) tpzl tpzh tphz tplz VOL ENABLE AND DISABLE TIMES, -STATE OUTPUTS 0 V Input In-Phase Output Out-of-Phase Output (see Note C) tplh tphl tphl VOL tplh VOL PROPAGATION DELAY TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform is for an output with internal conditio such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditio such that the output is high except when disabled by the output control. C. When measuring propagation delay items of -state outputs, switch S is open. D. All input pulses have the following characteristics: PRR MHz, tr = tf = 2, duty cycle = 0%. E. The outputs are measured one at a time with one traition per measurement. Figure. Load Circuits and Voltage Waveforms 6 POST OFFICE BOX 60 DALLAS, TEXAS 726
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