Quantum-effect Resonant Tunneling Device Technology for Practical Ultra Low-power High-speed Applications

Quantum-effect Resonant Tunneling Device Technology for Practical Ultra Low-power High-speed Applications SEMATECH Symposium October 23 rd, 2012 Prof. Kyounghoon Yang High Speed Nanoelectronics Laboratory Department of Electrical Engineering KAIST Daejeon, Republic of Korea

Outline Background - Future Nano-Scale Devices/Technology - Resonant Tunneling Diodes: Principle & Advantages - Overview of RTD Research Areas Major Results on Quantum-effect RTD-Based ICs Part. I. Ultra low-power Analog RF Applications Part. II. High-speed Digital Applications Future Challenges of RTD Technology

Future Nano-Scale Devices/Technology ITRS 2009 Moore s Law and More Future Technical Road map Beyond CMOS Beyond CMOS: Nano/Quantum Device Technology 2010 Year 2020 IBM 2004 Quantum-effect device : Resonant Tunneling Diode (RTD), Single Electron Transistor (SET), Quantum Dot (QD) Nanotube Molecular device SPINTRONICS

Operation Resonant Tunneling Principle of Diode RTD Resonant Tunneling Phenomenon <Basic structure of RTD> (a) V RTD = 0 <Band Diagram> E F E 1 off Inherent Excellent NDR (RF Signal Generator) Bi-Stable Points (Self-Latching Operation) (b) V RTD = V p e on qv p I RTD NDR (c) V RTD = V v off qv v OFF V RTD Merits of RTD for Practical Device Technology Room Temperature Operation NDR Characteristics Compatibility Excellent Switching Speed The most stable device New functionality Compatible with Conv. Devices High-Speed Operation

InP-based RTD/HBT IC Technology at KAIST InP-based RTD/ HBT Fabrication Technology (In-Campus) RTD/HBT stacked Epi-layer RTD HBT Layers RTD HBT Varactor Inductor BCB passivation TFR InP substrate <Cross sectional View of MMIC> University-level 1.5 m Optical Lithography Device Fabrication: BCB passivation Multi-layer interconnect process Mask Count : 22 RTD PVCR 10 at 300K HBT = 50, f T /f MAX 100 / 100 GHz - IC performance up to 40 Gb/s - 1.5 m RTD/HBT MMIC Technology with reasonably high yield ( 97 %) and uniform characteristics has been developed at KAIST Fab. facility. Sub- m Scaling IC Technology will be utilized for the next-generation Quantum-effect ICs.

Research of RTD ICs at KAIST 1974 Invented by Esaki and Chang in 1974 ~1990 ~2000 Theoretical study on resonant tunneling Material growth of RTD layers (MBE, MOCVD) Initial application of the RTD - Digital : Inverter, threshold logic, MVL logic - Analog : Oscillator * Univ. of Michigan and Others. 1 st Practical High-speed NDR IC development (NTT) - RTD/HEMT MOBILE (35 Gb/s, RZ-mode) - Optical UTC-PD/RTD MOBILE (80 Gb/s, RZ-mode) * USA, Japan, Europe CLK RTD Output D RTD/HEMT MOBILE RZ D-FF 2001~2010 2011~ Research at KAIST (2001 2010) : supported by Frontier Program for Tera-level Nano-devices of MOST, Korea Ultimate Potential of RTD NDR-ICs for Practical Applications: High-speed/Low-power/High-functionality - Digital : D-Flip flop, MUX, DEMUX - Analog : Oscillator, VCO RTD-based ICs for practical application - Better or comparable performance to the conv. transistor-based ICs Target application: - Low power/high speed digital communication - Ultra-low power wireless communication - Multi-functional logic array

Research on Low-power RF system Low power short-range wireless transceiver systems Transmitter Receiver Antenna Antenna Data Modulator Oscillator Low-power and short-range RFID, Sensor system, Wireless interconnect smaller antenna & wider bandwidth Low Noise Amplifier Mixer Demodulator Oscillator Data Previously reported RTD-based Analog ICs at KAIST Ku-band RTD VCO :14.9 GHz, 87 μw (2009) Ka-band RTD VCO :29 GHz, 85 μw (2010) Digital-mode RTD VCO :5.8 GHz, 1.3 pj/bit (2012)

Analog Osc. - Ultra-low Power Ka-band RTD VCO Circuit Schematic Microphotograph Measured Output spectrum Center freq.= 29 GHz Performance Comparison Total DC Power (mw) 100 0.25 m SiGe BiCMOS (JSSC, 2004) 10 1 130 nm CMOS (MWCL, 2010) 90nm CMOS (WCECS, 2010) 0.1 1.5 m RTD (KAIST) 0.01 16 18 20 22 24 26 28 30 32 Center Frequency (GHz) * Published at IEEE, Tran. On Nanotech., 2010 Performance summary DC Power Consumption (Core) : 85 μw Figure of Merit (FOM): - 193 dbc/hz Extremely Low Power: 1/50 (vs. 90-nm CMOS) The RTD-based push-push VCOs with extremely low-power characteristics have been successfully developed.

Digital Osc. - Low-power 5.8 GHz Digital-mode Oscillator Circuit Schematic Microphotograph Measured Output waveform 1 Gb/s modulation Performance Summary Power Consumption (mw) 6 5 4 3 2 1 250 nm CMOS (IMS, 2005) 180 nm CMOS (TMTT, 2010) 180 nm CMOS (IMS, 2007) 0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 Data Rate (Gb/s) * Published at IEEE, Tran. On Nanotech., 2012 1.5 m RTD/HBT (KAIST) Center Freq.: 5.8 GHz Power Consumption: 1.3 mw Data Rate: 1 Gb/s Energy Efficiency: 1.3 pj/bit Excellent Energy Efficiency: 1/20 (vs. 180-nm CMOS) The RTD-based Digital-mode oscillator with extremely low-power characteristics has been successfully developed.

DC Power (mw) Performance Summary of RTD Oscillators 12~40 GHz RF Oscillator 100 10 1 0.1 180 nm CMOS 130 nm CMOS 180 nm CMOS 130 nm CMOS 90 nm CMOS 130 nm CMOS 130 nm CMOS 90nm CMOS RTD Diff. RTD Single VCO VCO RTD Diff. VCO 90 nm CMOS RTD Diff. VCO 1.5 m RTD/HBT (KAIST) RTD push-push VCO 0.01 8 12 16 20 24 28 32 36 Center Frequency (GHz) ISM-band Digital-mode Oscillator Power Consumption (mw) 6 5 4 3 2 1 250 nm CMOS (IMS, 2005) 180 nm CMOS (TMTT, 2010) 180 nm CMOS (IMS, 2007) 20 times better Energy efficiency! 1.5 m RTD/HBT (KAIST) 0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 Data Rate (Gb/s) Extremely Low-power Characteristic 1/50 (vs. 90-nm CMOS) Excellent Energy Efficiency 1/20 (vs. 180-nm CMOS) The low power characteristics of the Analog RF RTD Applications are the best among those of reported MMIC Applications.

High-speed/Low-power Quantum-Effect ICs High-speed Digital Transceiver System High-Speed Transmitter High-Speed Receiver Electrical Input M U X Retimer D Q D-FF LD Optical Signal Optical Fiber PD Limiting Amp. Retimer D Q D-FF D E M U X Electrical Output %N Frequency Synthesizer Clock Recovery %N Previously reported RTD-based Digital ICs at KAIST Frequency Divider - 32 Gb/s, 33 mw (2006) NRZ D Flip-flop - 36 Gb/s, 20 mw (2008) 2:1 Multiplexer - 45 Gb/s, 22.5 mw (2009) 1:2 De-Multiplexer - 40 Gb/s, 61 mw (2012)

Research Motivation of RTD Digital ICs Advantages of RTD-based NDR ICs High Functionality Reduced Device Count High-speed & Low-power Operation Conventional Digital IC RTD-based NDR IC Clock RTD Data OUT [ECL NRZ D-Flip Flop] [MOBILE RZ D-Flip Flop, NTT ] Future 100 Gb/s-level Communication System High-Speed Digital ICs High-Efficiency Digital ICs High-functionality Multi-valued Logic

Power Dissipation (mw) Digital IC (I) _ New RTD/HBT D-Flip Flop IC Circuit Diagram Micrograph Eye-diagram results at 36 Gb/s Data : 300 mv/div., 8.3 ps/div. OUT : 50 mv/div., 8.3 ps/div. * Newly proposed topology (IET, Circuits Devices Syst. 2008) Performance Comparison Performance Summary Power Dissipation (mw) 2000 1000 100 Constant Power- Delay-Product 64 pj 32 pj 16 pj 8 pj 4 pj 2 pj 10 10 20 30 40 60 100 200 Operating Speed (Gb/s) 1 pj 0.1 µm InP HEMT [8] 1.5 µm InP HBT [6] 0.13 µm InP HEMT [9] 1.0 µm InP HBT InP [1] HEMT 1.0 µm InP HBT [2] 1.0 µm InP HBT[4] 1.0 µm InP HBT [7] 1.0 µm InP 0.8 µm InP HBT [10] 1 μm InP HBT 130 nm SiGe HBT 0.6 μm InP HBT 0.5 pj HBT [3] 0.13 µm SiGe HBT [5] 0.6 µm InP HBT [11] 0.25 pj Operating Speed (Gb/s) 130 nm 1.5 m RTD/HBT (KAIST) Technology 90 nm CMOS ( University of Toronto,2005 ) 1.5 µm RTD/HBT (KAIST) Device Count 20 12 (1/2) Power Consumption 40 mw 20 mw (1/2) Power-delay product 1.00 pj 0.55 pj The RTD/HBT based high-speed/low-power D-Flip Flop has been developed.

Digital IC (II) _ 40 Gb/s Level 2:1 MUX & 1:2 De-MUX ICs RTD-based 2:1 Multiplexer IC Circuit Diagram D 1 D 1 I EE1 CLK V EE I EE2 V EE OUT I EE1 CLK V EE * New topology (IEEE, TNANO, 2009) D 2 D 2 Eye-diagram - 45 Gb/s Operation 75 mv 75 mv/div Performance summary Technology 0.12 μm CMOS (Infineon) 1.5 µm RTD/HBT (KAIST) Device count 42 19 (1/2) Operation Speed 40 Gb/s 45 Gb/s Power Consumption 100 mw 22.5mW (1/4) RTD-based 1:2 De-Multiplexer IC Block diagram * New topology (IEEE, TNANO, 2012) Eye-diagram - 40 Gb/s Operation 130 mv OUT A OUT B Performance summary Technology 0.12 μm CMOS (Infineon) 1.5 µm RTD/HBT (KAIST) Device count 40 24 (2/3) Operation Speed 40 Gb/s 40 Gb/s Power Consumption 108 mw 61 mw (2/3) The world s first quantum-effect based 40 Gb/s level 2:1 multiplexer and 1:2 de-multiplexer ICs have been developed with the lowest power consumption.

Merits Commercialization of RTD for Practical Potential Device of RTD Technology NDR-ICs Quantum Device/Transistor Technology Compatible with commercial III-V IC Technology (HBT or HEMT) RTD Emitter Stacked RTD Double barrier RTD RTD Structure Collector Emitter Base Grading Layer Structure Collector Sub-collector Buffer Semi-Insulating Conv. HBT (HEMT) RTD Layer Structure Commercial Quantum-effect HBT MMIC * Recent Commercialization Trend : Device Hetero-Integration 4 Major Foundry Companies (RFMD, WIN, ANADIGICS, TriQuint) (BiFET : HBT + FET) Our approach of RTD Device Hetero Integration (RTD + HBT / HEMT) is also feasible for Commercialization. RTD technology is compatible with the Conv. III-V IC Technology.

3D Hetero-integration on Silicon (I) Epitaxial Growth on Si substrate <Non-selective Growth on Si> - Intel, IEDM 2011 - III-V FET on Silicon - Direct epitaxial growth (III-V buffer layer growth) - Molecular Beam Epitaxy <Selective Regrowth on Si> - IMEC, IPRM 2012 - InGaAs channel MOS - Shallow trench isolation - Ge seed deposition - MOVPE STI trenches (II) Hybrid Integration <Through-Silicon Via (TSV)> - Micron, Intel, IMEC, IEDM 2010 Extended to the integration of an - 3-D stacking of chips RTD on Si-CMOS technology - Higher packing density The III-V devices on Si substrates can be key components in advanced VLSIs. Hetero-integration of RTD with silicon CMOS is also feasible for commercialization.

Promising Research Areas of RTD Future super-intelligence Nano System - Artificial neural network system (Non-boolean operation) - Synapse function & Structure (Multi-valued logic) Deep sub-μm InP Resonant Tunneling Transistor Technology - High density (Device count: 1/10) - High speed (Time constant: 1/100) - Low power (Power diss.: 1/10) Research Direction High-speed Embedded Memory - Tunneling-based SRAM Cell RTD [Raytheon, Proc. of the IEEE, 1999] Sub-150 nm InP RTD/Transistor Technology - Fast access time (Time delay : 1/100) - Energy-saving (Power diss.: 1/100)

Acknowledgment - This work was supported by the National Program for Tera-level Nano-devices (TND, 2000~2010) of Education, Science, and technology in the Republic of Korea as one of the 21 st Century Frontier Programs, - Continuously, this work has been supported by the 2012~2013 Year High-risk High-return Project (HRHRP) sponsored by KAIST - Professor Kyounghoon Yang - Ph.D candidate Kiwon Lee Jongwon Lee Jooseok Lee Jaehong Park Maengkyu Kim