Trends and Challenges in VLSI Technology Scaling Towards 100nm

Trends and Challenges in VLSI Technology Scaling Towards 100nm Stefan Rusu Intel Corporation stefan.rusu@intel.com September 2001 Stefan Rusu 9/2001 2001 Intel Corp. Page 1

Agenda VLSI Technology Trends Frequency and power trends Scaling Challenges Transistor scaling Interconnect scaling Capacitive and inductive coupling Leakage Summary Stefan Rusu 9/2001 2001 Intel Corp. Page 2

Process Technology Evolution 1961 First Planar Integrated Circuit Two transistors 2001 Pentium 4 Processor 42 million transistors Stefan Rusu 9/2001 2001 Intel Corp. Page 3

Moore s Law - 1965 Electronics,, April 1965 Stefan Rusu 9/2001 2001 Intel Corp. Page 4

Moore s Law - Today Number of transistors per integrated circuit doubles every two years Stefan Rusu 9/2001 2001 Intel Corp. Page 5

SIA Technology Roadmap Characteristic 1999 2001 2004 2008 Process Technology [nm] 180 130 90 60 Logic Transistors [mil] 23.8 47.6 135 539 Across-chip Clock Speed [MHz] 1200 1600 2000 2655 Die area [sq. mm] 340 340 390 468 Wiring Levels 6 7 8 9 Stefan Rusu 9/2001 2001 Intel Corp. Page 6

ITRS Roadmap Acceleration Continues 500 350 1994 FeatureSize(nm) 250 180 130 100 70 50 35 1997 1998/1999 2000 25 95 97 99 01 04 07 10 13 16 Year of Production ITRS 2000 Update Review December 2000 Stefan Rusu 9/2001 2001 Intel Corp. Page 7

Processor Frequency Trend 10,000 Intel Processors Frequency Gate delays/clock 100 Pentium 4 Frequency [MHz] 1,000 100 Pentium II Pentium Pro Pentium III 10 Pentium 386 486 10 1987 1989 1991 1993 1995 1997 1999 2001 2003 2005 Gate Delays / Clock 1 Frequency doubles each generation Number of gates per clock reduces by 25% Stefan Rusu 9/2001 2001 Intel Corp. Page 8

Processor Core Vs. Bus Clock 2500 2000 1500 1000 500 0 Core Clk Bus Clk 386 486-33 486DX2 486DX4 P-100 P-150 P-200 PII-300 PII-400 PIII-600 PIII-700 PIII-800 PIII-1G P4-1.5G P4-2.0G Clock Frequency (MHz) Processor Bus frequency is not keeping up with the processor core Stefan Rusu 9/2001 2001 Intel Corp. Page 9

Processor Power Trend 100 Pentium II Pentium 4 Power (Watts) 10 Pentium Pro Pentium 486 486 Pentium MMX Pentium III 386 386 1 1.5µ 1µ 0.8µ 0.6µ 0.35µ 0.25µ 0.18µ 0.13µ Lead processor power increases every generation Compactions provide higher performance at lower power Stefan Rusu 9/2001 2001 Intel Corp. Page 10

Power Density Trend Watts 250 200 150 100 50 0 Leakage Pwr Active Pwr Power Density 0.25µ 0.18µ 0.13µ 0.1µ 100 75 50 25 0 Power Density (W/cm 2 ) Assumptions: 15mm die, 1.5x frequency increase per generation Stefan Rusu 9/2001 2001 Intel Corp. Page 11

Voltage Scaling 10 Supply Voltage [V] 1 ~0.7X Scaling ~0.85X Scaling 0.1 1991 1993 1995 1997 1999 2001 2003 2005 2007 Year Stefan Rusu 9/2001 2001 Intel Corp. Page 12

Transistor Physical Gate Length 1 0.5um 0.35um 0.25um Technology Node Micron 0.1 0.2um 130nm 0.18um 0.13um 90nm 65nm 70nm 45nm Transistor Physical Gate Length 50nm 30nm 20nm 0.01 1991 1993 1995 1997 1999 2001 2003 2005 2007 2009 Year Source: Robert Chau, 6/2001 Stefan Rusu 9/2001 2001 Intel Corp. Page 13

0.13µm m Process Technology 70nm Lgate NMOS transistor in production today Source: S. Tyagi, et.al., IEDM 2000 Stefan Rusu 9/2001 2001 Intel Corp. Page 14

Transistor Physical Gate Length 1 0.5um 0.35um 0.25um Technology Node Micron 0.1 0.2um 130nm 0.18um 0.13um 90nm 65nm 70nm 45nm Transistor Physical Gate Length 50nm 30nm 20nm 0.01 1991 1993 1995 1997 1999 2001 2003 2005 2007 2009 Year Source: Robert Chau, 6/2001 Stefan Rusu 9/2001 2001 Intel Corp. Page 15

30nm Physical Gate Length Transistor For the 65nm technology node production 2005 Source: R. Chau, et.al., IEDM 2000 Stefan Rusu 9/2001 2001 Intel Corp. Page 16

Transistor Physical Gate Length 1 0.5um 0.35um 0.25um Technology Node Micron 0.1 0.2um 130nm 0.18um 0.13um 90nm 65nm 70nm 45nm Transistor Physical Gate Length 50nm 30nm 20nm 0.01 1991 1993 1995 1997 1999 2001 2003 2005 2007 2009 Year Source: R. Chau, 6/2001 Stefan Rusu 9/2001 2001 Intel Corp. Page 17

Research Transistor with 20nm Physical Gate Length For the 45nm technology node research phase Source: R. Chau, et.al., SNW 2001 Stefan Rusu 9/2001 2001 Intel Corp. Page 18

Oxide Thickness Scaling 5 Oxide Thickness [nm] 4 3 2 1 Equivalent Oxide Thickness (Physical) T OX (Electrical) 0 0.25 0.18 0.13 0.1 0.07 Technology Generation [um] Source: T. Ghani, VLSI Symposium, 2000 Stefan Rusu 9/2001 2001 Intel Corp. Page 19

Atoms-Thin Gate Oxide Source: R. Chau, et.al., IEDM 2000 Stefan Rusu 9/2001 2001 Intel Corp. Page 20

Moore s Law + 300mm Wafers = 4x advantage Moore s Law: From 0.18µm to 0.13µm = 2x output 300mm Wafers: From 200mm to 300mm = 2x output Combined output advantage: 4x output Stefan Rusu 9/2001 2001 Intel Corp. Page 21

0.13µm m Production Ramp Six factories readying 0.13µm m production Plan to spend $7.5B on capital in 2001 Yields and volume exceeding expectations 0.13µm m products have been shipping since May Stefan Rusu 9/2001 2001 Intel Corp. Page 22

Lithography Challenges 1 Lithography Wavelength Micron 0.1 Silicon Feature Size 0.01 1989 1991 1993 1995 1997 1999 2001 2003 2005 2007 Year Stefan Rusu 9/2001 2001 Intel Corp. Page 23

Extreme Ultraviolet Lithography EUV lithography uses extremely short wavelength light (20x shorter than today s lithography processes) Visible light 400 to 700 nm DUV lithography 193 and 248 nm EUV lithography 13 nm Will be used first in 2005 for critical lithography steps to produce 70 nm patterns World s First 6-inch EUV ETS Mask Stefan Rusu 9/2001 2001 Intel Corp. Page 24

SRAM Cell Size Scaling SRAM Cell Size [sq.um] 50 45 40 35 30 25 20 15 10 5 0 44 21 10.6 5.6 2.1 0.5 0.35 0.25 0.18 0.13 Technology Generation [um] SRAM cell size will continue to scale ~0.5x per generation Stefan Rusu 9/2001 2001 Intel Corp. Page 25

Exploit Memory Power Efficiency 100 Power Density (W/cm 2 ) 10 Logic Memory 1 0.25µ 0.18µ 0.13µ 0.1µ Static memory has 10X lower active power density Lower leakage than logic Integrated L2 provides higher bandwidth and lower latency Stefan Rusu 9/2001 2001 Intel Corp. Page 26

Example: Pentium III Processor Evolution 0.18µm m technology 256KB L2 28 million transistors 106 mm² die size 0.13µm m technology 512KB L2 44 million transistors 80 mm² die size Stefan Rusu 9/2001 2001 Intel Corp. Page 27

Bit Line Delay Scaling Normalized delay 1.2 1.0 0.8 0.6 0.4 Logic circuit delay Bit line delay (15% swing scaling) Bit line delay (constant swing) 0.2 0 0.25 0.18 0.13 0.10 Technology generation [µm] Bit line swing limited by parameter mismatch & differential noise Cell stability degrades with Vt lowering Reducing number of rows per bitline approaching limit Stefan Rusu 9/2001 2001 Intel Corp. Page 28

Process Fluctuations Die-to-Die Fluctuations Within-Die Fluctuations Systematic Random Resist Thickness Lens Aberrations Source: K. Bowman, et.al., ISSCC 2001 Random Placement of Dopant Atoms Stefan Rusu 9/2001 2001 Intel Corp. Page 29

0.18µm m Al Interconnect Metal 6 Metal 5 Metal 4 Metal 3 Metal 2 Metal 1 Transistors Stefan Rusu 9/2001 2001 Intel Corp. Page 30

Wires Are Not Scaling Well 45 40 35 30 Delay [ps] 25 20 15 10 5 0 0.65 0.5 0.35 0.25 0.18 0.13 0.1 Process Generation [um] Gate Al wires + SiO2 Cu wires + lowk Gate + Al wires Gate + Cu wires Source: SIA NTRS projection Stefan Rusu 9/2001 2001 Intel Corp. Page 31

0.13µm m Cu Interconnect Metal 6 Metal 5 Metal 4 Source: S. Tyagi, et.al., IEDM 2000 Metal 3 Metal 2 Metal 1 Transistors Stefan Rusu 9/2001 2001 Intel Corp. Page 32

7 Metal Layers Number of Metal Layers 6 5 4 3 2 1 0 1.5 1 0.8 0.6 0.35 0.25 0.18 0.13 Technology Generation [um] Stefan Rusu 9/2001 2001 Intel Corp. Page 33

Metal Aspect Ratios 2 Average Aspect Ratio 1.5 1 0.5 0 1.5 1 0.8 0.6 0.35 0.25 0.18 0.13 Technology Generation [um] Stefan Rusu 9/2001 2001 Intel Corp. Page 34

Interconnect RC Delay vs. Pitch 40% lower RC delay by using Cu + FSG ILD Source: S. Tyagi, et.al., IEDM 2000 Stefan Rusu 9/2001 2001 Intel Corp. Page 35

Routing a 70nm Processor M9 M8 Super-Fat Wiring Top 2 layers Global routing 25mm M7 M6 M5 M4 M3 M2 M1 Fat Wiring 2 metal layers Cluster-level routing Semi-Global Wiring 2 metal layers Unit-level routing Local Wiring 3 metal layers Block-level routing Stefan Rusu 9/2001 2001 Intel Corp. Page 36

Noise Sources Capacitive Coupling Due to electric field Near field effect Measures resistance to a voltage change Inductive Coupling Due to magnetic field Far field effect Measures resistance to a current change Frequency dependent Stefan Rusu 9/2001 2001 Intel Corp. Page 37

Inductive Noise 1E+02 1E+04 Impedance (Ohms/cm) 1E+01 1E+00 ωl R 1E-01 1E-02 1E+06 1E+07 1E+8 1E+9 Impedance (Ohms/cm) 1E+03 1E+02 1E+01 R ωl 1E+00 1E+08 1E+09 1E+10 1E+11 Frequency (Hz) Frequency (Hz) PCB (FR4) Signal Trace VLSI Metal Line Inductance of VLSI metal lines is becoming important at operating frequencies above 1GHz Stefan Rusu 9/2001 2001 Intel Corp. Page 38

Effects of Capacitive Coupling Capacitive coupling can translate into a noise problem Aggressor Victim or a delay problem Aggressor Victim Stefan Rusu 9/2001 2001 Intel Corp. Page 39

Worst Case Input Patterns far near victim near far C-only L-only C & L cancel C & L additive! Near attackers couple mostly by capacitance! Far attackers couple mostly by inductance! Lenz s law - a change in current will generate an opposing current which resists the change! Worst-case switching pattern when near and far attackers switch anti-phase Stefan Rusu 9/2001 2001 Intel Corp. Page 40

Inductive Noise Impact on Delay RLC delay w/ far-attackers switching up Delay RC ONLY delay RLC delay w/ far-attackers switching down 0 0.5 1 1.5 2 Coupling Coefficient! Capacitive noise effect on delay is modeled by coupling coefficient! Inductive noise affects delay too! Inductive noise can also decrease delay Stefan Rusu 9/2001 2001 Intel Corp. Page 41

Skin Effect in VLSI Circuits 10.0 Al [µm] Skin depth [ [µm] 1.0 2.1µm 2.6µm 0.65µm 0.8µm Cu [µm] 0.26µm 0.1 1 10 100 Frequency [GHz] 0.21µm Edge frequency is 5-9x 5 the clock frequency Stefan Rusu 9/2001 2001 Intel Corp. Page 42

Sub-Threshold Leakage Sub-threshold leakage increases for lower channel lengths and lower V T s Stefan Rusu 9/2001 2001 Intel Corp. Page 43

Estimated Power of a 15mm Processor Power (Watts) 70 60 50 40 30 20 10 0.25µm, 2V Leakage Active 0% 0% 0% 0% 1% 1% 1% 2% 3% Power (Watts) 70 60 50 40 30 20 10 0.18µm, 1.4V Leakage Active 0% 0% 1% 1% 2% 3% 5% 7% 9% 30 40 50 60 70 80 90 Temp (C) 100 110 30 40 50 60 70 80 90 Temp (C) 100 110 Power (Watts) 70 60 50 40 30 20 10 0.13µm, 1V 26% 1% 2% 3% 5% 8% 11% 15% 20% Leakage Active Power (Watts) 70 60 50 40 30 20 10 41% 49% 56% 0.1µm, 0.7V 33% 26% 19% 6% 9% 14% Leakage Active 30 40 50 60 70 80 90 Temp (C) 100 110 30 40 50 60 70 80 90 Temp (C) 100 110 Stefan Rusu 9/2001 2001 Intel Corp. Page 44

Leakage Impact Ioff (na/µm) 10,000 1,000 100 10 0.10µm 0.13µm 0.18µm 0.25µm 1 30 40 50 60 70 80 90 100 110 Temp (C) Design issues: Dynamic circuits may fail Design workarounds needed to guarantee burn-in functionality Test issues: IDDQ testing may become ineffective Thermal-runaway runaway problems, especially at burn-in Stefan Rusu 9/2001 2001 Intel Corp. Page 45

Conclusion We still have not found a fundamental barrier to extending Moore s law The challenges are Power and Efficiency Focus on dissipation, delivery, density VLSI technology scaling is expected to continue for the next decade Stefan Rusu 9/2001 2001 Intel Corp. Page 46