ECE 274 Digital Logic. Digital Design. RTL Design RTL Design Method. RTL Design Memory Components

Similar documents
ECE 274 Digital Logic Fall 2009 Digital Design

ECE 274 Digital Logic. Digital Design. Datapath Components Shifters, Comparators, Counters, Multipliers Digital Design

Digital Design. Chapter 1: Introduction

ECE 274 Digital Logic

The Discussion of this exercise covers the following points:

Digital Design. Sequential Logic Design -- Controllers. Copyright 2007 Frank Vahid

Experiment 3: Non-Ideal Operational Amplifiers

Application Note. Differential Amplifier

Experiment 3: Non-Ideal Operational Amplifiers

ECE 274 Digital Logic Fall Digital Design. RTL Design RTL Design Method: Preview Example. RTL Design RTL Design Method

CS 135: Computer Architecture I. Boolean Algebra. Basic Logic Gates

CHAPTER 2 LITERATURE STUDY

Sequential Logic (2) Synchronous vs Asynchronous Sequential Circuit. Clock Signal. Synchronous Sequential Circuits. FSM Overview 9/10/12

Synchronous Machine Parameter Measurement

Exercise 1-1. The Sine Wave EXERCISE OBJECTIVE DISCUSSION OUTLINE. Relationship between a rotating phasor and a sine wave DISCUSSION

A Novel Back EMF Zero Crossing Detection of Brushless DC Motor Based on PWM

ECE 274 Digital Logic Spring Digital Design. Combinational Logic Design Process and Common Combinational Components Digital Design

Mixed CMOS PTL Adders

MAXIMUM FLOWS IN FUZZY NETWORKS WITH FUNNEL-SHAPED NODES

MEASURE THE CHARACTERISTIC CURVES RELEVANT TO AN NPN TRANSISTOR

Math Circles Finite Automata Question Sheet 3 (Solutions)

CHAPTER 3 AMPLIFIER DESIGN TECHNIQUES

(CATALYST GROUP) B"sic Electric"l Engineering

Design of a Pipelined DSP Microprocessor MUN DSP2000

ABB STOTZ-KONTAKT. ABB i-bus EIB Current Module SM/S Intelligent Installation Systems. User Manual SM/S In = 16 A AC Un = 230 V AC

Inclined Plane Walking Compensation for a Humanoid Robot

Synchronous Machine Parameter Measurement

EET 438a Automatic Control Systems Technology Laboratory 5 Control of a Separately Excited DC Machine

Topic 20: Huffman Coding

Abacaba-Dabacaba! by Michael Naylor Western Washington University

Synchronous Generator Line Synchronization

Engineer-to-Engineer Note

ALTERNATIVE WAYS TO ENHANCE PERFORMANCE OF BTB HVDC SYSTEMS DURING POWER DISTURBANCES. Pretty Mary Tom 1, Anu Punnen 2.

First Round Solutions Grades 4, 5, and 6

& Y Connected resistors, Light emitting diode.

Understanding Basic Analog Ideal Op Amps

Algorithms for Memory Hierarchies Lecture 14

Module 9. DC Machines. Version 2 EE IIT, Kharagpur

Compared to generators DC MOTORS. Back e.m.f. Back e.m.f. Example. Example. The construction of a d.c. motor is the same as a d.c. generator.

Figure 2.14: Illustration of spatial frequency in image data. a) original image, f(x,y), b) plot of f(x) for the transect across image at the arrow.

April 9, 2000 DIS chapter 10 CHAPTER 3 : INTEGRATED PROCESSOR-LEVEL ARCHITECTURES FOR REAL-TIME DIGITAL SIGNAL PROCESSING

PB-735 HD DP. Industrial Line. Automatic punch and bind machine for books and calendars

CS2204 DIGITAL LOGIC & STATE MACHINE DESIGN fall 2008

Kirchhoff s Rules. Kirchhoff s Laws. Kirchhoff s Rules. Kirchhoff s Laws. Practice. Understanding SPH4UW. Kirchhoff s Voltage Rule (KVR):

Dataflow Language Model. DataFlow Models. Applications of Dataflow. Dataflow Languages. Kahn process networks. A Kahn Process (1)

Three-Phase Synchronous Machines The synchronous machine can be used to operate as: 1. Synchronous motors 2. Synchronous generators (Alternator)

Lab 8. Speed Control of a D.C. motor. The Motor Drive

Lecture 16: Four Quadrant operation of DC Drive (or) TYPE E Four Quadrant chopper Fed Drive: Operation

Discontinued AN6262N, AN6263N. (planed maintenance type, maintenance type, planed discontinued typed, discontinued type)

MOS Transistors. Silicon Lattice

Example. Check that the Jacobian of the transformation to spherical coordinates is

A Simple Approach to Control the Time-constant of Microwave Integrators

Student Book SERIES. Fractions. Name

Birka B22: threaded in variation

TUTORIAL Electric Machine Modeling

CAL. NX15 DUO-DISPLAY QUARTZ

Engineer-to-Engineer Note

Make Your Math Super Powered

Ultra Low Cost ACCELEROMETER

Adaptive Geometric Features Based Filtering Impulse Noise in Colour Images

INSTITUTE OF AERONAUTICAL ENGINEERING (Autonomous) Dundigal, Hyderabad

EE Controls Lab #2: Implementing State-Transition Logic on a PLC

Job Sheet 2. Variable Speed Drive Operation OBJECTIVE PROCEDURE. To install and operate a Variable Speed Drive.

DP400 / DM350. Inverter. Total Solutions from the Single Source Provider DP400 PULSED MAG - PULSED MIG CO2 - MAG - MIG - FCAW

Ultra Low Cost ACCELEROMETER

A Development of Earthing-Resistance-Estimation Instrument

Energy Harvesting Two-Way Channels With Decoding and Processing Costs

Threshold Logic Computing: Memristive-CMOS Circuits for Fast Fourier Transform and Vedic Multiplication

5 I. T cu2. T use in modem computing systems, it is desirable to. A Comparison of Half-Bridge Resonant Converter Topologies

Polar Coordinates. July 30, 2014

ABOUT THIS MANUAL ABOUT THIS MANUAL

The Math Learning Center PO Box 12929, Salem, Oregon Math Learning Center

From Off-The-Shelf to Market-Ready New Age Enclosures is your Single Source Solution. Let us quote modifiying our Stock Enclosures to meet your

Operation Manual. Addendum. Embroidery Machine. Product Code: 884-T13

Student Book SERIES. Patterns and Algebra. Name

001CK CK0012 FR-001CK0013 FR EN English

Joanna Towler, Roading Engineer, Professional Services, NZTA National Office Dave Bates, Operations Manager, NZTA National Office

This is a repository copy of Effect of power state on absorption cross section of personal computer components.

On the Description of Communications Between Software Components with UML

9.4. ; 65. A family of curves has polar equations. ; 66. The astronomer Giovanni Cassini ( ) studied the family of curves with polar equations

CS2204 DIGITAL LOGIC & STATE MACHINE DESIGN SPRING 2005

University of North Carolina-Charlotte Department of Electrical and Computer Engineering ECGR 4143/5195 Electrical Machinery Fall 2009

Regular languages can be expressed as regular expressions.

mac profile Configuration Guide Adobe Photoshop CS/CC Sawgrass Virtuoso SG400/SG800 Macintosh v

How to Build Wealth Like Warren Buffett.

Interference Cancellation Method without Feedback Amount for Three Users Interference Channel

Mini Mario & Friends: amiibo Challenge

From Off-The-Shelf to Market-Ready New Age Enclosures is your Single Source Solution. Let us quote modifiying our Stock Enclosures to meet your

METHOD OF LOCATION USING SIGNALS OF UNKNOWN ORIGIN. Inventor: Brian L. Baskin

Controls. Solid-State Switching Devices. Reference Manual April Low-Voltage Controls and Distribution

Section 2.2 PWM converter driven DC motor drives

Lecture 20. Intro to line integrals. Dan Nichols MATH 233, Spring 2018 University of Massachusetts.

Extremely small "footprint" and the highest circuit density available AK550. Front Wire Entry

Geometric quantities for polar curves

B inary classification refers to the categorization of data

Spiral Tilings with C-curves

Design And Implementation Of Luo Converter For Electric Vehicle Applications

Question Paper Wednesday 13 Thursday 14 January 2010

Simulation of Transformer Based Z-Source Inverter to Obtain High Voltage Boost Ability

THE present trends in the development of integrated circuits

Transcription:

ECE 27 Digitl Logic Memories n Hierrchy Digitl Design 5.6 5. Digitl Design Chpter 5: Slies to ccompny the textbook Digitl Design, First Eition, by Frnk Vhi, John Wiley n Sons Publishers, 27. http://www.vhi.com Copyright 27 Frnk Vhi Instructors of courses requiring Vhi's Digitl Design textbook (publishe by John Wiley n Sons) hve permission to moify n use these slies for customry course-relte ctivities, subject to keeping this copyright notice in plce n unmoifie. These slies my be poste s unnimte pf versions on publicly-ccessible course websites.. PowerPoint source (or pf with nimtions) my not be poste to publicly-ccessible websites, but my be poste for stuts on internl protecte sites or istribute irectly to stuts by other electronic mens. Instructors my mke printouts of the slies vilble to stuts for resonble photocopying chrge, without incurring roylties. Any other use requires explicit permission. Instructors my obtin PowerPoint source or obtin specil use permissions from Wiley see http://www.vhi.com for informtion. Metho Memory Componts 5.6 Register-trnsfer level esign instntites pth componts to crete pth, controlle by controller A few more componts re oft use outsie the controller n pth MxN memory M s, N bits wie ech M s Severl vrieties of memory, which we now introuce N-bits wie ech M N memo r y 3

Rnom Access Memory () Internl Structure Reble n writble memory Rnom ccess memory Strnge nme Crete severl eces go to contrst with sequtilly-ccesse storge like tpe rives Logiclly sme s register file Memory with ess inputs, inputs/outputs, n control usully just one port; register file usully two or more vs. register file typiclly lrger thn roughly 52 or 2 s typiclly stores bits using bit storge pproch tht is more efficit thn flip flop typiclly implemte on chip in squre rther thn rectngulr shpe keeps longest wires (hce ely) short W_ W_ W_ R_ 6 register file R_ R_ 2 R A M Register file from Chpt. block symbol 2x (A-) Let A = log 2 M AxM ecoer (A-) e (M-) to ll s w(n-) w(n-2) w ble r(n-) r(n-2) r bit storge block (k ) w o r Similr internl structure s register file Decoer bles pproprite bse on ess inputs rw controls whether is writt or re Let s see wht s insie ech ble ble 5 6 Sttic (S) 2x S Sttic (S) 2x Sttic 6 trnsistors (recll inverter is 2 trnsistors) Writing this ble input comes from ecoer Wh, vlue loops roun inverters Tht loop is where bit stys store Wh, the bit vlue ters the loop is the bit to be store in this ters on other sie Exmple shows being writt into ble S ble Sttic Reing this Somewht trickier Wh rw set to re, the logic sets both n to The store bit will pull either the left line or the right bit own slightly below Sse mplifiers etect which sie is slightly pulle own The electricl escription of S is relly beyon our scope just gerl ie here, minly to contrst with D... S < ble To sse mplifiers ble 7 2

Dynmic (D) Compring Memory Types 2x Dynmic trnsistor (rther thn 6) Relies on lrge cpcitor to store bit Write: Trnsistor conucts, voltge level gets store on top plte of cpcitor Re: Just look t vlue of Problem: Cpcitor ischrges over Must refresh regulrly, by reing n th writing it right bck D ble ble ( ) c ell cpcitor slowly ischrging ischrges ( b ) Register file Fstest But biggest size S Fst More compct thn register file D Slowest An refreshing tkes But very compct Use register file for smll items, S for lrge items, n D for huge items Note: D s big cpcitor requires specil chip esign process, so D is oft seprte chip register file MxN Memory implemte s : S D Size comprison for sme number of bits (not to scle) 9 Reing n Writing Exmple: Digitl Soun Recorer 2 3 9 3 9 5 mens write 999 Z 5 vli vli setup hol setup [9] [3] now equls 5 now equls 999 Writing ( b ) Put ess on lines, on lines, set rw=, = Reing Set n lines, but put nothing (Z) on lines, set rw= Dt will pper on lines Don t forget to obey setup n hol s In short keep inputs stble before n fter clock ege Z 5 ccess Behvior Recor: Digitize soun, store s series of 96 2-bit igitl vlues in We ll use 96x6 (2-bit wie not common) Ply bck lter Common behvior in telephone nswering mchine, toys, voice recorers To recor, processor shoul re -to-, store re vlues into successive s To ply, processor shoul re successive s n ble -to- 2 3

Exmple: Digitl Soun Recorer Exmple: Digitl Soun Recorer RTL esign of processor Crete high-level stte mchine Begin with the recor behvior Keep locl register Stores currt ess, rnges from to 95 (thus nee 2 bits) Crete stte mchine tht counts from to 95 using For ech Re nlog-to-igitl conv. _l=, _buf= Write to t ess R=, Rrw=, R= nlog-toigitl 6 _buf _l Recor behvior Locl register: (2 bits) S = 96x6 2 R Rw R processor T _l= _buf= R= Rrw= R= _l <95 U =+ =95 igitl-tonlog Now crete ply behvior Use locl register gin, crete stte mchine tht counts from to 95 gin For ech Re Write to igitl-to-nlog conv. Note: Must write -to- one cycle fte reing, wh the re is vilble on the bus The recor n ply stte mchines woul be prts of lrger stte mchine controlle by signls tht etermine wh to recor or ply nlog-toigitl 6 _buf _l Ply behvior V = 96x6 2 R Rw R processor Locl register: (2 bits) W _buf= R= Rrw= R= _l <95 X _l= =+ =95 bus igitl-tonlog 3 Re-Only Memory Re-Only Memory Memory tht cn only be re from, not writt to Dt lines re output only No nee for rw input Avntges over Compct: My be smller Nonvoltile: Sves bits ev if power supply is turne off Spee: My be fster (especilly thn D) Low power: Doesn t nee power supply to sve bits, so cn ext bttery life Choose over if store won t chnge (oon t chnge oft) For exmple, tble of Celsius to Fhrheit conversions in igitl thermometer 2 R A M block symbol 2x block symbol 2x block symbol (A-) Let A = log 2 M AxM ecoer (A-) e (M-) ble r(n-) r(n-2) r bit storge block (k ) Internl logicl structure similr to, without the input lines w o r ble ble 5 6

Types Types If cn only be re, how re the store bits store in the first plce? Storing bits in known s progrmming Severl methos Msk-progrmme Bits re hrwire s s or s uring chip mnufcturing 2-bit on right stores ble (from ecoer) simply psses the hrwire vlue through trnsistor Notice how compct, n fst, this memory woul be ble line line Fuse-Bse Progrmmble Ech hs fuse A specil evice, known s progrmmer, blows certin fuses (using higher-thnnorml voltge) Those s will be re s s (involving some specil electronics) Cells with unblown fuses will be re s s 2-bit on right stores Also known s One-Time Progrmmble (OTP) ble fuse line line blown fuse 7 Types Types Ersble Progrmmble (EP) Uses floting-gte trnsistor in ech Specil progrmmer evice uses higherthn-norml voltge to cuse electrons to tunnel into the gte Electrons become trppe in the gte Only one for s tht shoul store Other s (without electrons trppe in gte) will be 2-bit on right stores Detils beyon our scope just gerl ie is necessry here To erse, shine ultrviolet light onto chip Gives trppe electrons ergy to escpe Requires chip pckge to hve winow floting-gte trnsistor ble line line c ell c ell e Ð e Ð trppe electrons Electroniclly-Ersble Progrmmble (EEP) Similr to EP Uses floting-gte trnsistor, electronic progrmming to trp electrons in certin s But ersing one electroniclly, not using UV light Ersing one one t Flsh memory Like EEP, but ll s (or lrge blocks of s) cn be erse simultneously Become common reltively rectly (lte 99s) Both types re in-system progrmmble Cn be progrmme with new store bits while in the system in which the opertes Requires bi-irectionl lines, n write control input Also nee busy output to inicte tht ersing is in progress ersing tkes some write busy 2x EEP 9 2 5

Blurring of Distinction Betwe n Hierrchy n Abstrction We si tht is reble n writble Flsh EEP NV is re-only But some s ct lmost like s EEP n Flsh re in-system progrmmble Esstilly mens tht writes re slow Also, number of writes my be limite (perhps few million s) An, some s ct lmost like s Non-voltile s: Cn sve their without the power supply One type: Built-in bttery, my work for up to yers Another type: Inclues bckup for controllerites contts to before turning off New memory technologies evolving tht merge n befits e.g., M Bottom line Lot of choices vilble to esigner, must fin best fit with esign gols Hierrchy helps us mnge complexity To go from trnsistors to gtes, muxes, ecoers, registers, ALUs, controllers, pths, memories, queues, etc. Imgine trying to compreh controller n pth t the level of gtes Abstrction Hierrchy oft involves not just grouping items into new item, but lso ssociting higher-level behvioith the new item, known s bstrction e.g., n -bit er hs n unerstnble highlevel behvior it s two -bit binry numbers Frees esigner from hving to remember, or ev from hving to unerstn, the lower-level etils 7.. b7.. b -bit er ci c o s7.. s 2 22 Hierrchy n Composing Lrger Componts from Smller Versions Hierrchy n Composing Lrger Componts from Smller Versions A common tsk is to compose smller componts into lrger one Gtes: Suppose you hve plty of 3-input AND gtes, but nee 9-input AND gte Cn simple compose the 9-input gte from severl 3-input gtes Muxes: Suppose you hve x n 2x muxes, but nee n x mux s2 selects either top or bottom x ss select prticulr x input Implemts x mux inputs, 3 selects, one output Composing memory very common Mking memory s wier Esy just plce memories sie-by-sie until esire with obtine Shre ess/control lines, conctte lines Exmple: Compose 2x s into 2x 2x 2x 2x 2x P r o vin c e 2x (3..) 23 2 6

Hierrchy n Composing Lrger Componts from Smller Versions Creting memory with more s Put memories on top of one nother until the number of esire s is chieve Use ecoer to select mong the memories Cn use highest orer ess input(s) s ecoer input Although ctully, ny ess line coul be use Exmple: Compose 2x memories into 2x memory just chooses which memory to ccess 9 2x 2x 9.. x2 i c e 2x 2x 2x To crete memory with more s n wier s, cn first compose to ough s, th wi. 25 7