TMS2C12 24288-BIT UV RSBL PROGRMMBL TMS2PC12 24288-BIT PROGRMMBL RD-ONLY MMORY This Data Sheet is pplicable to ll TMS2C12s and TMS2PC12s Symbolized with Code B as Described on Page 182. Organization...64K 8 Single -V Power Supply Pin Compatible With xisting 12K MOS ROMs, PROMs, and PROMs ll Inputs/Outputs Fully TTL Compatible Max ccess/min Cycle Time V CC ± 10% 2C/PC12-10 100 ns 2C/PC12-12 120 ns 2C/PC12-0 ns 2C/PC12-20 200 ns 2C/PC12-2 20 ns Power Saving CMOS Technology Very High-Speed SNP! Pulse Programming 3-State Output Buffers 400-mV Minimum DC Noise Immunity With Standard TTL Loads Latchup Immunity of 20 m on ll Input and Output Lines Low Power Dissipation ( V CC =.2 V ) ctive... 8 mw Worst Case Standby...1.4 mw Worst Case (CMOS Input Levels) PP4 Version vailable With 168-Hour Burn-In, and Choices of Operating Temperature Ranges 12K PROM vailable With MIL-STD-883C Class B High Reliability Processing (SMJ2C12) description The TMS2C12 series are 24 288-bit, ultraviolet-light erasable, electrically programmable read-only memories. The TMS2PC12 series are 24 288-bit, onetime electrically programmable read-only memories. 6 4 3 2 1 0 DQ0 0 DQ0 DQ G /VPP GND NU VCC 6 8 10 12 13 J ND N PCKGS ( TOP VIW ) 12 6 4 3 2 1 0 DQ0 DQ1 DQ2 GND 1 2 3 4 6 8 10 12 13 14 28 2 26 2 24 23 22 21 20 1 18 1 16 4 3 2 1 32 31 30 14 16 1 18 1 20 DQ1 DQ2 FM PCKG ( TOP VIW ) 12 NU V CC 14 13 GND NU DQ3 PIN NOMLTUR V CC 14 13 8 G/V PP 10 DQ DQ6 DQ DQ4 DQ3 DQ4 DQ 2 28 2 26 2 24 23 22 21 8 G/V PP 10 DQ DQ6 ddress Inputs Chip nable/powerdown Inputs (programming) / Outputs 13-V Programming Power Supply Ground No Internal Connection Make No xternal Connection -V Power Supply PRODUCTION DT information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 1, Texas Instruments Incorporated POST OFFIC BOX 1443 HOUSTON, TXS 21 1443 1
TMS2C12 24288-BIT UV RSBL PROGRMMBL TMS2PC12 24288-BIT PROGRMMBL RD-ONLY MMORY TMS2PC12 DD PCKG ( TOP VIW ) 8 13 14 V CC 12 6 4 1 2 3 4 6 8 10 12 13 14 16 32 31 30 2 28 2 26 2 24 23 22 21 20 1 18 1 G / V PP 10 DQ DQ6 DQ DQ4 DQ3 V SS DQ2 DQ1 DQ0 0 1 2 3 TMS2PC12 DU PCKG RVRS PINOUT ( TOP VIW ) G / V PP 10 DQ DQ6 DQ DQ4 DQ3 V SS DQ2 DQ1 DQ0 0 1 2 3 1 2 3 4 6 8 10 12 13 14 16 32 31 30 2 28 2 26 2 24 23 22 21 20 1 18 1 8 13 14 V CC 12 6 4 2 POST OFFIC BOX 1443 HOUSTON, TXS 21 1443
TMS2C12 24288-BIT UV RSBL PROGRMMBL TMS2PC12 24288-BIT PROGRMMBL RD-ONLY MMORY description (continued) These devices are fabricated using power-saving CMOS technology for high speed and simple interface with MOS and bipolar circuits. ll inputs (including program data inputs) can be driven by Series 4 TTL circuits without the use of external pull-up resistors. ach output can drive one Series 4 TTL circuit without external resistors. The data outputs are three-state for connecting multiple devices to a common bus. The TMS2C12 and the TMS2PC12 are pin compatible with 28-pin 12K MOS ROMs, PROMs, and PROMs. The TMS2C12 PROM is offered in a dual-in-line ceramic package (J suffix) designed for insertion in mounting hole rows on,2-mm (600-mil) centers. The TMS2PC12 OTP PROM is offered in a dual-in-line plastic package (N suffix) designed for insertion in mounting hole rows on,2-mm (600-mil) centers. The TMS2PC12 OTP PROM is also supplied in a 32-lead plastic leaded chip carrier package using 1,2-mm (0-mil) lead spacing (FM suffix), and in a 32-lead thin small-outline package (DD and DU suffixes). The TMS2C12 and TMS2PC12 are offered with two choices of temperature ranges of 0 C to 0 C (JL, NL, FML, and DDL suffixes) and 40 C to 8 C (J, N, FM, and DD suffixes). The TMS2C12 and TMS2PC12 are also offered with a 168-hour burn-in on both temperature ranges (JL4, NL4, FML4, DDL4, J4, N4, FM4, and DD4 suffixes); see table below. ll package styles conform to JDC standards. PROM ND OTP SUFFIX FOR OPRTING TMPRTUR RNGS WITHOUT PP4 BURN-IN SUFFIX FOR PP4 168 HR. BURN-IN VS TMPRTUR RNGS PROM 0 C TO 0 C 40 C TO 8 C 0 C TO 0 C 40 C TO 8 C TMS2C12-xxx JL J JL4 J4 TMS2PC12-xxx NL N NL4 N4 TMS2PC12-xxx FML FM FML4 FM4 TMS2PC12-xxx DDL DD DDL4 DD4 TMS2PC12-xxx DUL DU DUL4 DU4 These PROMs and OTP PROMs operate from a single -V supply (in the read mode), thus are ideal for use in microprocessor-based systems. One other 13-V supply is needed for programming. ll programming signals are TTL level. The device is programmed using the SNP! Pulse programming algorithm. The SNP! Pulse programming algorithm uses a V PP of 13 V and a V CC of 6. V for a nominal programming time of seven seconds. For programming outside the system, existing PROM programmers can be used. Locations can be programmed singly, in blocks, or at random. POST OFFIC BOX 1443 HOUSTON, TXS 21 1443 3
TMS2C12 24288-BIT UV RSBL PROGRMMBL TMS2PC12 24288-BIT PROGRMMBL RD-ONLY MMORY operation The seven modes of operation are listed in the following table. The read mode requires a single -V supply. ll inputs are TTL level except for V PP during programming (13 V for SNP! Pulse) and 12 V on for signature mode. MOD FUTION RD OUTPUT DISBL STNDBY PROGRMMING VRIFY PROGRM INHIBIT SIGNTUR MOD VIH VIH G /VPP VIH X VPP VPP VCC VCC VCC VCC VCC VCC VCC VCC X X X X X X VH VH 0 X X X X X X VIH COD DQ0 DQ Data Out Hi-Z Hi-Z Data In Data Out Hi-Z MFG DVIC X can be or VIH. VH = 12 V ± 0. V. 8 read/ output disable When the outputs of two or more TMS2C12s or TMS2PC12s are connected in parallel on the same bus, the output of any particular device in the circuit can be read with no interference from the competing outputs of the other devices. To read the output of a single device, a low-level signal is applied to the and G/V PP pins. ll other devices in the circuit should have their outputs disabled by applying a high-level signal to one of these pins. Output data is accessed at pins DQ0 through DQ. latchup immunity Latchup immunity on the TMS2C12 and TMS2PC12 is a minimum of 20 m on all inputs and outputs. This feature provides latchup immunity beyond any potential transients at the P.C. board level when the devices are interfaced to industry-standard TTL or MOS logic devices. Input-output layout approach controls latchup without compromising performance or packing density. power down ctive I CC supply current can be reduced from 30 m to 00 µ (TTL-level inputs) or 20 µ (CMOS-level inputs) by applying a high TTL/CMOS signal to the pin. In this mode all outputs are in the high-impedance state. erasure ( TMS2C12) Before programming, the TMS2C12 PROM is erased by exposing the chip through the transparent lid to a high intensity ultraviolet light (wavelength 23 angstroms). PROM erasure before programming is necessary to assure that all bits are in the logic high state. Logic lows are programmed into the desired locations. programmed logic low can be erased only by ultraviolet light. The recommended minimum exposure dose (UV intensity exposure time) is -W s/cm 2. typical 12-mW/cm 2, filterless UV lamp erases the device in 21 minutes. The lamp should be located about 2. cm above the chip during erasure. It should be noted that normal ambient light contains the correct wavelength for erasure. Therefore, when using the TMS2C12, the window should be covered with an opaque label. 4 POST OFFIC BOX 1443 HOUSTON, TXS 21 1443
TMS2C12 24288-BIT UV RSBL PROGRMMBL TMS2PC12 24288-BIT PROGRMMBL RD-ONLY MMORY initializing (TMS2PC12) The one-time programmable TMS2PC12 PROM is provided with all bits in the logic high state, then logic lows are programmed into the desired locations. Logic lows programmed into a PROM cannot be erased. SNP! Pulse programming The 12K PROM and OTP PROM are programmed using the TI SNP! Pulse programming algorithm illustrated by the flowchart in Figure 1, which programs in a nominal time of seven seconds. ctual programming time varies as a function of the programmer used. The SNP! Pulse programming algorithm uses initial pulses of 100 microseconds (µs) followed by a byte verification to determine when the addressed byte has been successfully programmed. Up to 10 (ten) 100-µs pulses per byte are provided before a failure is recognized. The programming mode is achieved with G/V PP = 13 V, V CC = 6. V, and =V IL. Data is presented in parallel (eight bits) on pins DQ0 to DQ. Once addresses and data are stable, is pulsed. More than one device can be programmed when the devices are connected in parallel. Locations can be programmed in any order. When the SNP! Pulse programming routine is complete, all bits are verified with V CC = V, G/V PP = V IL, and = V IL. program inhibit Programming can be inhibited by maintaining a high level input on the pin. program verify Programmed bits can be verified when G/V PP and = V IL. signature mode The signature mode provides access to a binary code identifying the manufacturer and type. This mode is activated when is forced to 12 V ± 0. V. Two identifier bytes are accessed by 0; i.e., 0 = V IL accesses the manufacturer code, which is output on DQ0 DQ; 0 = V IH accesses the device code, which is output on DQ0 DQ. ll other addresses must be held at V IL. The manufacturer code for these devices is, and the device code is 8. POST OFFIC BOX 1443 HOUSTON, TXS 21 1443
TMS2C12 24288-BIT UV RSBL PROGRMMBL TMS2PC12 24288-BIT PROGRMMBL RD-ONLY MMORY Start ddress = First Location VCC = 6. V ± 0.2 V, G /VPP = 13 V ± 0.2 V Program Mode Program One Pulse = tw = 100 µs Increment ddress Last ddress? No Yes ddress = First Location X = 0 Program One Pulse = tw = 100 µs No Increment ddress Verify One Byte Fail X = X + 1 X = 10? Interactive Mode Pass No Last ddress? Yes VCC = V ± 0. V, G /VPP = Yes Device Failed Compare ll Bytes To Original Data Fail Final Verification Pass Device Passed Figure 1. SNP! Pulse Programming Flowchart 6 POST OFFIC BOX 1443 HOUSTON, TXS 21 1443
logic symbols TMS2C12 24288-BIT UV RSBL PROGRMMBL TMS2PC12 24288-BIT PROGRMMBL RD-ONLY MMORY 0 1 2 3 4 6 8 10 12 13 14 G /VPP 10 8 6 4 3 2 24 21 23 2 26 2 1 20 22 0 [PWR DWN] & N PROM 6 36 8 0 6 3 12 13 16 1 18 1 DQ0 DQ1 DQ2 DQ3 DQ4 DQ DQ6 DQ 0 1 2 3 4 6 8 10 12 13 14 10 8 6 4 3 2 24 21 23 2 26 2 1 20 22 G /VPP 0 [PWR DWN] & N OTP PROM 6 36 8 0 6 3 12 13 16 1 18 1 DQ0 DQ1 DQ2 DQ3 DQ4 DQ DQ6 DQ These symbols are in accordance with NSI / I Std 1-184 and IC Publication 61-12. Pin numbers shown are for J and N packages. absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, V CC (see Note 1).............................................. 0.6 V to V Supply voltage range, V PP......................................................... 0.6 V to 14 V Input voltage range (see Note 1): ll inputs except........................... 0.6 V to V CC + 1 V............................................... 0.6 V to 13. V Output voltage range (see Note 1)............................................ 0.6 V to V CC + 1 V Operating free-air temperature range ( 2C12- JL and JL4, 2PC12- NL and NL4, FML and FML4, DDL and DDL4).................... 0 C to 0 C Operating free-air temperature range ( 2C12- J and J4, 2PC12- N and N4, FM and FM4, DD and DD4)................ 40 C to 8 C Storage temperature range, T stg.................................................. 6 C to 0 C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. xposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOT 1: ll voltage values are with respect to GND. POST OFFIC BOX 1443 HOUSTON, TXS 21 1443
TMS2C12 24288-BIT UV RSBL PROGRMMBL TMS2PC12 24288-BIT PROGRMMBL RD-ONLY MMORY recommended operating conditions VCC Supply voltage MIN NOM MX UNIT Read mode (see Note 2) 4.. SNP! Pulse programming algorithm 6.2 6. 6. G /VPP Supply voltage SNP! Pulse programming algorithm 12. 13 13.2 V VIH T T NOT 2: High-level dc input voltage Low-level dc input voltage Operating free-air temperature Operating free-air temperature TTL 2 VCC+1 CMOS VCC 0.2 VCC+1 TTL 0. 0.8 CMOS 0. 0.2 V TMS2C12- JL, JL4 TMS2PC12- NL, NL4, FML, FML4, DDL, DDL4 0 0 C TMS2C12- J, J4 TMS2PC12- N, N4, FM, FM4, DD, DD4 40 8 C VCC must be applied before or at the same time as G/VPP and removed after or at the same time as G /VPP. The device must not be inserted into or removed from the board when VPP or VCC is applied. electrical characteristics over recommended ranges of supply voltage and operating free-air temperature VOH VOL High-level dc output voltage Low-level dc output voltage PRMTR TST CONDITIONS MIN TYP MX UNIT IOH = 2. m 3. IOH = 20 µ VCC 0.1 IOL = 2.1 m 0.4 IOL = 20 µ 0.1 II Input current (leakage) VI = 0 V to. V ±1 µ IO Output current (leakage) VO = 0 V to VCC ±1 µ IPP G /VPP supply current (during program pulse) G /VPP = 13 V 3 0 m ICC1 ICC2 VCC supply current (standby) VCC supply current (active) TTL-input level VCC =. V,..... = VIH 20 00 CMOS-input level VCC =. V,..... = VCC 100 20 VCC =. V, =, tcycle = minimum cycle time, outputs open V V V V µ 30 m capacitance over recommended ranges of supply voltage and operating free-air temperature, f = 1 MHz PRMTR TST CONDITIONS MIN TYP MX UNIT CI Input capacitance VI = 0 V, f = 1 MHz 6 10 pf CO Output capacitance VO = 0 V, f = 1 MHz 10 14 pf CG / VPP G /VPP input capacitance G /VPP = 0 V, f = 1 MHz 20 2 pf Typical values are at T = 2 C and nominal voltages. Capacitance measurements are made on a sample basis only. 8 POST OFFIC BOX 1443 HOUSTON, TXS 21 1443
TMS2C12 24288-BIT UV RSBL PROGRMMBL TMS2PC12 24288-BIT PROGRMMBL RD-ONLY MMORY switching characteristics over recommended ranges of operating conditions 2C12-10 2PC12-10 2C12-12 2PC12-12 TST CONDITIONS PRMTR UNIT (S NOTS 3 ND 4) MIN MX MIN MX ta() ccess time from address 100 120 ns ta() ccess time from chip enable 100 120 ns CL = 100 pf, ten(g) Output enable time from G /VPP 1 Series 4 TTL Load, ns tdis Output disable time from G /VPP or, whichever occurs first Input tr 20 ns, 0 4 0 4 ns Input tf 20 ns Output data valid time after change of address,, or G /VPP, tv() 0 0 ns whichever occurs first PRMTR TST CONDITIONS (S NOTS 3 ND 4) 2C12-2PC12- MIN MX ta() ccess time from address 0 ns ta() ccess time from chip enable 0 ns CL = 100 pf, ten(g) Output enable time from G /VPP 1 Series 4 TTL Load, ns tdis Output disable time from G /VPP or, whichever occurs first Input tr 20 ns, 0 60 ns Input tf 20 ns Output data valid time after change of address,, or G /VPP, whichever tv() 0 ns occurs first UNIT 2C12-20 2PC12-20 2C12-2 2PC12-2 TST CONDITIONS PRMTR UNIT (S NOTS 3 ND 4) MIN MX MIN MX ta() ccess time from address 200 20 ns ta() ccess time from chip enable 200 20 ns CL = 100 pf, ten(g) Output enable time from G /VPP 1 Series 4 TTL Load, 100 ns tdis Output disable time from G /VPP or, whichever occurs first Input tr 20 ns, 0 60 0 60 ns Input tf 20 ns Output data valid time after change of address,, or G /VPP, tv() 0 0 ns whichever occurs first Value calculated from 0. V delta to measured output level. This parameter is only sampled and not 100% tested. switching characteristics for programming: V CC = 6.0 V and G/V PP = 13 V (SNP! Pulse), T = 2 C (see Note 3) PRMTR MIN MX UNIT tdis(g) Disable time, output from G /VPP 0 130 ns NOTS: 3. For all switching characteristics the input pulse levels are 0.4 V to 2.4 V. Timing measurements are made at 2 V for logic high and 0.8 V for logic low. (Reference page 10.) 4. Common test conditions apply for tdis except during programming. POST OFFIC BOX 1443 HOUSTON, TXS 21 1443
TMS2C12 24288-BIT UV RSBL PROGRMMBL TMS2PC12 24288-BIT PROGRMMBL RD-ONLY MMORY recommended timing requirements for programming: V CC = 6.0 V and G/V PP = 13 V (SNP! Pulse), T = 2 C (see Note 3) MIN TYP MX UNIT tw(ipgm) Pulse duration, initial program 100 10 µs tsu() Setup time, address 2 µs tsu(d) Setup time, data 2 µs tsu(vpp Setup time, G /VPP 2 µs tsu(vcc) Setup time, VCC 2 µs th() Hold time, address 0 µs th(d) Hold time, data 2 µs th(vpp) Hold time, G /VPP 2 µs trec(pg) Recovery time, G /VPP 2 µs thd Data valid from low 1 µs tr(pg)g Rise time, G /VPP 0 ns NOT 3. For all switching characteristics the input pulse levels are 0.4 V to 2.4 V. Timing measurements are made at 2 V for logic high and 0.8 V for logic low. (Reference below.) PRMTR MSURMNT INFORMTION 2.08 V Output Under Test RL = 800 Ω CL = 100 pf C testing input/output wave forms Figure 2. C Testing Output Load Circuit 2.4 V 0.4 V 2 V 0.8 V 2 V 0.8 V.C. testing inputs are driven at 2.4 V for logic high and 0.4 V for logic low. Timing measurements are made at 2 V for logic high and 0.8 V for logic low for both inputs and outputs. 10 POST OFFIC BOX 1443 HOUSTON, TXS 21 1443
TMS2C12 24288-BIT UV RSBL PROGRMMBL TMS2PC12 24288-BIT PROGRMMBL RD-ONLY MMORY PRMTR MSURMNT INFORMTION 0 ddresses Valid VIH ta() VIH ta() VIH G /VPP DQ0 DQ Hi-Z ten(g) tv() Output Valid tdis Hi-Z VOH VOL Figure 3. Read-Cycle Timing 0 ddress Stable VIH tsu() th() DQ0 DQ Data-In Stable tsu(d) th(d) Hi-Z Data-Out Valid tdis(g) VIH / VOH / VOL G /VPP th(vpp) tsu(vpp) thd VPP tr(pg)g trec(pg) tsu(vcc) VIH tw(ipgm) VCC tdis(g) is a characteristic of the device but must be accommodated by the programmer. 13-V G /VPP and 6.-V VCC for SNP! Pulse programming. VCC VCC Figure 4. Program-Cycle Timing (SNP! Pulse Programming) POST OFFIC BOX 1443 HOUSTON, TXS 21 1443
TMS2C12 24288-BIT UV RSBL PROGRMMBL TMS2PC12 24288-BIT PROGRMMBL RD-ONLY MMORY device symbolization This data sheet is applicable to all TI TMS2C12 CMOS PROMs and TMS2PC12 CMOS OTP PROMs with the data sheet revision code B as shown below. TI FML TMS2PC12 TMS 2C12 B L X P YY WW B L X P YY WW Data Sheet Revision Code Wafer Fab Code Die Revision Code ssembly Site Code Year of Manufacture Week of Manufacture Data Sheet Revision Code Wafer Fab Code Die Revision Code ssembly Site Code Year of Manufacture Month of Manufacture 12 POST OFFIC BOX 1443 HOUSTON, TXS 21 1443
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