LEAN NPI AT OPTIMUM DESIGN ASSOCIATES: PART 2 WHAT IS LEAN NPI AND HOW TO ACHIEVE IT

Similar documents
User2User The 2007 Mentor Graphics International User Conference

DESIGN FOR MANUFACTURABILITY (DFM)

PCB Fundamentals Quiz

Fertigungsdaten bequem aufbereiten mit Cross Probe zum PCB Editor

PCB Fundamentals Quiz

HOW SMALL PCB DESIGN TEAMS CAN SOLVE HIGH-SPEED DESIGN CHALLENGES WITH DESIGN RULE CHECKING MENTOR GRAPHICS

Design For Manufacture

Integrated stackup design for PCB fabricators and OEM designers

PADS Layout for an Integrated Project. Student Workbook

Allegro New Products - DFM / Rule Checkers

Getting Started in Eagle Professional Schematic Software. Tyler Borysiak Team 9 Manager

PCB layer stackup and controlled impedance design system

Value Stream Map Process Flow

PCB Production Methods

Ruth Kastner Eli Moshe. Embedded Passives, Go for it!

Release Highlights for BluePrint-PCB Product Version 2.0.1

PCB Design (with EAGLE tutorial) TA: Robert Likamwa ELEC 424, Fall 2010

Controlled Impedance Test

The secret behind mechatronics

METRIC PITCH BGA AND MICRO BGA ROUTING SOLUTIONS

VLSI Physical Design Prof. Indranil Sengupta Department of Computer Science and Engineering Indian Institute of Technology, Kharagpur

Digital Systems Design

FPGA World Conference Stockholm 08 September John Steinar Johnsen -Josse- Senior Technical Advisor

PCB layout tutorial MultiSim/Ultiboard

INTEGRATED DESIGN & TEST

Fertigungsdaten aufbereiten mit GerbTool und VisualCAM

New excitement about the process

PCB Layout. Date : 22 Dec 05. Prepare by : HK Sim Prepare by : HK Sim

PCB Layout in the Xpedition Flow. Student Workbook

Instrumentation and Control

Subject Description Form. Industrial Centre Training I for EIE. Upon completion of the subject, students will be able to:

CAD Layout Recommendations for the PowerBlox Family

Why Moving from AutoCAD to AutoCAD MEP Just Makes Sense!

Relationship Between Signal Integrity and EMC

How to anticipate Signal Integrity Issues: Improve my Channel Simulation by using Electromagnetic based model

Damage-free failure/defect analysis in electronics and semiconductor industries using micro-atr FTIR imaging

28nm and below: New Frontiers and Innovations in Design for Manufacturing. Vito Dai, Ph.D. Sr. Member of Technical Staff, DFM

Chapter 16 PCB Layout and Stackup

An Introduction to Automatic Optical Inspection (AOI)

Generic Multilayer Specifications for Rigid PCB s

PCB Design Guidelines for GPS chipset designs. Section 1. Section 2. Section 3. Section 4. Section 5

Project Design for TAPR Manufacturing. Design for Manufacturability

What We Heard Report Inspection Modernization: The Case for Change Consultation from June 1 to July 31, 2012

Moving to Model-Based Design

Practical Limitations of State of the Art Passive Printed Circuit Board Power Delivery Networks for High Performance Compute Systems

Component Based Mechatronics Modelling Methodology

Additive Manufacturing: A New Frontier for Simulation

Plant & Process Electrical Design Introduction to I&W, promis e & BRCM

EECAD s MUST List. Requests for drawing numbers MUST be submitted via the EECAD job request form at

TOLERANCE FORGOTTEN: IMPACTS OF TODAY S COMPONENT PACKAGING AND COPPER ROUTING ON ELECTRONIC

Systems Engineering Process

LTE Small-Cell Base Station Antenna Matched for Maximum Efficiency

Requirements Gathering using Object- Oriented Models

MICROELECTRONICS ASSSEMBLY TECHNOLOGIES. The QFN Platform as a Chip Packaging Foundation

NextGIn( Connec&on'to'the'Next'Level' Application note // DRAFT Fan-out 0,50mm stapitch BGA using VeCS. Joan Tourné NextGIn Technology BV

Introduction to Board Level Simulation and the PCB Design Process

Tutorial In Practical Circuit Board Design Ben LeVesque ECE480 Team 3 November 9 th, 2007

Creating another Printed Circuit Board

Understanding, measuring, and reducing output noise in DC/DC switching regulators

AVEVA PDMS 12.0 The 3D plant design application for accurate and clash-free plant design

SMART PLACES WHAT. WHY. HOW.

Engineering White Paper The Low Mass Solution to 0402 Tombstoning

Gerber Setup. Summary. Access. Options/Controls. General Tab. Modified by on 13-Sep Parent page: WorkspaceManager Dialogs

Passive Microwave Products. Facts - Products - Applications

Process Control & Inspection, Assembly Programming, Reverse Engineering & Design. Products for the Electronics Industry

Assessment of Smart Machines and Manufacturing Competence Centre (SMACC) Scientific Advisory Board Site Visit April 2018.

AltiumLive 2017: Creating Documentation for Successful PCB Manufacturing

Introduction to NI Multisim & Ultiboard Software version 14.1

EXECUTIVE SUMMARY. St. Louis Region Emerging Transportation Technology Strategic Plan. June East-West Gateway Council of Governments ICF

Published on Online Documentation for Altium Products (

TECHNOLOGY ASSESSMENT STRATEGIC PLAN MISSION STATEMENT VISION STATEMENT

The Benefits of Using the Electrical Toolset in AutoCAD

Milling PCBs. Jonathan Bachrach. September 14, EECS UC Berkeley

APPLICATION NOTE 6381 ORGANIC LAND GRID ARRAY (OLGA) AND ITS APPLICATIONS

CUSTOMIZED ASSESSMENT BLUEPRINT ENGINEERING TECHNOLOGIES/TECHNICIANS PA. Test Code: 8091 Version: 01

Revised April High School Graduation Years 2015, 2016, and 2017

Assembly Set. capabilities for assembly, design, and evaluation

WHAT CLICKS? THE MUSEUM DIRECTORY

Anaren 0805 (B0809J50ATI) balun optimized for Texas Instruments CC1100/CC1101 Transceiver

Very Large Scale Integration (VLSI)

Matched Length Matched Delay

THIS DOCUMENT OVERIDES ALL OTHER DOCUMENTATION WITH THE EXCEPTION OF THE READ ME FILE AND DRAWING SUPPLIED WITH THE DATA.

Jacek Stanisław Jóźwiak. Improving the System of Quality Management in the development of the competitive potential of Polish armament companies

PECL DIFFERENTIAL CRYSTAL OSCILLATOR SOLUTIONS FOR TODAY S HIGH SPEED DIGITAL DESIGNER

High-Speed Interconnect Technology for Servers

Wisconsin Technical College System. Curriculum Standards & Program Design Summary CARPENTRY APPRENTICE (ABC)

Course Summary. CLASSROOM: On-site Instructor-led Education WEBINAR: Instructor-led On-line Training ON-DEMAND: Virtual Self-Paced Learning

Horizon 2020 Project: FENIX (No: ) Type of action: RIA. To be supplied to I3DU

Identification and Reduction of Risks in Remote Operations of Offshore Oil and Gas Installations

Project 4.1 Puzzle Design Challenge

Via Stitching. Contents

Concurrent Engineering

Controlled Impedance Line Designer

RF System Design and Analysis Software Enhances RF Architectural Planning

SOON CHIN FHONG IGNATIUS AGUNG WIBOWO PENERBIT UTHM. iii

polarinstruments.com

MISSISSIPPI STATE UNIVERSITY Office of Planning Design and Construction Administration

Soldering Module Packages Having Large Asymmetric Pads

General Design Rules for Conformal Coating

Years 9 and 10 standard elaborations Australian Curriculum: Design and Technologies

Transcription:

W H I T E P A P E R LEAN NPI AT OPTIMUM DESIGN ASSOCIATES: PART 2 WHAT IS LEAN NPI AND HOW TO ACHIEVE IT RANDY HOLT, OPTIMUM DESIGN ASSOCIATES JAMES DOWDING, MENTOR GRAPHICS w w w. o d b - s a. c o m

In the first part of this series, we looked at the business processes employed by Optimum Design Associates (Optimum), a PCB design and assembly service provider. Optimum s PCB design flow and the integration of Mentor Graphics PCB layout and Valor NPI tools were described. Optimum has recognised the importance of embracing new process methodology and improvements to ensure their customers receive an unrivalled level of service. To this end, Optimum s vision is to adopt the Lean New Product Introduction (NPI) business process. The collaboration between Optimum and Mentor Graphics was forged to achieve the ideal combination of Mentor s software technologies and Optimum s business processes. During this second article, Lean NPI will be defined, and Optimum s current business process will be analyzed. This will identify areas where enhancements can be made to align Optimum with the best practice Lean NPI model. In order to measure the success of the transition to Lean NPI, some performance metrics will be specified. These metrics will be referenced in future parts of the series to illustrate the results achieved by Optimum. BEST PRACTICE STANDARD NPI PROCESS MODEL The standard NPI process verifies that the PCB design output data is suitable for the production processes and constraints and, at the same time, provides a streamlined hand-off directly into manufacturing process preparation. Figure 1 shows the standard NPI process for PCB based products. On completion of the PCB design, the manufacturing output is generated using an integrated data format such as ODB++. Additional intelligence and information is applied to the data to form the complete manufacturing-level product model, defining exactly what is to be fabricated and assembled with the minimum need for ancillary documentation such as drawings. Attributes are added to the data which enable a highlevel of DFM to be performed automatically and repeatedly. DFM analysis is executed and feedback is provided about the design so that any DFM related problems can be fixed at source. The next step in the process is to design the assembly panel according to the assembly manufacturer s line-specifications. Figure 1: Standard New Product Introduction process for PCB-based products. The assembly panel design is then DFM verified for both fabrication and assembly. The final manufacturing data can now be generated and handed-off to the fabricators and assemblers, so they can perform their manufacturing process preparation based on the same data. 2

WHAT IS LEAN NPI? There are various levels of DFM that can be executed during the NPI process. Figure 2 illustrates these levels. Level 0 DFM is performed on the factory floor where the product build is attempted and DFM problems are discovered. This method of DFM verification is very time-consuming and expensive with material wastage and production labour costs at a premium. Level 1 DFM is performed by the manufacturer using software tools and is a reasonable method to ensure the design complies with manufacturing rules and process constraints. The downside to Level 1 DFM is that the PCB design organization is heavily reliant on complete and correct DFM feedback from the manufacturer. This feedback is used to make necessary design changes to correct DFM problems but may not include details about the design which could affect product yield or reliability. Level 2 DFM is the ideal scenario, where DFM is executed during the design process using manufacturer derived rules and process constraints. Not only can critical DFM errors be addressed during design, but improvements can be made to increase product yield or reliability, before committing to expensive production runs. The most efficient method of implementing DFM is to adopt concurrent DFM engineering. The PCB layout is designed in stages placement, critical routing, final routing / planes. At each of these key milestone stages, DFM analysis is executed. It can be very difficult and time-consuming to correct DFM problems on completion of the layout. The left-shift of DFM analysis ensures that any DFM problems can be resolved at an early point in the design process. An example of concurrent DFM engineering is shown in Figure 3. 3

Figure 3: Concurrent engineering process, effectively left shifting DFM into the very beginning of the PCB design task. Lean NPI is defined by three enhancement elements within the Best Practice Standard NPI Process Model seen earlier. Firstly, ODB++ data is used as the preferred format for manufacturing hand-off. Product model intelligence is contained within this ODB++ data, thus enabling high levels of automation with minimum keyboard entries. The second element is to execute concurrent DFM at key stages during PCB design development. The final element for Lean NPI is to execute DFM at Level 2. The Lean NPI definition is summarized in Figure 4. Figure 4: Lean NPI defined. BEST PRACTICE LEAN NPI PROCESS MODEL In order that Optimum succeeds in their goal of operating in Lean NPI mode, the Best Practice Lean NPI Process Model will be followed, as illustrated in Figure 5. All actions shown in green are performed using Mentor Graphics Valor NPI and Valor Parts Library (VPL) technologies. The PCB layout is designed in stages and concurrent Level 2 DFM analysis is executed. When the layout is complete and any DFM problems resolved, the assembly panel is designed and validated. Throughout the Lean NPI Process, ODB++ format data is used. The final ODB++ manufacturing output is generated using the standard Valor NPI Output Automation tool and released for manufacturing process preparation. 4

Figure 5: Best Practice model for Lean NPI. MENTOR GRAPHICS TOOLS IN THE LEAN NPI PROCESS As users of Mentor Graphics tools, Optimum is equipped with the complete toolkit required to successfully lay out and hand off PCB designs to manufacture, whilst following the Lean NPI process model. Optimum uses Mentor Graphics Expedition PCB and PADS layout tools with DFM performed using Valor NPI. The integration between Expedition PCB and Valor NPI is fully exercised to provide the feedback of DFM results. Bi-directional graphics cross-probing and the import of DFM Hazards are utilized to the full to efficiently correct DFM problems. Cross-probing from Valor NPI to PADS is also implemented to fix DFM problems. For non-mentor Graphics design flows, Optimum uses the Scorecard and Sharelist features in Valor NPI to deliver reporting functionality and provide the DFM feedback loop. LEAN NPI PROCESS FLOW FOR OPTIMUM DESIGN ASSOCIATES During the collaboration with Mentor Graphics, some areas of Optimum s business process have been identified where improvements can be made to achieve Lean NPI. During the first part of this series we looked at the existing design PCB Layout Process Flow followed by Optimum. By merging this with the Best Practice Lean NPI Process Model seen earlier, the resulting Lean NPI Process Flow for Optimum is shown in Figure 6. Although it may appear complex at first, many of the steps in the flow are automated using the functionality offered by Valor NPI. 5

Figure 6: Lean NPI Best Practice model adapted to fit Optimum Design Associates environment. At the beginning of the design, the BOM is validated using Valor NPI and VPL. This ensures all VPL packages are available. If new VPL packages are required, these can be generated while the component placement is performed. The completed placement is then subject to initial assembly analysis utilizing the VPL packages. If DFM problems exist, they can be fixed before continuing with any complex routing. Prior to each analysis stage, product modelling adds attributes to the ODB++ data which enables comprehensive DFM checks to be executed. Product modelling also adds intelligence and information to the ODB++ manufacturing data which defines exactly what is to be manufactured such as layer stackup, copper weights, solder mask color and component assembly instructions. This removes the need for many drawings and documents which are traditionally used to tell the manufacturer what to deliver. All product modelling activities are automated and repeatable. Any critical routing can then be added to the design. On completion of the critical routing, an initial fabrication analysis is run. This highlights any DFM problems associated with the critical nets which need correcting before continuing with general routing. Clearly, critical routing does not want to be disturbed at a later stage due to DFM problems, as it may be very difficult to make changes whilst retaining the signal integrity. 6

Next, the remainder of the routing, copper areas, power and ground planes and silkscreen legend (if applicable) can be completed. A final DFM analysis is run for fabrication, assembly and test which captures any DFM problems with the completed layout. Figure 7: In actual fabrication, the assembly panel is made four-to-a-set on the fabrication panel, which is then separated into individual boards. Once all DFM problems are investigated and corrected on the single PCB design, the assembly panel design and panel DFM analysis can be performed. This is an optional step offered by Optimum. Figure 7 illustrates the difference between the assembly panel and fabrication panel. The assembly panel is the fabricators deliverable and is used by the PCB assemblers. The assembly panel usually contains an array of single circuit boards. The fabrication panel contains an array of assembly panels and is only used to suit the fabrication processes and make best use of their raw materials. The Valor NPI Output Automation tool is used to generate the necessary outputs for customer design approval. During the approval process, if the customer requires Gerber data as a deliverable, the Valor NPI Cam Compare tool is used to compare the Gerber output against the master ODB++ output to ensure that the Gerber data is graphically identical to the ODB++ data. Thus, the traditional Gerber data can still be used as a valid but less efficient alternative in manufacturing process preparation. On receipt of customer design approval, the Output Automation tool is used again, this time to generate and package the final deliverable manufacturing data. STEPS REMAINING FOR OPTIMUM TO ACHIEVE LEAN NPI During the study of Optimum s PCB Layout Process Flow, some areas were identified where changes could be made to fully implement the Best Practice Lean NPI Process Model described earlier. Making these changes would greatly enhance the already high level of service offered by Optimum. Key areas where Optimum s business process could be modified are as follows: 1. One element of the Lean NPI definition is the use of concurrent DFM engineering during the PCB design process. Optimum s PCB design and NPI process would be enhanced by adding a DFM analysis stage when the critical routing is complete. This would ensure no DFM problems exist with the critical nets. If DFM problems do exist, they can be easily corrected and the signal integrity retained. If DFM problems are discovered with the critical nets at a later stage it may be very difficult and time-consuming to fix the problems without disturbing other routing or even the component placement, whilst retaining the signal integrity. 2. The second recommendation would be to move the customer-approval stage to after the final fabrication and assembly DFM analysis step. This will ensure that the output data used for customer review and approval not only meets the electronic design specifications but is also fully manufacturing compliant. Otherwise, changes may need to be made during the final DFM validation stage which the customer may not be aware of. This change to the process flow will also enable the customer to check and approve the ODB++ manufacturing product model - exactly what is to be manufactured. 7

3. The final recommendation for Optimum is to ensure that only ODB++ output data format is used throughout the flow from design to manufacturing process preparation. This will enable a more efficient data hand-off to both Optimum s external fabrication partners and internal assembly and test lines. HOW TO MEASURE THE SUCCESS OF ADOPTING LEAN NPI As with any significant changes in design methods or business processes, there need to be metrics in place to measure performance improvements and show the effect of those changes on the performance of the business. Discussions with Optimum prior to the Lean NPI transition revealed aspects of the design flow and manufacturing activities which could be monitored to give meaningful statistics. These statistics would prove the effectiveness of adopting Lean NPI. During the PCB layout process, the design is subject to assembly analysis. This highlights problems with placement as well as component footprints. By using Valor NPI and VPL, the integrity of the footprint library is checked. The number of library-related DFM problems per design can be recorded. This number will definitely reduce as Lean NPI is implemented. It is also recommended that the library itself is subject to DFM analysis. This will catch any DFM problems in the library so they can be corrected at source. This will improve assembly times and efficiency as common footprint related problems are corrected. Using ODB++ as the only data transfer format, instead of Gerber and other file types, will make a notable difference to the manufacturing hand-off. The time taken to load, check and prepare the data will be considerably reduced, as will the possibility of error. Using ODB++, the data is loaded directly into manufacturing process preparation tools. As a result, there is a measurable time improvement in going straight from design to manufacturing process preparation. Often there are customer call-backs from the fabrication vendors. These are either related to DFM problems or interpretation of data and design intent. In these situations the job may be put on hold until the question is resolved. If the DFM problems are captured during design and an integrated ODB++ product model is delivered to the fabrication vendor, the number of call-backs will be reduced. These can then be recorded and analysed on a regular basis. Using Valor NPI Scorecard, a DFM report from each design can be made. The list would include, for example, the top ten common DFM problems found within designs. A report for each new design will show a reduction in these top ten DFM problems. This will occur as Optimum s designers start to change the way they think about designing and start applying DFM concurrently during the design flow. For the latest information, visit: w w w. o d b - s a. c o m 2013 ODB++ Solutions Alliance, all rights reserved. MF 7/13 MISC1730-w