Towards Implemening Muli-Channels, Ring-Oscillaor-Based, Vernier Time-o-Digial Converer in FPGAs: Key Design Poins and Consrucion Mehod Ke Cui, Xiangyu Li, Zongkai Liu and Rihong Zhu arxiv:7382v2 [physicsins-de] 9 Jun 27 Absrac For TOF posiron emission omography (TOF PET) deecors, ime-o-digial converers (TDCs) are essenial o resolve he coincidence ime of he phoon pairs Recenly, an efficien TDC srucure called ring-oscillaor-based (RO-based) Vernier TDC using carry chains was repored by our eam The mehod is very promising due o is low lineariy error and low resource cos However, he implemenaion complexiy is raher high especially when moving o muli-channels TDC designs, since his mehod calls for a manual inervenion o he iniial fiing resuls of he compilaion sofware In his paper, we elaborae he key poins oward implemening high performance muli-channels TDCs of his kind while keeping he leas implemenaion complexiy Furhermore, we propose an efficien fine ime inerpolaor consrucion mehod called he period difference recording which only needs a mos 3 adjusmen rials o obain a argeed TDC resoluion To validae he echniques proposed in his paper, we buil a 32-channels TDC on a Sraix III FPGA chip and fully evaluaed is performance Code densiy ess show ha he obained resoluion resuls lie in he range of (23 ps ~ 37 ps), he differenial nonlineariy (DNL) resuls lie in he range of (-4 LSB ~ 4 LSB) and he inegral nonlineariy (INL) resuls lie in he range of (-7 LSB ~ 7 LSB) for each of he 32 TDC channels This paper grealy eases he designing difficuly of he carry chain RO-based TDCs and can significanly propel heir developmen in pracical use Index Terms ime-o-digial converer, field programmable gae array, ring oscillaor, carry chain, Vernier delay line, period difference recording I INTRODUCTION TIME-of-fligh (TOF) PET consiss of very fas deecors which uilize muli-channel ime-o-digial converer (TDC) modules o resolve he coincidence ime of he phoon pairs This helps o improve he omographic reconsrucion qualiy while simulaneously reducing radiaion doses and/or scan imes [] The performance of he overall PET sysem is direcly relaed o he precision of he used TDCs In his paper, we will focus on he designing of highly accurae This work was suppored by he Fundamenal Research Funds for he Cenral Universiies under Grans 39642-9 and 396349 Ke Cui, Zongkai Liu and Rihong Zhu are are wih he MIIT Key Laboraory of Advanced Solid Laser, Nanjing Universiy of Science and Technology, Nanjing, Jiangsu, China, and also wih he Advanced Launching Co-innovaion Cener, Nanjing Universiy of Science and Technology, Nanjing, Jiangsu, China (e-mail: njuscuik@njuseducn) Xiangyu Li is wih he School of Compuer Science and Engineering, Nanjing Universiy of Science and Technology, Nanjing, Jiangsu, China muli-channel TDCs while keeping as leas implemenaion complexiy as possible Mos presen TDC srucures adop a wo-sep ime measuremen echnique [2]-[5] In his mehod, he firs sep uses a coarse couner running a sysem clock rae (usually corresponding o a period of several nanoseconds) o record he elapsed coarse ime o guaranee large dynamic range The second sep adops a fine ime inerpolaor wih subnanosecond resoluion o accuraely record he ime bin locaing in he specific sysem clock cycle a which he coarse ime couner is lached o guaranee high precision The mosly used fine ime inerpolaor echniques include: apped delay line (TDL) [3]-[2], pulse shrinking delay line [3] and Vernier delay line [4]-[6] Generally, here are wo plaforms o implemen TDCs: applicaion specific inegraed circuis (ASICs) and field programmable gae arrays (FPGAs) ASIC-based TDCs have srong design flexibiliy and can uilize some very beneficial analog circuis such as delay locked loops (DLLs) conribuing o an excellen delay line However, heir cos is especially high when he producion volume is low and he developmen period is raher long FPGA-based TDCs have much less design freedom which are consrained in he digial design space However, he reconfigurabiliy of FPGAs makes he design much less expensive and can be adjused o mee new requiremens quickly J Wu proposed he carry chain based srucure as an efficien TDL inerpolaor which is imporan o he developmen of he FPGA-based TDCs [7] The carry chains which widely exis in modern FPGAs are specially provided by heir vendors o fulfill fas algorihm funcions such as fas addiion or comparison The delay ime of a basic carry chain cell is very small such ha i is reasonably conceived as he mos ideal ool o fulfill he fine ime inerpolaion ask on FPGA chips Tha is he reason why he carry chain based TDL TDCs have gained exensive sudies in recen years However, exisence of ulra-wide bin which is physically deermined during chip fabricaion process limis he precision of such TDCs significanly J Wu proposed he wave-union A and B mehods o effecively subdivide he ulra-wide bin by muliple measuremens along a single carry chain and improved he precision beyond is cell delay [6] The wave-union mehods are hen widely adoped by many laer emerging FPGA-based TDC designs [8], [] Anoher drawback of such TDCs is he large differenial nonlineariy (DNL) and inegral nonlineariy
2 sysem coarse cn sysem hi signal clear clock exracion _in hi_in hi_syn crl_ cn coarse couner coarse cn fine ime inerpolaor hi_syn cn clear crl_2 m-2 m- m m+ fine cn coarse cn ime assembler fine cn crl_2 crl_ clear ime samp resul hi crl_ (for coarse cn laching) hi_syn wo clocks laency fine ime fine cn n (he valid fine cn) crl_2 (for fine cn laching) clear hi_syn clear pulse widh pulse widh slow RO fas RO p DUs cascaded carry chain q DUs (c) SET D Q CLK Q CLR pulse widh pulse widh En c o u n en e clr r crl_2 generaor fine ime couner crl_2 Vcc hi_syn () SET D Q dff CLK Q CLR T pos oupu Fig Carry chain RO-based TDC overall srucure; iming diagram; (c) srucure of he RO-based fine ime inerpolaor (INL) problem caused by uneven bin granulariy of he used carry chains One possible echnique o miigae his problem is o use he bin-by-bin calibraion echniques [2] However, his incurs large memory and logic resource cos Recenly, we proposed a new ring-oscillaor-based (RObased) TDC srucure by organizing he carry chains in a Vernier loop syle [7] A specific consrucion mehod o se up wo ROs wih very lile period difference was fully illusraed This mehod opened up a new way o uilize he carry chains o build he fine ime inerpolaor which led o much reduced DNL and INL In his paper, we repor a 32- channels TDC realized on a single FPGA chip by furher exploiing he mehod proposed in [7] One main challenge on he implemenaion complexiy emerges when moving o muli-channels TDC designs, since he effors which should be paid linearly increase wih he channel number This is especially rue because he design flow requires an exhausive manual inervenion o he iniial fiing resuls of he compilaion sofware o obain he wo ROs wih a argeed period difference This paper proposes a new consrucion mehod for building he wo ROs wih definiely less han 3 rials per TDC channel which grealy reduces he design complexiy In summary, he main conribuions of his paper conain: key poins o obain high performance TDC by uilizing he carry chain RO-based mehod; a new and highly efficien consrucion mehod called he period difference recording (PDR) o build he ROs; muli-channel abiliy and scalabiliy by uilizing he carry chain RO-based mehod in a single FPGA chip II MULTI-CHANNEL TDC DESIGN A Carry Chain RO-Based TDC Srucure The basic carry chain RO-based Vernier TDC srucure is depiced in Fig I uses wo seps o measure a ime inerval including a coarse and a fine ime measuremen seps (Fig) The corresponding iming diagram is shown in Fig The coarse couner running a he sysem clock rae is adoped o record he coarse ime The clock exracion module is designed o find he closes clock signal in ime afer he hi signal and exrac he delayed hi and clock signals pair o he fine ime inerpolaor module o measure he fine ime inerval beween hem The working principle and circui implemenaion of he clock exracion module can be found
3 in Secion II-B Two signals labeled crl_ and crl_2 are generaed o denoe he proper iming for he ime assembler module o lach he coarse and fine couner values correcly and combine hem ogeher o produce he final imesamp Fig(c) shows he deailed srucure of he RO-based Vernier fine ime inerpolaer which connecs he las cell of he carry chain back o is firs cell The wo ROs are composed of differen numbers of carry chain cells (or delay unis - DUs) and hold differen oscillaion periods The DU works as basic delay uni and a complee Vernier delay line can conain an even or odd number of DUs The period difference beween he wo ROs deermines he resoluion of he TDC Addiionally, each RO conains a pulse widh module o mainain he sabiliy of he posiive duraion of he oscillaion signal propagaing along i Is circui implemenaion is shown in he righmos par of Fig(c) According o he iming diagram (Fig), he leading signal of a fine ime inerval even (he hi_syn signal in Fig) is fed o he slow RO while he lagging one (he signal in Fig) o he fas RO The fine imesamp is obained by reading ou he fine ime couner which records he oscillaion number a he momen ha he lagging signal caches up he leading signal Obviously, he DNL of such TDCs avoids he bad influence of he uneven bin granulariy, since he resoluion is deermined by he physical lengh difference of he wo ROs bu no he bin widhs of he used carry chains as in he TDL form Much reduced DNL has been observed in [7] However, since he ROs are no compensaed and sabilized during he ime measuremen, he oscillaion number canno be se oo large o assure small precision RMS which means ha radeoff beween he resoluion and he precision should be carefully considered and made by he designers B Key Design Poins There are wo key poins for he designers o build he RObased Vernier TDC: he clock exracion module and he fine ime inerpolaor module ) key design poin for he clock exracion module: The basic ask for he clock exracion module is o locae he clock signal which is neares in ime afer he hi signal and hen exrac i ou The oupued leading and lagging signals are ermed as hi_syn and correspondingly and he fine ime inerval beween hem will be measured by he following fine ime inerpolaor module The circui implemenaion of he clock exracion module is depiced in Fig2 I can be seen ha an undesired addiional delay τ d = τ reg + τ 2 τ is added o he original fine ime inerval and causes a minimal oscillaion number n = τ d LSB, where τ reg represens he delay inroduced by he sampling D-ype flipflops, τ and τ 2 represens he adjusable delay inroduced by he delay compensaion unis for he hi_in and _in signals respecively, and LSB represens he resoluion of he TDC The exisence of n deerioraes he TDC performance, since he precision RMS increases abou proporionally o he square roo of he overall oscillaion number [8] The iming diagram in Fig2 shows ha he following formula should be saisfied o guaranee he requiremen ha he renewed arrival ime of hi_in _in hi_in _in hi_syn D SET CLK CLR 2 Q Q T d T pos 2 2 reg 2 D T pos T SET CLK CLR Q Q reg delay compensaion uni hi_syn 2 ( T pos T crl_ 2 ( T pos T 2 Fig 2 Circui implemenaion and iming diagram of he clock exracion module Here and 2 are he arrival ime of he hi_in and _in signals respecively, while and 2 are he corresponding oupu ime afer passing he clock exracion module hi_syn hi_syn 2 2 d Tpos d (c) T hi_syn T 2 d T d T d T Tpos Fig 3 Relaive phase relaionship beween he hi_syn and signals he signal should no exceed he posiive duraion of he hi_syn signal for correc operaing of he sampling D-ype flip-flop in he fine ime inerpolaor: (e) (d) τ d (T pos T ) () where T pos represens he posiive duraion of he hi_syn signal and T represens he period of he sysem clock The compensaion delays τ and τ 2 are inenionally added o ry o make τ d as small as possible leading o he leas n o gain he bes precision performance The compensaion uni is composed of 32 cascaded look-up able (LUT) implemened NOT gaes According o our experimenal experience, his gae amoun is adequae o find a good enough parameer se (τ, τ 2 ) The acually used gaes number for each signal is manually adjused and deermined by using he resource edior ool provided by he FPGA manufacurers (for example he engineering change orders - ECO ool by Alera and he FPGA edior ool by Xilinx) The adjusmen crieria is o make τ d locaing in he range consrained by equaion () and as close o zero as possible However, his ask is difficul o ) )
4 be fulfilled direcly since all he iming parameers τ, τ 2, τ reg and T pos are very hard o be known exacly To comba he difficuly, we propose o infer he acual τ d value by observing he disribuion of he oupued fine ime couner values n capured from he fine ime inerpolaor module The cases of he relaive phase beween he hi_syn and signals are depiced in Fig3 and he corresponding disribuions of n are summarized in Table I, where he parameer n m represens he maximal fine ime couner value TABLE I DISTRIBUTIONS OF THE FINE TIME COUNTER VALUES n CORRESPONDING TO DIFFERENT CASES IN FIG3 case number (c) (d) (e) descripion all he occurring ime poins of he are lae o he posiive duraion of he hi_syn all he occurring ime poins of he are prior o he posiive duraion of he hi_syn par of he occurring ime poins of he are lae o he posiive duraion of he hi_syn par of he occurring ime poins of he are prior o he posiive duraion of he hi_syn all he relaive phase relaions are in he expec range saisfying equaion () disribuion of n {} {} {} {(n, n m)} {(, n m)} {(n, n m)} According o he cases lised in Table I, he following seps are applied o efficienly find an opimal se (τ, τ 2 ) for each TDC channel: ) According o he colleced disribuions of n, classify which case he presen parameer se (τ, τ 2 ) belongs o If i accords wih case (c), goo sep 2; if i accords wih case (d), goo sep 3; if i accords wih case (e), goo sep 4; oherwise modify he number of cascaded NOT gaes in eiher of he wo delay compensaion uni unil one of he cases (c)~(e) appears 2) Ieraively shoren he gaes number of he delay compensaion uni in he signal pah unil case (e) appears and hen goo sep 4 3) Ieraively shoren he gaes number of he delay compensaion uni in he hi_syn signal pah unil case (e) appears and hen goo sep 4 4) Decrease n by ineraively shorening he gaes number of he delay compensaion uni in he signal pah unil he minimal achievable posiive n is found The shorened gaes number in seps 2 ~ 3 is usually se larger han o boos he finding process while he number in sep 4 is se jus as o search he opimal n The above menioned manual adjusmen for he clock exracion module is very useful, since as he argeed TDC channels number increases, he iniial fiing resuls have more risk o lay ou of case (e) and lead o operaion failure Even he auomaic fiing resuls iniially accords wih case (e), i is sill very beneficial o apply sep 4 o find he opimal n 2) key design poin for he fine ime inerpolaor module: The fine ime inerpolaor module conains wo srucuresymmeric ROs buil from he carry chains The srucural similariy is obained by uilizing he pariion based wosep consrucion mehod proposed in [7] The complee oscillaion period of he RO is composed of hree pars: τ p caused by he carry chain (he pah encompassed by he doed recangle), τ p2 caused by he connecion pah beween he end of he carry chain and he pulse module (he bold line), and τ p3 caused by all he remaining logic unis and pahs in he RO as shown in Fig4 I is clear ha τ p3 keeps consan once he RO is se up In our previous work, τ p2 is also assumed o be unchanged afer manual inervenion a he fine uning poin, so an ieraive adjusmen process of assigning differen DU number combinaion ses o aler τ p for he wo ROs is adoped The adjusmen ask is performed as follows: cu off he connecion a he fine uning poin whose oscillaion period is longer; shoren he lengh of he carry chain by one DU; finally reconnec he new shorer carry chain o he corresponding pulse widh module The oscillaion periods are observed on an exernal oscilloscope by inroducing he oscillaion signals ou of he FPGA chip This adjusmen principle resrics ha he DU number combinaion se assigning direcion can only be conduced forward o he fron end of he carry chain, which may incur he missing of many poenial DU number combinaion ses, since τ p2 becomes acually uncerain afer each ime of adjusmen This arises from he possibiliy ha when a RO needs o reduce is oscillaion period, he DU number may acually require adding insead of subracing, if τ p2 decreases so dramaically ha he enire oscillaion period decreases even wih he larger DU number In our example design, he overall lengh of a complee carry chain is 32 and his heoreically gives 32 32 = 24 possible DU number combinaion ses if boh τ p and τ p2 are viewed changeable The release of he adjusmen consrain generaes huge DU number combinaion se space and gives flexible design freedom This poin is also imporan in muli-channels TDC designs since he more DU number combinaion candidaes can be used, he less design failure may be encounered when using such a shor carry chain (oally 32 DUs) If a design failure happens for a TDC channel, he designer has o re-allocae a new physic region on he FPGA chip and re-consruc his bad channel which will grealy increase he design complexiy Alhough exending he lengh of he used carry chain is also feasible o improve he design success rae, i will cause much larger resource cos which is especially rue in muli-channels TDC designs C Period difference recording mehod for fine ime inerpolaor consrucion In his secion we propose he PDR mehod, by using which every possible DU number combinaion se can be covered wih very few oal adjusmen rials To clarify he PDR mehod, we define he oscillaion period of he fas RO as τ f, i (i = 32, 3,, ), when he i-h DU number of he fas RO is conneced o he fine uning poin Similarly we define he oscillaion period of he slow RO as τ s, j (j = 32, 3,, ), when he j-h DU number of he slow RO is conneced o he fine uning poin Addiionally we
5 slow RO hi_syn clear pulse widh pulse widh p DUs p q n q DUs p q n pulse widh delay pah p fine uning poin delay pah p2 delay pah p 3 fas RO pulse widh oupu oupu oscilloscope CH CH 2 Fig 4 Delay pahs along he RO define he oscillaion period difference beween he fas and slow ROs as τ i, j = τ s, j τ f, i corresponding o he DU number combinaion se (i, j) By using he above definiions, we illusrae he PDR design flow as follows: ) Tes and record he resul of τ 32, 32, and goo sep 2 2) Fix i = 32, enumerae j = 3, 3,,, es and record he resuls of τ 32, j, and goo sep 3 3) Fix j = 32, and iniialize i = 3 if his is he firs ime enering his sep Tes and record he resul of τ i, 32, goo sep 4 4) For he curren argeed DU number combinaion se (i, j) (j = 3, 3,, ), compue τ i, j = τ 32, j + τ i, 32 τ 32, 32 If any τ i, j lying in he argeed resoluion range exiss, oupu he combinaion se (i, j) and sop he ieraion wih success, oherwise make i = i and goo sep 3 If no saisfying τ i, j can be found even wih i =, sop he ieraion wih failure The PDR mehod only needs o record a mos 63 resuls bu can cover as much as 24 differen DU number combinaion ses, which grealy reduces he design complexiy I originaes from he following idenical equaion: τ i, j = τ s, j τ f, i = τ s, j τ f, 32 + τ s, 32 τ f, i + τ f, 32 τ s, 32 = τ 32, j + τ i, 32 τ 32, 32 (2) In pracical use, he period difference beween he wo ROs is obained by observing an exernal oscilloscope o collec he oscillaion number k, he iniial period difference τ ini and he final period difference τ fnl for an arbiary DU number combinaion se (i, j) (i, j = 32, 3,, ), and hen he period difference is calculaed as τ i, j = τ fnl τ ini k For example, Fig5 shows a real waveform capured during our design process by a 25 Gs/s Tekronix oscilloscope (series number: DPO 332), of which he channel represens he slow RO while he channel 2 represens he fas RO I can be seen ha Fig5 shows he enire oscillaions waveform giving k = 25, Fig5 shows he locally enlarged waveform of he firs wo oscillaions giving τ ini 3 ps, and Fig5(c) shows he locally enlarged waveform of he las wo oscillaions giving τ fnl ps, so τ i,j can be ps 3 ps esimaed as 25 = 28 ps Fig5 also shows ha he realized ROs have an approximaely 2 MHz frequency (corresponding o an abou 5 ns period) ini 3 ps k 25 fnl ps Fig 5 Oscillaion waveforms for he DU number combinaion se (i, j) According o our design experience, 6 6 design space generaing 256 possible DU number combinaion ses is large enough o consruc our 32-channels TDC No failure happens during he whole design process As an example, we summarize he recorded period difference values wih he 6 6 design space for he TDC channel No in Table II Since a arge resoluion range of 25 ~ 35 ps is chosen in our design, by exploiing Table II, we can easily conclude he saisfying DU number combinaion ses by applying equaion (2) For example, he combinaion se (i, j)=(25, 3) gives τ 25, 3 = 68 + 62 ( 33) = 27 ps which demonsraes iself a valid DU combinaion candidae I should be noiced ha he PDR mehod jus provides an esimaion of he resoluion whose accurae value should be obained from he code densiy ess as performed in Secion III III TEST RESULTS This paper buil a 32-channels TDC prooype on a single EP3SEF52I3 Sraix III device from Alera using a self-
6 TABLE II RECORDED PERIOD DIFFERENCE VALUES FOR THE TDC CHANNEL NO IN OUR DESIGN i (fixing j = 32) τ i,32 (ps) j (fixing i = 32) τ 32,j (ps) 32-33 32-33 3-75 3-3 3-63 3-68 29-96 29-256 28 7 28-23 27 45 27-37 26 88 26-344 25 62 25-383 24 3 24-333 23 45 23-4 22 3 22-286 2 25 2-433 2 9 2-4 9 45 9-46 8 35 8-362 7 9 7-4 TDC oupu resul (ps) TDC oupu resul (ps) 6 55 5 45 4 35 3 25 2 5 y 3 x 2252 5 5 2 25 3 35 35, 32, 28, 24, 2, 6, 2, 8, Time inerval (ps) y 5 x 2244 4, designed es board The coarse couner is se as 9 bis widh running a 6 MHz clock rae (corresponding o 667 ps period) The fine ime couner is se as 7 bis widh There are oally 6 bis o represen a imesamp Resource repor afer compilaion shows he LUT occupaion percenage is 39/852 (4%) and he regiser occupaion percenage is 4/852 (2%) per TDC channel So only abou 3% LUTs and 7% regisers of he FPGA chip are cos for he 32-channels TDC design 4, 8, 2, 6, 2, 24, 28, 3, Time inerval (ps) Fig 7 Transfer curves using a sep size of ps and a dynamic range of 35 ns; using a sep size of 5 ps and a dynamic range of 3 ns were applied o es he performance of he DNL and INL Furhermore, precision RMS es was also performed via wo TDC channels by feeding wo hi signals having a fixed delay value To reduce any possible saisical error of couning, he es sample size was se o be one million All he menioned ess were conduced using nominal supply volages and a an ambien emperaure of around 2 C Fig 6 The DNL and INL of he TDC channel No During ess, all recorded imesamps were ransferred o PC via he USB 2 bus for furher analysis Code densiy ess A Specific performance characerizaion of TDC channel No To apply he code densiy es, an arbirary funcion generaor AFG325 was used o generaed pulsed signals wih repeiion frequency of 5 khz The generaor ran under an uncorrelaed clock wih he TDC o guaranee he correcness of he code densiy ess The pulsed signals were inroduced ino he FPGA chip acing as hi signals The esed fine imesamps for TDC channel No lie in range of (9 ~ 64), 667 ps 64 9 so he LSB = = 33 ps The obained diagrams of he DNL lying in he range of (-5 LSB ~ 82 LSB) and he INL lying in he range of (-2 LSB ~ 28 LSB) are depiced in Fig6 To es large ime inerval resuls and evaluae he precision RMS, TDC channel No2 was included The AFG325 was used o generae wo correlaed hi signals wih a programmed delay value ranging in ( ps ~ 3 ps) The wo hi signals were fed o TDC channels No and No2 respecively by using wo co-axial cable wih equal lengh The TDC oupu resuls were obained by subracing he ime resuls of channel No from hose of channel No2 Before es, a 74Zi Lecroy digial oscilloscope working a he Random Inerleaved Sampling Mode (RIS) providing 2 Gs/s equivalen sampling rae was used o deermine he signal jier inroduced by he AFG325 which urned ou o be less han 8 ps Tha value has small
7 Coun 2, 8, 6, 4, 2,, 8, 6, 4, 2, Mean: 32737 ps Precision: 34 ps RMS 32,4 32,5 32,6 32,7 32,8 32,9 33, 33, Time inerval (ps) Fig 8 Hisogram of he ime inerval resuls beween he TDC channels No2 and No AFG325 inpu TDC channel No delay module No TDC channel No2 delay module No2 FPGA-EP3SEF52I3 Fig 9 Tes configuraion for he proposed 32-channels TDC TDC channel No32 delay module No32 influence o our final resuls The ransfer curves of he TDC are depiced in Fig7 of which Fig7 uses a sep size of 5 ps and a dynamic range of 3 ns while Fig7 uses a sep size of ps and a dynamic range of 35 ns The fied linear curve has a slope very close o which demonsraes ha he TDC has very good lineariy performance The offse in he figure is mainly caused by he delay pah difference of he wo TDC channels from he IO elemen o he TDC module on he FPGA chip During he ransfer curve es process, he precision RMS values a each ime inerval poin are calculaed simulaneously which urn ou o lie in he range of (32 ps ~ 4 ps) As an example, he hisograms of he ime inerval resuls wih values of 2324 ps and 32737 ps are depiced in Fig8 B Performance summarizaion of all he 32 TDC channels In his secion, a specific es configuraion depiced in Fig9 was applied o help simplify he es process The AFG325 is used o generae hi signals wih repeiion frequency of 5 khz We se a delay module independenly for each of he 32 TDC channels which is composed of cascaded NOT gaes wih even number (he gaes number is randomly se in he range of 4 ~ ) This configuraion is very useful o evaluae he precision RMS under large ime inerval ess such as 4 ~ 2 ns By analyzing he disribuion of he ime imesamps for each of he 32 TDC channels, all imporan performance parameers including fine ime couner range, resoluion, equivalen bin widh, DNL, INL and precision RMS can be obained The deailed parameers resuls are lised in Table III In his 667 ps able, he resoluion is calculaed as LSB = n m n The erm equivalen bin widh w eq can ake effecs of he various bin widhs ino accoun [9] I is calculaed as w eq = i ( w3 i W ) wih W = i w i, where w i represens he bin widh for he i-h bin number All he w i values are obained by he code densiy ess From Table III, we conclude ha he obained resoluions and equivalen bin widhs all lie in he range of (232 ps ~ 372 ps), and he fac ha hey are very close o each oher reflecs ha he TDC has good lineariy performance [] The obained DNL resuls generally lie in he range of (-4 LSB ~ 4 LSB) wih a maximal ampliude of 59 LSB (channel number 6) and he obained INL resuls generally lie in he range of (-7 LSB ~ 7 LSB) wih a maximal ampliude of 87 LSB (channel number 6) The obained lineariy is no as good as ha repored in [7] One reason is ha he physical locaion of a TDC channel on he FPGA chip is found o influence he lineariy error significanly However, we did no opimize he physical locaions in his design since i would be considerably ime consuming and no necessarily required in mos applicaion cases All he implemenaion regions were auomaically generaed by he compilaion sofware If he designers wan o obain TDC channels wih very small lineariy error, manually assigning he implemenaion regions and comparing heir performance are recommended Anoher reason is ha muli-channels may influence each oher during operaion and deeriorae he lineariy error Manually and properly assign he implemenaion regions may help improve he lineariy performance Even so he lineariy performance is sill relaively beer han ha in he TDL based mehod uilizing carry chains which usually owns a maximal ampliude of 2 ~ 4 LSBs Large ime inerval resuls are obained by subracing he ime resuls calculaed from TDC channel No from hose of he TDC channels No2 ~ 32 respecively The precision RMS is calculaed from he corresponding ime inerval resuls for each of he TDC channels From Table III, i can be seen ha all of he precision RMS resuls lie in he range of (32 ps ~ 39 ps) Finally, he dead ime of he realized TDC channels is mainly deermined by he oscillaion period of he Vernier delay line and he maximal oscillaion numbers The oscillaion
8 channel number (n, n m) LSB (ps) equivalen bin widh (ps) TABLE III TESTED PERFORMANCE OF EACH OF THE 32-CHANNELS TDC DNL (% LSB) INL (% LSB) mean delay value (ps) relaive o channel No precision RMS (ps) relaive o channel No (9, 64) 33 35-5~8-2~28 N/A N/A 2 (3, 6) 355 357-7~9-3~5 582 34 3 (2, 76) 26 263-22~24-38~4 5689 38 4 (2, 64) 32 323 -~ -26~28 689 36 5 (8, 64) 297 3-5~2-72~5 723 34 6 (9, 6) 327 33-32~27-5~36 7983 35 7 (9, 58) 34 34-8~8-2~47 642 33 8 (8, 59) 327 329 -~3-28~3 882 32 9 (8, 68) 278 3-9~9-55~6 836 38 (6, 68) 269 272-22~6-28~33 9247 36 (6, 57) 327 329 -~ -48~ 9835 32 2 (, 59) 34 342-3~5-58~7 25 34 3 (2, 65) 35 36-9~9-5~22 678 36 4 (5, 73) 287 29-9~22-52~2 2872 39 5 (, 6) 333 336-8~22-46~2 4883 33 6 (4, 58) 39 32-33~6-7~65 5824 33 7 (5, 56) 327 329-3~ -62~2 3764 36 8 (4, 59) 33 35-8~2 -~69 2748 37 9 (9, 58) 34 343-2~4-3~5 4782 33 2 (, 6) 34 343-5~6-68~4 5824 34 2 (8, 76) 245 247-2~23-59~25 6732 35 22 (7, 52) 37 372-2~36-2~4 532 35 23 (8, 8) 232 233-3~8-2~38 6329 37 24 (6, 7) 26 262-3~2-7~33 5897 38 25 (8, 57) 34 342-2~6-5~ 723 35 26 (, 58) 347 349-32~2-44~24 7467 33 27 (8, 58) 333 334-2~3-22~8 8237 32 28 (, 66) 298 299-9~2-4~38 5983 36 29 (9, 6) 32 323-4~5-54~3 8476 37 3 (5, 58) 35 37-2~7-8~36 9238 38 3 (, 75) 26 262-3~2-26~33 9782 36 32 (7, 55) 347 348-3~7-2~7 8472 32 N/A=no applicable period (from Fig5) is abou 5 ns and he maximal oscillaion number is 8 (from Table III, channel No23) leading o he dead ime of 5 8 = 4 ns IV DISCUSSION Carry chains are usually organized in TDL syle which is he mainsream realizaion mehod for FPGA-based TDCs This mehod provides low implemenaion complexiy since he carry chain based TDL can be auomaically synhesized by sofware compiler wihou any manual inervenion However, a plain TDC consruced by he TDL mehod usually suffers from large DNL and INL Forunaely, by applying some well developed opimizaion echniques, such as he wave union [6] or muli-chains averaging echnique [] o improve he equivalen resoluion and he bin-by-bin calibraion echnique [2] o improve he INL, his TDC mehod is very promising for pracical use This paper emphasizes he Vernier mehod by organizing he carry chains in RO syle This mehod has demonsraed iself very compeiive in erms of resource cos, DNL and INL when compared wih he TDL mehod for a plain TDC design The shorcomings are ha he realized resoluion is no as high as ha in he TDL mehod so far, he dead ime is relaively longer, and manual inervenion o adjus he RO period difference is needed during design process However, similar opimizaion echniques such as he mulichains averaging and bin-by-bin calibraion can also be applied o his kind of TDC o furher improve is performance Mos imporanly, applying he muli-chains averaging echnique is very valuable o suppress he large precision RMS and furher explois he resoluion capabiliy of such TDCs down o ps level Some performance comparisons beween his work and some oher recen FPGA-based works are summarized in Table IV V CONCLUSIONS Our recenly proposed RO-based TDCs by organizing he carry chains in he Vernier loop syle are a promising opion for he TDC designers mainly due o is remarkably low lineariy error and low resource cos However, implemenaion complexiy problem is posed since his design calls for manual inervenion o he iniial fiing resuls when moving o muli-channels TDC designs To comba ha problem, his paper elaboraes he key poins o consruc muli-channels TDCs o achieve high performance while keeping he leas design complexiy: one for he clock exracion module and one for he fine ime inerpolaor module Furhermore he PDR mehod is proposed o search he poenial DU number combinaion ses for a argeed resoluion which coss a mos 3 rials in our example design The PDR mehod grealy
9 TABLE IV PERFORMANCE COMPARISONS BETWEEN THIS WORK AND SOME OTHER RECENT FPGA-BASED WORKS ref chip mehod resoluion (ps) precision RMS (ps) DNL (LSB) INL (LSB) dead ime (ns) cosed regisers [4] Virex-5 TDL 3 5 - ~ 3-4 ~ 4 3 57 64 [5] UlraScale TDL 45 39 N/S N/S 4 N/S N/S [9] Virex-6 TDL 28 - ~ 9-22 ~ 393 N/S N/S N/S [] Cyclone II TDL 28 288 N/S N/S N/S 23494 2885 [2] Virex-6 TDL 96 - ~ 5-225 ~ 6 33 N/S N/S [3] Sparan-3 pulse shrinking 42 56-98 ~ 6-47 ~ 36 7 N/S N/S his work Sraix III Vernier 23 ~ 37 32 ~ 39-4 ~ 4-7 ~ 7 4 39 4 N/S=no specified cosed LUTs reduces he implemenaion complexiy during he fine ime inerpolaor consrucion process This paper buil a 32-channels TDC on a Alera Sraix III FPGA and demonsraes good performance This paper grealy eases he designing difficuly of he carry chain RO-based TDCs and can significanly propel heir developmen in pracical use REFERENCES [] J K Dan, M E Casey, M Coni, B W Jakoby, C Lois, and D W Townsend, Impac of ime-of-fligh on PET umor deecion, Journal of Nuclear Medicine, vol 5, no 8, pp 35 323, 29 [2] J Wu, Several key issues on implemening delay line based TDCs using FPGAs, IEEE Transacions on Nuclear Science, vol 57, no 3, pp 543 548, June 2 [3] J Song, Q An, and S Liu, A high-resoluion ime-o-digial converer implemened in field-programmable-gae-arrays, IEEE Transacions on Nuclear Science, vol 53, no, pp 236 24, Feb 26 [4] L Zhao, X Hu, S Liu, J Wang, Q Shen, H Fan, and Q An, The design of a 6-channel 5 ps TDC implemened in a 65 nm FPGA, IEEE Transacions on Nuclear Science, vol 6, no 5, pp 3532 3536, Oc 23 [5] Y Wang and C Liu, A 39 ps ime-inerval RMS precision ime-odigial converer using a dual-sampling mehod in an UlraScale FPGA, IEEE Transacions on Nuclear Science, vol 63, no 5, pp 267 262, Oc 26 [6] J Wu and Z Shi, The -ps wave union TDC: improving FPGA TDC resoluion beyond is cell delay, in 28 IEEE Nuclear Science Symposium Conference Record, Oc 28, pp 344 3446 [7] J Wu, Z Shi, and I Y Wang, Firmware-only implemenaion of imeo-digial converer (TDC) in field-programmable gae array (FPGA), in 23 IEEE Nuclear Science Symposium Conference Record, Oc 23, pp 77 8 [8] J Wang, S Liu, L Zhao, X Hu, and Q An, The -ps muliime measuremens averaging TDC implemened in an FPGA, IEEE Transacions on Nuclear Science, vol 58, no 4, pp 2 28, Aug 2 [9] J Y Won, S I Kwon, H S Yoon, G B Ko, J W Son, and J S Lee, Dual-phase apped-delay-line ime-o-digial converer wih onhe-fly calibraion implemened in 4 nm FPGA, IEEE Transacions on Biomedical Circuis and Sysems, vol, no, pp 23 242, Feb 26 [] Q Shen, S Liu, B Qi, Q An, S Liao, P Shang, C Peng, and W Liu, A 7 ps equivalen bin size and 42 ps RMS FPGA TDC based on mulichain measuremens averaging mehod, IEEE Transacions on Nuclear Science, vol 62, no 3, pp 947 954, June 25 [] W Pan, G Gong, and J Li, A 2-ps ime-o-digial converer (TDC) implemened in field-programmable gae array (FPGA) wih auomaic emperaure correcion, IEEE Transacions on Nuclear Science, vol 6, no 3, pp 468 473, June 24 [2] M Fishburn, L H Menninga, C Favi, and E Charbon, A 96 ps, FPGA-based TDC wih muliple channels for open source applicaions, IEEE Transacions on Nuclear Science, vol 6, no 3, pp 223 228, June 23 [3] R Szple and K Klepacki, An FPGA-inegraed ime-o-digial converer based on wo-sage pulse shrinking, IEEE Transacions on Insrumenaion and Measuremen, vol 59, no 6, pp 663 67, June 2 [4] J Kalisz, R Szple, J Pasierbinski, and A Poniecki, Fieldprogrammable-gae-array-based ime-o-digial converer wih 2-ps resoluion, IEEE Transacions on Insrumenaion and Measuremen, vol 46, no, pp 5 55, Feb 997 [5] B Markovic, S Tisa, F A Villa, A Tosi, and F Zappa, A highlineariy, 7 ps precision ime-o-digial converer based on a single-sage Vernier delay loop fine inerpolaion, IEEE Transacions on Circuis and Sysems I: Regular Papers, vol 6, no 3, pp 557 569, March 23 [6] J Yu, F F Dai, and R C Jaeger, A 2-bi Vernier ring ime-o-digial converer in 3 um CMOS echnology, IEEE Journal of Solid-Sae Circuis, vol 45, no 4, pp 83 842, April 2 [7] K Cui, Z Ren, X Li, Z Liu, and R Zhu, A high-lineariy, ringoscillaor-based, Vernier ime-o-digial converer uilizing carry chains in FPGAs, IEEE Transacions on Nuclear Science, vol 64, no, pp 697 74, Jan 27 [8] A A Abidi, Phase noise and jier in CMOS ring oscillaors, IEEE Journal of Solid-Sae Circuis, vol 4, no 8, pp 83 86, Aug 26 [9] J Wu, Uneven bin widh digiizaion and a iming calibraion mehod using cascaded PLL, in 24 9h IEEE-NPSS Real Time Conference, May 24, pp 4