Fitting Optical Interconnects to an Electrical World- Packaging and Reliability Issues of Arrayed Optoelectronic Modules Keith Goossen, University of Delaware 1
OUTLINE 1. Technology a. Physical rack limitations on optical interconnects dictating a bent package. b. Optical packaging difficulties encountered going to 2-dimensional optics. c. Reliability limitations on the data rate of VCSEL s and possible alleviation via either revolutionary thermal device packaging or modulators. 2. Market path 2
Early experiments: The Bell Labs photonic switch; systems with no electrical data lines going into the photonic chip, only optical in/out Construction of large system by interconnecting of small electrical systems through fiber optics via photonic chip buffered electronic switches memoryless crossbar switch (crossconnect that reconfigures at the packet rate)- optical data in, optical data out; control for setting switch inputted electrically buffered electronic switches 3
Early experiments: Made without concern of physical constraints in the third dimension, ignoring rack-based system packaging 4
Conforming to existing rack packaging requires the light to come out parallel to the board optical bend electrical bend 5
Actually, the later Bell Labs experiments did recognize the need for rack packaging, but with ~ 4 inch clearance requirements (for 4352 channels!) Used flexible circuit board to effect ninety degree turn of control information inputted electrically to switching chip 6
Conforming to rack architecture requires using modules, which become harder to make as channel count increases 1xN E/O module mxn E/O module VCSEL chip driver chip Optical fiber bundle electrical interface to customer board 7
Size of parallel optic modules is actually determined by electrical and thermal considerations! Since optical pitch is 0.25 mm, but electrical pin or ball pitch to customer board is ~ a millimeter (note: two per signal), electrical footprint increases far faster then optical footprint (~ 16x). Heat sink requirements increase footprint even faster (~ 200x). Modules larger than ~ 50-100 channels will require water cooling. 8
1x12 vs. 2D array packaging: traditional mating pin technique inhibited by chip VCSEL chip driver chip optical fiber array wire bonded module mating pins flip-chip bonded module no board access for mating pins 9
2D array packaging: Various approaches for optical packaging 10
2D array packaging: Can the mating pins protrude through holes in the chip? 11
2D array packaging via protruding mating pinsdie placement + fiber-pin accuracy must be less than ~ 10 microns for multimode Experiment with single mode ribbon mating indicates that injection molded plastic ferrules have < +/- 5 micron accuracy. Must have micron die placement accuracy for protruding mating pin 2D array packaging. 7 MTP jumpers fabricated using 6 single mode fiber. Indicates 5 < +/- 4 µm fiber center accuracy. excess loss (db) 4 3 2 1 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 channel number 12
VCSEL reliability: the data (Honeywell) can be modeled effectively 1E7 d=17 µm T 1% failure (hours) 1000000 100000 10000 d=5 µm d=14 µm d=17 µm d=5 µm d=14 µm d=17 µm d=5 µm d=14 µm 1000 100 20 40 60 80 100 120 1400 5 10 15 20 case temperature (C.) current (ma) 0 5000 10000 15000 20000 current density (ka/cm 2 ) 13
VCSEL reliability: the data can be modeled effectively MFT = j c A j 2 e T T + ZIV EA 1 1 ( )( ) k T 373 j For latest Honeywell data, A=1200 E E 1 A A A ( ) ( )( ) E E E A A A ( ) ( ) ( ZIV ) 2 373k k Tc+ ZIV 373k ktc ktc 2 2 A MFT e e e e e j j 65A = e j 2 ZIV ( ) 12 14
VCSEL reliability: modeling indicates trouble at high data rates 1E7 f res =C f (j-j th ) 1/2, C f =37 GHzµm/mA 1/2 (10 GHz~0.1 ma/µm 2 ) T case =40 C. 1000000 T 1% failure (hours) 100000 10000 1000 10 years d=5 µm d=14 µm d=17 µm 100 0 2 4 6 8 10 12 14 16 18 20 resonant frequency (GHz) 15
VCSEL reliability for 10000 count arraylooks fine at low data rates 1E7 1000000 f res =C f (j-j th ) 1/2, C f =37 GHzµm/mA 1/2 T case =40 C. T 0.01% failure (hours) 100000 10000 1000 10 years d=5 µm d=14 µm d=17 µm 100 0 2 4 6 8 10 12 14 16 18 20 resonant frequency (GHz) 16
VCSEL reliability can be high if thermal impedance is reduced to zero 1E7 Median Failure Time (hours) 1000000 100000 10000 1000 100 10 1 10 years decrease current threshold to 0 decrease thermal impedance to 0 40 Gbit/sec VCSEL existing technology 0.1 0.01 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 case temperature (C.) 17
Lower thermal impedance can be achieved if flip-chip bump is used to convey heat 18
Even direct bonding results in high thermal impedance, due to Bragg mirror, which can be reduced by adding gold layer 19
Using this technique, we have achieved about 500 C./W thermal impedance 3.0 2.5 2.0 Z~500 C./W d=15 µm V (volts) 67.2 Ω 1.5 1.0 0.5 I th =1.68 ma L (mw) 0.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 current (ma) 20
However, bonding directly to the mesa, while lowering junction temperature, causes ~ 96 times faster failure at a given junction temperature and current (A=12.5) current required for 1 mw light output (ma) 9.0 8.5 8.0 7.5 7.0 6.5 6.0 5.5 5.0 4.5 set of 12 VCSELs flip-chip bonded to mesa Median Failure Time=2700 hours junction temperature=110 C. 4.0 0 200 400 600 800 100012001400160018002000220024002600280030003200 operation time at 5.8 ma, 95 C. case temperature (hrs) 21
The VCSEL thermal quandary Making the VCSEL run cooler requires intimate placement of heat sinking bonds to the active region, but that increases failure rate at a given temperature! 22
Thermal impedance requirements for 40 Gbit/sec 1000000 Median Failure Time (hours) 100000 10000 1000 100 10 1 0.1 0.01 1E-3 die-bond requires failure physics understanding flip-chip our flip -chip data, in house VCSEL (only Z demonstrated), commercial VCSEL f 3dB =40 GHz T case =40 C. Honeywell die-bonded 1E-4 0.01 0.1 1 thermal impedance (Z) (C/mW) 23
Proposed 1x12 modulator transmit module with on-board VCSEL readout lasers VCSEL chip 30:60:90 prism OE/VLSI chip with integrated modulator array 24
Modulators vs. VCSEL s Modulators: chips can be made with thousands all working (Bell Labs). Channel 1 Channel 2 Channel 3 Channel 4 Channel 13 Channel 14 Channel 15 Channel 16 Channel 17 Channel 18 Channel 19 Channel 20 Channel 5 Channel 6 Channel 7 Channel 8 Channel 21 Channel 22 Channel 23 Channel 24 Channel 9 Channel 10 Channel 11 Channel 12 Channel 27 Channel 28 Channel 25 Channel 26 Channel 29 Channel 30 Channel 31 Channel 32 VCSEL s: chips can be made with tens all working (Aralight). Channel 33 Channel 34 Channel 35 Channel 36 25
Modulators vs. VCSEL s readout laser spot array grating input fiber bundle p i n input beam readout beam p i n "smart pixel" IC output fiber bundle Modulators: packaging (nightmare?). photodiode/ modulator transistor logic photodiode/ modulator VCSEL s: essentially buttcoupled; relatively well developed. 26
Technology observations Early system experiments into the use of optical interconnects ignored third dimension (rack) physical constraints and assumed an open structure. Fitting (surface normal, e.g. VCSEL) optical interconnects to a rack structure requires bending either the light or electrical drive through a 90 o turn- most workers in the field agree that it is easier to do the latter via a flexible board. Packaging of linear VCSEL arrays is facilitated by optically accurate ferrule mating pins fixed to the board; however, 2D (flipchip) arrays suffer from the driver chip being in the way. Can we just etch pin access holes through it? Curve fitting Honeywell reliability data results in very effective model that predicts lifetime limit of VCSEL systems to ~ 20 Gbit/sec channel rate. Reducing thermal impedance to zero alleviates this, but may not be practical. Do we need external modulators? 27
What is the future path of optical interconnects? 10000 intrachip 1000 interchip number of channels 100 10 1 intraboard (C2OI) parallel-lan? interboard long distance (1990) campus networks (2000) Local Area Networks (2004, $2.4 bil/year) 100000 10000 1000 100 10 1 0.1 0.01 1E-3 interconnect distance (meters) 28
What is the future path of optical interconnects? 10000 intrachip 1000 interchip number of channels 100 10 long distance (1990) parallel-lan??? interboard? intraboard (C2OI) 1 Local Area Networks (2004, $2.4 bil/year) 100000 10000 1000 100 10 1 0.1 0.01 1E-3 interconnect distance (meters) 29
Conclusion An evolutionary path to optical interconnects would employ denser and denser modules, respecting the rack system paradigm. Allowing advanced packaging such as water cooling, such a 1000 channel module could be constructed and would be ~ 30x30 mm. Only an extremely compelling performance/cost argument would allow shifting away from the rack paradigm to allow full utilization of the third dimension for optical interconnects. 30