Texas Instruments Sitara XAM3715CBC Application Processor Structural Analysis For comments, questions, or more information about this report, or for any additional technical needs concerning semiconductor and electronics technology, please call Sales at Chipworks. 3685 Richmond Road, Suite 500, Ottawa, ON K2H 5B7, Canada Tel: 613.829.0414 Fax: 613.829.0515 www.chipworks.com
Structural Analysis Some of the information in this report may be covered by patents, mask, and/or copyright protection. This report should not be taken as an inducement to infringe on these rights. 2010 Chipworks Inc. This report is provided exclusively for the use of the purchasing organization. It can be freely copied and distributed within the purchasing organization, conditional upon the accompanying Chipworks accreditation remaining attached. Distribution of the entire report outside of the purchasing organization is strictly forbidden. The use of portions of the document for the support of the purchasing organization s corporate interest (e.g., licensing or marketing activities) is permitted, as defined by the fair use provisions of the copyright act. Accreditation to Chipworks must be attached to any portion of the reproduced information. SAR-1007-801 20585JMTW Revision 1.0 Published: August 6, 2010
Structural Analysis Table of Contents 1 Overview 1.1 List of Figures 1.2 List of Tables 1.3 Company Profile 1.4 Introduction 1.5 Device Summary 1.6 Process Summary 2 Device Overview 2.1 Package and Die 2.2 Die Features 3 Process Analysis 3.1 General Device Structure 3.2 Bond Pads 3.3 Dielectrics 3.4 Metallization 3.5 Vias and Contacts 3.6 Transistors and Poly 3.7 Isolation 3.8 Wells and Substrate 3.9 Standard Logic NAND Gate 4 High Density Six Transistor SRAM Cell 4.1 Overview 4.2 Plan View Analysis High Density 6T SRAM 4.3 Cross-Sectional Analysis (Perpendicular to Wordline) 5 Low Density Six Transistor SRAM 5.1 Overview 6 Materials Analysis 6.1 Overview 6.2 TEM-EDS Analyses of the Dielectrics 6.3 TEM-EDS Metallization, Silicides, and Contacts
Structural Analysis 7 Critical Dimensions 7.1 Horizontal Dimensions 7.2 Vertical Dimensions 8 References 9 Statement of Measurement Uncertainty and Scope Variation About Chipworks
Overview 1-1 1 Overview 1.1 List of Figures 2 Device Overview 2.1.1 Top Package View 2.1.2 Bottom Package View 2.1.3 Package X-Ray 2.1.4 Die Photograph 2.1.5 Die Markings 2.1.6 Die Annotated with Analysis Locations 2.2.1 Die Corner 1 2.2.2 Die Corner 2 2.2.3 Die Corner 3 2.2.4 Die Corner 4 2.2.5 Bond Pad Pitch 2.2.6 Bond Pad 3 Process Analysis 3.1.1 General View of the XAM3715CBC 3.1.2 Die Edge 3.1.3 Die Edge Seal 3.2.1 Bond Pad and Copper Stud 3.2.2 Bond Pad Via 3.2.3 Bond Pad Edge 3.3.1 Passivation and ILD 7 3.3.2 TEM Passivation 3.3.3 TEM ILD 7 3.3.4 SEM ILD 6 3.3.5 TEM ILD 6 3.3.6 TEM ILD 5 3.3.7 TEM ILD 4 3.3.8 TEM ILD 3 3.3.9 TEM ILD 2 3.3.10 TEM ILD 1 3.3.11 Pre-Metal Dielectric Overview 3.3.12 TEM Pre-Metal Dielectric and CESL 3.4.1 Minimum Space Metal 8 3.4.2 TEM Metal 8 Cap Layer 3.4.3 TEM Metal 8 Barrier Layers 3.4.4 Minimum Pitch Metal 7 3.4.5 TEM Bottom Metal 7 3.4.6 Minimum Pitch Metal 6 3.4.7 TEM Metal 6 Liner 3.4.8 Minimum Pitch Metal 5 3.4.9 TEM Metal 5 Thickness and Liner 3.4.10 TEM Metal 4 Thickness and Liner
Overview 1-2 3.4.11 TEM Metal 3 Thickness and Liner 3.4.12 TEM Minimum Pitch Metal 3 3.4.13 TEM Minimum Pitch Metal 2 3.4.14 TEM Minimum Pitch Peripheral Metal 1 3.4.15 TEM Minimum Pitch SRAM Metal 1 3.4.16 TEM Metal 1 Thickness and Liner 3.5.1 Minimum Width Via 7 3.5.2 Minimum Pitch Via 6s 3.5.3 TEM Via 6s 3.5.4 Stacked Via 5s Through Via 2s 3.5.5 Minimum Pitch Via 4s 3.5.6 TEM Contact to Diffusion 3.5.7 TEM Contact Top 3.5.8 TEM Contact Bottom 3.5.9 Contact to Poly 3.6.1 NMOS Transistors 3.6.2 PMOS Transistors 3.6.3 TEM NMOS Transistor 3.6.4 TEM PMOS Transistor 3.6.5 TEM Minimum Gate Length PMOS Transistor 3.6.6 TEM Transistor SWS 3.6.7 TEM Logic Transistor Gate Oxide 3.7.1 TEM Minimum Width and Pitch STI in Periphery 3.7.2 Poly Over STI 3.7.3 TEM STI Edge 3.8.1 TEM Diffraction Pattern Si Channel Region 3.8.2 SCM SRAM Wells 3.8.3 SRP Peripheral P-Well 3.8.4 SIMS Logic 3.9.1 NAND Gate 4 High Density Six Transistor SRAM Cell 4.1.1 6T SRAM 4.2.1 High Density 6T SRAM at Metal 3 4.2.2 High Density 6T SRAM at Metal 2 4.2.3 High Density 6T SRAM at Metal 1 4.2.4 High Density 6T SRAM at Poly 4.2.5 High Density 6T SRAM at Diffusion 4.3.1 TEM SRAM Perpendicular to Wordline 4.3.2 TEM PMOS Pull-Up Transistor 4.3.3 TEM NMOS Transistor 4.3.4 TEM SRAM Gate Oxide
Overview 1-3 5 Low Density Six Transistor SRAM 5.1.1 Low Density 6T SRAM at Metal 3 5.1.2 Low Density 6T SRAM at Metal 2 5.1.3 Low Density 6T SRAM at Metal 1 5.1.4 Low Density 6T SRAM at Poly 5.1.5 Low Density 6T SRAM at Diffusion 6 Materials Analysis 6.2.1 TEM-EDS Passivation 2 6.2.2 TEM-EDS Passivation 1 6.2.3 TEM-EDS ILD 7-2 6.2.4 TEM-EDS ILD 7-1 6.2.5 TEM-EDS ILD 6-5 6.2.6 TEM-EDS ILD 6-4 6.2.7 TEM-EDS ILD 6-3 6.2.8 TEM-EDS ILD 6-2 6.2.9 TEM-EDS ILD 6-1 6.2.10 TEM-EDS ILD 5-3 6.2.11 TEM-EDS ILD 5-2 6.2.12 TEM-EDS ILD 5-1 6.2.13 TEM-EDS PMD 7 6.2.14 TEM-EDS PMD 6 6.2.15 TEM-EDS PMD 5 6.2.16 TEM-EDS PMD 4 6.2.17 TEM-EDS CESL 6.2.18 TEM-EDS STI 6.3.1 TEM-EDS Metal 8 Cap Layer 6.3.2 TEM-EDS Metal 8 Bulk 6.3.3 TEM-EDS Metal 8 Bottom of Bulk 6.3.4 TEM-EDS Metal 8 Top Barrier 6.3.5 TEM-EDS Metal 8 Middle Barrier 6.3.6 TEM-EDS Metal 8 Bottom Barrier 6.3.7 TEM-EDS Metal 7 Top Barrier 6.3.8 TEM-EDS Metal 7 Bottom Barrier 6.3.9 TEM-EDS Metal 1 Top 6.3.10 TEM-EDS Contact Liner 6.3.11 TEM-EDS Polycide 6.3.12 TEM-EDS Source/Drain Silicide
Overview 1-4 1.2 List of Tables 1 Overview 1.4.1 Device Identification 1.5.1 Device Summary 1.6.1 Process Summary 2 Device Overview 2.1.1 Package, Die, and Bond Pad Sizes 3 Process Analysis 3.3.1 Dielectric Thicknesses 3.4.1 Metallization Vertical Dimensions 3.4.2 Metallization Horizontal Dimensions 3.5.1 Via and Contact Dimensions 3.6.1 Peripheral Transistor Horizontal Dimensions 3.6.2 Peripheral Transistor and Polycide Vertical Dimensions 3.8.1 Die Thickness and Well Depths 4 High Density Six Transistor SRAM Cell 4.2.1 High Density SRAM Dimensions 5 Low Density Six Transistor SRAM 5.1.1 Low Density SRAM Dimensions 7 Critical Dimensions 7.1.1 Package, Die, and Bond Pads 7.1.2 Minimum Pitch Metals 7.1.3 Minimum Pitch Contacts and Vias 7.1.4 Peripheral Transistor Horizontal Dimensions 7.1.5 High Density 6T SRAM Cell Dimensions 7.2.1 Vertical Dimensions Dielectrics 7.2.2 Vertical Dimensions Metals 7.2.3 Transistor Vertical Dimensions 7.2.4 Die and Wells Vertical Dimensions
About Chipworks About Chipworks Chipworks is the recognized leader in reverse engineering and patent infringement analysis of semiconductors and electronic systems. The company s ability to analyze the circuitry and physical composition of these systems makes them a key partner in the success of the world s largest semiconductor and microelectronics companies. Intellectual property groups and their legal counsel trust Chipworks for success in patent licensing and litigation earning hundreds of millions of dollars in patent licenses, and saving as much in royalty payments. Research & Development and Product Management rely on Chipworks for success in new product design and launch, saving hundreds of millions of dollars in design, and earning even more through superior product design and faster launches. Contact Chipworks To find out more information on this report, or any other reports in our library, please contact Chipworks at: Chipworks 3685 Richmond Rd. Suite 500 Ottawa, Ontario K2H 5B7 Canada T: 1.613.829.0414 F: 1.613.829.0515 Web site: www.chipworks.com Email: info@chipworks.com Please send any feedback to feedback@chipworks.com