W/ C V GS Gate-to-Source Voltage ± 20 dv/dt Peak Diode Recovery f 27

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PD 96329 Applications l High Efficiency Synchronous Rectification in SMPS l Uninterruptible Power Supply l High Speed Power Switching l Hard Switched and High Frequency Circuits Benefits l Improved Gate, Avalanche and Dynamic dv/dt Ruggedness l Fully Characterized Capacitance and Avalanche SOA l Enhanced body diode dv/dt and di/dt Capability l LeadFree l HalogenFree G D S IRFB367GPbF V DSS R DS(on) typ. max. I D D HEXFET Power MOSFET S D G TO22AB IRFB367GPbF 75V 7.34m: 9.m: 8A G D S Gate Drain Source Absolute Maximum Ratings Symbol Parameter Max. Units I D @ T C = 25 C Continuous Drain Current, VGS @ V 8c I D @ T C = C Continuous Drain Current, V GS @ V 56c A I DM Pulsed Drain Current d 3 P D @T C = 25 C Maximum Power Dissipation 4 W Linear Derating Factor.96 W/ C V GS GatetoSource Voltage ± 2 V dv/dt Peak Diode Recovery f 27 V/ns T J Operating Junction and 55 to 75 C T STG Storage Temperature Range Soldering Temperature, for seconds (.6mm from case) Mounting torque, 632 or M3 screw 3 lbxin (.Nxm) Avalanche Characteristics E AS (Thermally limited) Single Pulse Avalanche Energy e 2 mj I AR Avalanche Currentc 46 A E AR Repetitive Avalanche Energy g 4 mj Thermal Resistance Symbol Parameter Typ. Max. Units R θjc JunctiontoCase j.45 R θcs CasetoSink, Flat Greased Surface, TO22.5 C/W R θja JunctiontoAmbient, TO22 62 www.irf.com 8/2/

IRFB367GPbF Static @ (unless otherwise specified) Symbol Parameter Min. Typ. Max. Units V (BR)DSS DraintoSource Breakdown Voltage 75 V V (BR)DSS / T J Breakdown Voltage Temp. Coefficient.96 V/ C R DS(on) Static DraintoSource OnResistance 7.34 9. mω V GS(th) Gate Threshold Voltage 2. 4. V I DSS DraintoSource Leakage Current 2 µa 25 I GSS GatetoSource Forward Leakage na GatetoSource Reverse Leakage Dynamic @ (unless otherwise specified) Symbol Parameter Min. Typ. Max. Units gfs Forward Transconductance 5 S Q g Total Gate Charge 56 84 nc Q gs GatetoSource Charge 3 Q gd GatetoDrain ("Miller") Charge 6 Q sync Total Gate Charge Sync. (Q g Q gd ) 4 R G(int) Internal Gate Resistance.55 Ω t d(on) TurnOn Delay Time 6 ns t r Rise Time t d(off) TurnOff Delay Time 43 t f Fall Time 96 C iss Input Capacitance 37 pf C oss Output Capacitance 28 C rss Reverse Transfer Capacitance 3 C oss eff. (ER) Effective Output Capacitance (Energy Related)j 38 C oss eff. (TR) Effective Output Capacitance (Time Related)h 6 Diode Characteristics Symbol Parameter Min. Typ. Max. Units I S Continuous Source Current 8c A Conditions V GS = V, I D = 25µA Reference to 25 C, I D = 5mAd V GS = V, I D = 46A g V DS = V GS, I D = µa V DS = 75V, V GS = V V DS = 6V, V GS = V, T J = 25 C V GS = 2V V GS = 2V Conditions V DS = 5V, I D = 46A I D = 46A V DS = 38V V GS = V g I D = 46A, V DS =V, V GS = V V DD = 49V I D = 46A R G = 6.8Ω V GS = V g V GS = V V DS = 5V ƒ =.MHz V GS = V, V DS = V to 6V j V GS = V, V DS = V to 6V h Conditions MOSFET symbol (Body Diode) showing the I SM Pulsed Source Current 3 integral reverse G (Body Diode)d pn junction diode. V SD Diode Forward Voltage.3 V, I S = 46A, V GS = V g t rr Reverse Recovery Time 33 5 ns V R = 64V, 39 59 T J = 25 C I F = 46A Q rr Reverse Recovery Charge 32 48 nc di/dt = A/µs g 47 7 T J = 25 C I RRM Reverse Recovery Current.9 A t on Forward TurnOn Time Intrinsic turnon time is negligible (turnon is dominated by LSLD) D S Notes: I SD 46A, di/dt 92A/µs, V DD V (BR)DSS, T J 75 C. Calculated continuous current based on maximum allowable junction Pulse width 4µs; duty cycle 2%. temperature. Note that current limitations arising from heating of the C oss eff. (TR) is a fixed capacitance that gives the same charging time device leads may occur with some lead mounting arrangements. as C oss while V DS is rising from to 8% V DSS. Repetitive rating; pulse width limited by max. junction temperature. C oss eff. (ER) is a fixed capacitance that gives the same energy as ƒ Limited by T C oss while V DS is rising from to 8% V DSS. Jmax, starting, L =.2mH R ˆ R θ is measured at T J approximately 9 C. G = 25Ω, I AS = 46A, V GS =V. Part not recommended for use above this value. 2 www.irf.com

C, Capacitance (pf) V GS, GatetoSource Voltage (V) I D, DraintoSource Current (A) R DS(on), DraintoSource On Resistance (Normalized) I D, DraintoSource Current (A) I D, DraintoSource Current (A) IRFB367GPbF VGS TOP 5V V 8.V 6.V 5.5V 5.V 4.8V BOTTOM 4.5V VGS TOP 5V V 8.V 6.V 5.5V 5.V 4.8V BOTTOM 4.5V 4.5V 4.5V 6µs PULSE WIDTH Tj = 25 C. V DS, DraintoSource Voltage (V) Fig. Typical Output Characteristics 6µs PULSE WIDTH Tj = 75 C. V DS, DraintoSource Voltage (V) Fig 2. Typical Output Characteristics 3. 2.5 I D = 8A V GS = V T J = 75 C 2..5 V DS = 25V 6µs PULSE WIDTH. 2 3 4 5 6 7 8 V GS, GatetoSource Voltage (V) Fig 3. Typical Transfer Characteristics..5 6 4 2 2 4 6 8 2468 T J, Junction Temperature ( C) Fig 4. Normalized OnResistance vs. Temperature V GS = V, f = MHZ C iss = C gs C gd, C ds SHORTED C rss = C gd C oss = C ds C gd 2.. 8. I D = 46A V DS = 24V V DS = 5V C iss 6. C oss 4. C rss 2.. 2 3 4 5 6 V DS, DraintoSource Voltage (V) Q G, Total Gate Charge (nc) Fig 5. Typical Capacitance vs. DraintoSource Voltage Fig 6. Typical Gate Charge vs. GatetoSource Voltage www.irf.com 3

Energy (µj) E AS, Single Pulse Avalanche Energy (mj) V (BR)DSS, I D, Drain Current (A) DraintoSource Breakdown Voltage (V) I SD, Reverse Drain Current (A) I D, DraintoSource Current (A) IRFB367GPbF OPERATION IN THIS AREA LIMITED BY R DS (on) T J = 75 C V GS = V...5..5 2. V SD, SourcetoDrain Voltage (V) Fig 7. Typical SourceDrain Diode Forward Voltage msec msec µsec Tc = 25 C Tj = 75 C Single Pulse DC V DS, DraintoSource Voltage (V) Fig 8. Maximum Safe Operating Area 8 7 6 5 4 3 2 95 9 85 8 75 Id = 5mA 25 5 75 25 5 75 T C, Case Temperature ( C) Fig 9. Maximum Drain Current vs. Case Temperature 7 6 4 2 2 4 6 8 2468 T J, Temperature ( C ) Fig. DraintoSource Breakdown Voltage.2..8.6.4 5 45 4 35 3 25 2 5 I D TOP 5.6A A BOTTOM 46A.2 5. 2 3 4 5 6 7 8 25 5 75 25 5 75 V DS, DraintoSource Voltage (V) Starting T J, Junction Temperature ( C) Fig. Typical C OSS Stored Energy Fig 2. Maximum Avalanche Energy vs. DrainCurrent 4 www.irf.com

E AR, Avalanche Energy (mj) Avalanche Current (A) IRFB367GPbF.. D =.5 Thermal Response ( Z thjc ) C/W...2..5.2. R R R 2 R 2 R 3 R 3 τ J τ J τ τ τ 2 τ 2 τ 3 τ 3 Ci= τi/ri Ci i Ri R 4 Ri ( C/W) τi (sec) R 4.9.3 Notes: SINGLE PULSE. Duty Factor D = t/t2 ( THERMAL RESPONSE ) 2. Peak Tj = P dm x Zthjc Tc. E6 E5.... t, Rectangular Pulse Duration (sec) Fig 3. Maximum Effective Transient Thermal Impedance, JunctiontoCase τ 4 τ 4 τ C τ.26925.3.4973.3.26766.8693. Duty Cycle = Single Pulse Allowed avalanche Current vs avalanche pulsewidth, tav, assuming Tj = 5 C and Tstart =25 C (Single Pulse).5. Allowed avalanche Current vs avalanche pulsewidth, tav, assuming Τj = 25 C and Tstart = 5 C...E6.E5.E4.E3.E2.E tav (sec) Fig 4. Typical Avalanche Current vs.pulsewidth 5 25 75 5 25 TOP Single Pulse BOTTOM.% Duty Cycle I D = 46A Notes on Repetitive Avalanche Curves, Figures 4, 5: (For further info, see AN5 at www.irf.com). Avalanche failures assumption: Purely a thermal phenomenon and failure occurs at a temperature far in excess of T jmax. This is validated for every part type. 2. Safe operation in Avalanche is allowed as long ast jmax is not exceeded. 3. Equation below based on circuit and waveforms shown in Figures 6a, 6b. 4. P D (ave) = Average power dissipation per single avalanche pulse. 5. BV = Rated breakdown voltage (.3 factor accounts for voltage increase during avalanche). 6. I av = Allowable avalanche current. 7. T = Allowable rise in junction temperature, not to exceed T jmax (assumed as 25 C in Figure 4, 5). t av = Average time in avalanche. D = Duty cycle in avalanche = t av f Z thjc (D, t av ) = Transient thermal resistance, see Figures 3) 25 5 75 25 5 75 Starting T J, Junction Temperature ( C) Fig 5. Maximum Avalanche Energy vs. Temperature P D (ave) = /2 (.3 BV I av ) = DT/ Z thjc I av = 2DT/ [.3 BV Z th ] E AS (AR) = P D (ave) t av www.irf.com 5

Q RR (A) I RR (A) Q RR (A) V GS(th), Gate Threshold Voltage (V) I RR (A) IRFB367GPbF 4.5 4. 2 I F = 3A V R = 64V 3.5 5 T J = 25 C 3. 2.5 2..5 I D = µa I D = 25µA I D =.ma I D =.A 5. 75 5 25 25 5 75 25 5 75 2 T J, Temperature ( C ) Fig 6. Threshold Voltage vs. Temperature 2 4 6 8 di F /dt (A/µs) Fig. 7 Typical Recovery Current vs. di f /dt 2 I F = 46A V R = 64V 56 48 I F = 3A V R = 64V 5 T J = 25 C 4 T J = 25 C 32 24 5 6 8 2 4 6 8 2 4 6 8 di F /dt (A/µs) di F /dt (A/µs) Fig. 8 Typical Recovery Current vs. di f /dt Fig. 9 Typical Stored Charge vs. di f /dt 56 48 4 I F = 46A V R = 64V T J = 25 C 32 24 6 8 2 4 6 8 di F /dt (A/µs) Fig. 2 Typical Stored Charge vs. di f /dt 6 www.irf.com

IRFB367GPbF D.U.T ƒ Circuit Layout Considerations Low Stray Inductance Ground Plane Low Leakage Inductance Current Transformer Reverse Recovery Current Driver Gate Drive Period P.W. D.U.T. I SD Waveform Body Diode Forward Current di/dt D.U.T. V DS Waveform Diode Recovery dv/dt D = P.W. Period V GS =V V DD * R G dv/dt controlled by RG Driver same type as D.U.T. I SD controlled by Duty Factor "D" D.U.T. Device Under Test V DD ReApplied Voltage Body Diode Inductor Curent Current Forward Drop Ripple 5% I SD * V GS = 5V for Logic Level Devices Fig 2. Peak Diode Recovery dv/dt Test Circuit for NChannel HEXFET Power MOSFETs 5V tp V (BR)DSS V DS L DRIVER R G 2V V GS tp D.U.T IAS.Ω V DD A I AS Fig 2a. Unclamped Inductive Test Circuit Fig 2b. Unclamped Inductive Waveforms L D V DS V DD V DS 9% D.U.T % V GS Pulse Width < µs Duty Factor <.% V GS t d(on) t r t d(off) t f Fig 22a. Switching Time Test Circuit Fig 22b. Switching Time Waveforms Vds Id Vgs K DUT L VCC Vgs(th) Qgs Qgs2 Qgd Qgodr Fig 23a. Gate Charge Test Circuit Fig 23b. Gate Charge Waveform www.irf.com 7

IRFB367GPbF TO22AB Package Outline Dimensions are shown in millimeters (inches) TO22AB Part Marking Information EXAMPLE: THIS IS AN IRFB43GPBF Note: "G" suffix in part number indicates "Halogen Free" Note: "P" in assembly line position indicates "Lead Free" INTERNATIONAL RECTIFIER LOGO ASSEMBLY LOT CODE PART NUMBER DATE CODE: Y= LAST DIGIT OF CALENDAR YEAR WW= WORK WEEK X= FACT ORY CODE TO22AB packages are not recommended for Surface Mount Application. Note: For the most current drawing please refer to IR website at: http://www.irf.com/package/ Data and specifications subject to change without notice. This product has been designed and qualified for the Industrial market. Qualification Standards can be found on IR s Web site. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 9245, USA Tel: (3) 25275 TAC Fax: (3) 252793 Visit us at www.irf.com for sales contact information. 8/2 8 www.irf.com