Noel Technologies. Provider of Advanced Lithography and Semiconductor Thin Film Services

Similar documents
Application-Based Opportunities for Reused Fab Lines

A Perspective on Semiconductor Equipment. R. B. Herring March 4, 2004

Photolithography I ( Part 1 )

Lithography in our Connected World

Fabricating 2.5D, 3D, 5.5D Devices

Progress due to: Feature size reduction - 0.7X/3 years (Moore s Law). Increasing chip size - 16% per year. Creativity in implementing functions.

MAPPER: High throughput Maskless Lithography

450mm and Moore s Law Advanced Packaging Challenges and the Impact of 3D

MEMS in ECE at CMU. Gary K. Fedder

Waveguide-Integrated Optical Antenna nanoleds for On-Chip Communication

University of California, Berkeley Department of Mechanical Engineering. ME 290R Topics in Manufacturing, Fall 2014: Lithography

Feature-level Compensation & Control

DOE Project: Resist Characterization

Holst Centre Wireless Autonomous Sensor Technologies & Flexible Electronics

Market and technology trends in advanced packaging

2010 IRI Annual Meeting R&D in Transition

Nanotechnology, the infrastructure, and IBM s research projects

Image sensor combining the best of different worlds

MEMS for RF, Micro Optics and Scanning Probe Nanotechnology Applications

Silicon Photonics: A Platform for Integration, Wafer Level Assembly and Packaging

Nanostencil Lithography and Nanoelectronic Applications

Flexible Hybrid Electronics Fabricated with High-Performance COTS ICs using RTI CircuitFilm TM Technology

Beyond Moore the challenge for Europe

Mass transfer with elastomer stamps for microled displays.

TXC Proprietary Info June 2012

Technology for the MEMS processing and testing environment. SUSS MicroTec AG Dr. Hans-Georg Kapitza

Lecture: Integration of silicon photonics with electronics. Prepared by Jean-Marc FEDELI CEA-LETI

TSI, or through-silicon insulation, is the

MEDIA RELEASE INSTITUTE OF MICROELECTRONICS KICKS OFF COPPER WIRE BONDING CONSORTIUM II TO TACKLE COPPER INTERCONNECTS RELIABILITY ISSUES

450mm silicon wafers specification challenges. Mike Goldstein Intel Corp.

Introduction of ADVANTEST EB Lithography System

Mobile Electrostatic Carrier (MEC) evaluation for a GaAs wafer backside manufacturing process

Intel's 65 nm Logic Technology Demonstrated on 0.57 µm 2 SRAM Cells

The SEMATECH Model: Potential Applications to PV

3D ICs: Recent Advances in the Industry

High-yield Fabrication Methods for MEMS Tilt Mirror Array for Optical Switches

Process Optimization

Chapter 1, Introduction

EE C245 ME C218 Introduction to MEMS Design

EE105 Fall 2015 Microelectronic Devices and Circuits. Invention of Transistors

Des MEMS aux NEMS : évolution des technologies et des concepts aux travers des développements menés au LETI

InP-based Photonic Integration: Learning from CMOS

Technology & Manufacturing

EE C245 ME C218 Introduction to MEMS Design Fall 2010

450mm patterning out of darkness Backend Process Exposure Tool SOKUDO Lithography Breakfast Forum July 10, 2013 Doug Shelton Canon USA Inc.

SUNY Poly in a New Era

Manufacturing Development of a New Electroplated Magnetic Alloy Enabling Commercialization of PwrSoC Products

Critical Dimension Enhancement of DUV Photolithography on the ASML 5500/300. Francesca Calderon Miramonte High School August 13th, 2015

EUV Supporting Moore s Law

Flexline - A Flexible Manufacturing Method for Wafer Level Packages (Extended Abstract)

DUV. Matthew McLaren Vice President Program Management, DUV. 24 November 2014

32nm High-K/Metal Gate Version Including 2nd Generation Intel Core processor family

Photonique sur silicium: Tendances et perspectives de marché

Simulation of High Resistivity (CMOS) Pixels

Index. Cambridge University Press Silicon Photonics Design Lukas Chrostowski and Michael Hochberg. Index.

Part 5-1: Lithography

The Department of Advanced Materials Engineering. Materials and Processes in Polymeric Microelectronics

Evaluating and Optimizing Tradeoffs in CMOS RFIC Upconversion Mixer Design. by Dr. Stephen Long University of California, Santa Barbara

IMAPS NE 45 A HETEROGENEOUS SIP SOLUTION FOR RF APPLICATIONS

Plan Optik AG. Plan Optik AG PRODUCT CATALOGUE

Recent Innovations in MEMS Sensors for PNT Applications

DTU DANCHIP an open access micro/nanofabrication facility bridging academic research and small scale production

IMPACT OF 450MM ON CMP

Innovative Mask Aligner Lithography for MEMS and Packaging

Applications of Maskless Lithography for the Production of Large Area Substrates Using the SF-100 ELITE. Jay Sasserath, PhD

My USM. Mustafa G. Guvench. Professor, Electrical Engineering

Strategies for low cost imprint molds

HOW TO CONTINUE COST SCALING. Hans Lebon

Recent Developments in Multifunctional Integration. Stephan Guttowski, Head of Technology Park»Heterointegration«, Fraunhofer FMD

45nm Foundry CMOS with Mask-Lite Reduced Mask Costs

Laser patterning and projection lithography

SWTW 2000, June Assessing Pad Damage and Bond Integrity for Fine Pitch Probing

IMPACT Roundtable Lithography + DfM

Sonion TC100Z21A DigiSiMic Silicon Condensor Microphone MEMS Process Review

TWINSCAN XT:1950i Water-based immersion taken to the max Enabling fast, single-exposure lithography at sub 40 nm

Introduction to VLSI ASIC Design and Technology

Reducing MEMS product development and commercialization time

Winter College on Optics: Fundamentals of Photonics - Theory, Devices and Applications February 2014

IWORID J. Schmitz page 1. Wafer-level CMOS post-processing Jurriaan Schmitz

Projects and Partners Working with Chalcogenide Advanced Manufacturing Partnership (ChAMP)

Update: SOI Wafer Market Continues Its Growth

45nm Foundry CMOS with Mask-Lite Reduced Mask Costs

DTU DANCHIP an open access micro/nanofabrication facility bridging academic research and small scale production

Emerging MEMS & Sensor Technologies to Watch: Alissa M. Fitzgerald, Ph.D., Founder & CEO Semicon West 2018

Outline. 1 Introduction. 2 Basic IC fabrication processes. 3 Fabrication techniques for MEMS. 4 Applications. 5 Mechanics issues on MEMS MDL NTHU

(12) Patent Application Publication (10) Pub. No.: US 2003/ A1

Optical Microlithography XXVIII

DC-40GHz ATTENUATOR. GaAs Monolithic Microwave IC. Insertion Loss ( db )

Doug Dunn ASML President and Chief Executive Officer Deutsche Bank Conference London, England September 19, / Slide 1

(Complementary E-Beam Lithography)

POSSUM TM Die Design as a Low Cost 3D Packaging Alternative

Optical Lithography. Keeho Kim Nano Team / R&D DongbuAnam Semi

Body-Biased Complementary Logic Implemented Using AlN Piezoelectric MEMS Switches

Extending The Life Of 200mm Fabs And The Re-use of Second Hand Tools

Advanced Packaging Lithography and Inspection Solutions for Next Generation FOWLP-FOPLP Processing

Through-Silicon-Via Inductor: Is it Real or Just A Fantasy?

Packaging Roadmap: The impact of miniaturization. Bob Pfahl, inemi Celestica-iNEMI Technology Forum May 15, 2007

Lecture 1 Introduction to Solid State Electronics

SAMPLE SLIDES & COURSE OUTLINE. Core Competency In Semiconductor Technology: 2. FABRICATION. Dr. Theodore (Ted) Dellin

ATV 2011: Computer Engineering

Transcription:

Noel Technologies Provider of Advanced Lithography and Semiconductor Thin Film Services

Noel Technologies Keith Best Biography Over the last 27 years, Keith Best has held a variety of semiconductor processing and applications positions for both device manufacturing and capital equipment companies, of which 11 years were with ASML Special Applications. Keith specializes in Photolithography and Process integration for the more than Moore application markets. He is currently the Director of Photolithography at Noel Technologies. Keith holds a B.Sc. Honors Degree in Materials Science from the University of Greenwich, UK. He has numerous publications and holds 16 US patents in the areas of Photolithography and Process integration.

Abstract Over the past few years there has been a paradigm shift in the nature of manufacturing in Silicon Valley. What was once a manufacturing hub, is now a center for research and development. In this new era, many of the local Semiconductor manufacturing companies have adapted their approach to focus on the More than Moore Application markets and providing wafer processing services to generate additional revenue. These new specialty foundries are agile and capable of supplying high quality devices and wafer processing services. This, coupled with the wealth of engineering experience, can readily supply solutions to enable new technologies. This talk provides an insight into how these specialty foundries operate and examples of unique problems they can solve to help R&D centers progress to volume manufacturing and bridge the so called valley of death.

Noel Technologies Specialty foundries Enabling the transition from lab to fab

Outline Brief History Markets Applications Processing Challenges The Valley of Death Specialty Foundries Enabling Technologies Conclusions

History Shockley Labs 1956 Mountain View, CA Traitorous 8 1957 - Fairchild Intel Pioneering ------------------------> Fairchild 8 ---------> Fair Children & Moore s Law

Noel Technologies Silicon Valley From Fruit to Gold

New Era Silicon Valley Fruit again? The original Shockley building at 391 San Antonio Road, Mountain View, California, was a produce market in 2006

Life beyond Fruit The Silicon Valley landscape has changed dramatically, we are now returning to our R &D roots Valley jobs are not in high volume manufacturing, they are in High technology innovation, application focused The Valley s engineering talent is adapting to this new environment, where market forces are shaping the future beyond Silicon ICs

Markets

More than Moore Applications Lab on a Chip Solar Micro mirror arrays MEMS - Gyroscopes Flexible electronics LEDs Optoacoustic Microphones Thin Film Heads HDD

Material Handling Challenges Small Pieces Perforated wafers Flexible thin substrates Transparent substrates Small substrates e.g. InP Curved Surfaces

Processing Challenges Cantilevers T Gates Waveguides Nanotubes Lithography in 3D Photonic Crystals

Valley of Death Photonics Analog RF Bio Chips Power LEDs MEMS Solar Passives Collaborative Zone Collaborative Zone

What are Specialty Foundries? Facilities that provide wafer processing services; from single steps, to complete product build, basically 3 types: Integrated device manufacturers (IDMs) who open up part of their fab for more than Moore activity Researchers who work within the University network R&D Small and Medium Enterprises (SME) utilize in house processes and ad hoc networks: Universities and other SMEs to produce new products e.g. Noel Technologies

What are Specialty Foundries? Provide customized processing services to researchers and industry: Significantly less material restrictions than CMOS facilities Thin and Thick substrates Transparent and perforated substrates Double side processing Substrate dimension requirements pieces to 300mm, later 450mm

Specialty Foundry Models Model Cost Time to Market IP Ownership Collaboration IDMs Low Intermediate Negotiated Yes University Labs Low Proof of concept Typically shared Research driven SMEs (Noel Technologies) Low Fast Your IP is your IP Yes Captive Foundry High Fast, restricted to mainstream Company Selective

University Labs California Universities have been increasing their capabilities R & D efforts are utilizing equipment built for manufacturing UCSB, UC Berkeley, UCLA, Stanford (SNF) have opened their doors to industry to provide access to researchers Industrial researchers can develop next technology node prototype devices prior to ramping up In some cases, Universities have more equipment capabilities than industry, however, collaboration is key to success

University Labs From Lab tools to Fab tools - UCSB ASML 5500/300 DUV Resolution 0.15um

University Labs From Lab tools to Fab tools - UCLA Headway Spinner - UCLA SVG 88 Series wafer track UCLA

University Labs From Lab tools to Fab tools - UCLA Automated CD SEM ASML 5500/200 i-line Resolution 0.35um

Enabling Technologies To address material handling challenges, Noel Technologies co-developed a unique Mobile Electrostatic Carrier (MESC) with Beam Services Inc.

Lithography Carriers

Existing Temporary Bonding Solutions

Existing Temporary Bonding Lithography Solutions Hot Plate removal Steam method 2 wafer mounted on 4 Silicon carrier with H20 droplets Dump rinse removal Method Capillary action

Enabling Technologies Beam Services MESC Low voltage, High Performance: 200+ hrs 400V charge Electrostatic force holds substrate in position on carrier

Design requirement - ASML Handling Must be able to cycle through system without hang ups Functionality - Must bond to target substrate firmly and cycle through system without sliding on carrier Flatness: <2um TTV Mechanical reproducibility: Substrate placement must be repeatable, within the capture range of the alignment system

Lithography Carriers

Testing Results 4 and 8 quartz mobile carriers were successfully used on ASML systems at Stanford University & SVTC Completed multiple cycles validating handling compliance with scanners and steppers 6 and 8 mobile carriers successfully used on ASML, Canon, Nikon and GCA systems

Conclusions A new era, beyond fruit, requires the same pioneering attitude as the Fairchild 8 go where no one has gone before Crossing the Valley of Death - Collaboration between SMEs and the University network provides a cost effective bridge from lab to fab New enabling technologies are providing pioneers with the tools they need to develop new products

Acknowledgements UC Berkeley, Marvell, Nanolab - http://nanolab.berkeley.edu UC Santa Barbara - http://www.nanotech.ucsb.edu Stanford Nanofab (SNF) - http://snf.stanford.edu UC Los Angeles - http://www.isnc.cnsi.ucla.edu Beam Services Inc. http://www.beamservices.com Steve Kent Noel Technologies

Specialty Foundry Noel Technologies, Inc. is a Silicon Valley based specialty foundry focused on process development, optimization, quality and delivery. An ISO 9001 registered facility, Noel Technologies offers process development and fabrication from 50mm up to 300mm