Low Capacitance, Low Charge Injection, ±15 V/+12 V icmo PT in OT-23 AG121/AG122 FEATURE 2.4 pf off capacitance <1 pc charge injection Low leakage;.6 na maximum @ 85 C 12 Ω on resistance Fully specified at ±15 V, +12 V No VL supply required 3 V logic-compatible inputs Rail-to-rail operation 6-lead OT-23 package APPLICATION Automatic test equipment ata acquisition systems Battery-powered systems ample-and-hold systems Audio signal routing Video signal routing Communication systems GENERAL ECRIPTION The AG121/AG122 are monolithic complementary metal-oxide semiconductor (CMO) devices containing an PT switch designed in an icmo (industrial CMO) process. icmo is a modular manufacturing process combining high voltage CMO and bipolar technologies. It enables the development of a wide range of high performance analog ICs capable of 33 V operation in a footprint that no previous generation of high voltage parts has been able to achieve. Unlike analog ICs using conventional CMO processes, icmo components can tolerate high supply voltages while providing increased performance, dramatically lower power consumption, and reduced package size. The ultralow capacitance and charge injection of these switches make them ideal solutions for data acquisition and sample-and-hold applications, where low glitch and fast settling are required. Fast switching speed coupled with high signal bandwidth make the parts suitable for video signal switching. FUNCTIONAL BLOCK IAGRAM AG121 IN AG122 WITCHE HOWN FOR A LOGIC 1 INPUT Figure 1. icmo construction ensures ultralow power dissipation, making the parts ideally suited for portable and batterypowered instruments. The AG121/AG122 contain a single-pole/single-throw (PT) switch. Figure 1 shows that with a logic input of 1, the switch of the AG121 is closed and that of the AG122 is open. Each switch conducts equally well in both directions when on and has an input signal range that extends to the supplies. In the off condition, signal levels up to the supplies are blocked. PROUCT HIGHLIGHT 1. Ultralow capacitance. 2. <1 pc charge injection. 3. Ultralow leakage. 4. 3 V logic-compatible digital inputs: VIH = 2. V, VIL =.8 V. 5. No VL logic power supply required. 6. OT-23 package. IN 6576-1 Rev. Information furnished by Analog evices is believed to be accurate and reliable. However, no responsibility is assumed by Analog evices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. pecifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog evices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 916, Norwood, MA 262-916, U..A. Tel: 781.329.47 www.analog.com Fax: 781.461.3113 28 Analog evices, Inc. All rights reserved.
TABLE OF CONTENT Features... 1 Applications... 1 Functional Block iagram... 1 General escription... 1 Product Highlights... 1 Revision History... 2 pecifications... 3 ual upply... 3 ingle upply... 4 Absolute Maximum Ratings...5 E Caution...5 Pin Configuration and Function escriptions...6 Typical Performance Characteristics...7 Test Circuits... 1 Terminology... 12 Outline imensions... 13 Ordering Guide... 13 REVIION HITORY 2/8 Revision : Initial Version Rev. Page 2 of 16
PECIFICATION UAL UPPLY V = 15 V ± 1%, V = 15 V ± 1%, GN = V, unless otherwise noted. Table 1. Parameter 25 C 4 C to +85 C B Version 1 4 C to +125 C Unit Test Conditions/Comments ANALOG WITCH Analog ignal Range V to V V On Resistance (RON) 12 Ω typ V = +13.5 V, V = 13.5 V 2 24 27 Ω max V = ±1 V, I = 1 ma; see Figure 2 On Resistance Flatness (RFLAT(ON)) 2 Ω typ V = 5 V, V, and +5 V; I = 1 ma 6 72 79 Ω max LEAKAGE CURRENT V = +16.5 V, V = 16.5 V ource Off Leakage, I (Off) ±.4 na typ V = ±1 V, V = ±1 V; see Figure 21 ±.1 ±.6 ±1 na max rain Off Leakage, I (Off) ±.4 na typ V = ±1 V, V = ±1 V; see Figure 21 ±.1 ±.6 ±1 na max Channel On Leakage, I, I (On) ±.4 na typ V = V = ±1 V; see Figure 22 ±.15 ±.6 ±1 na max IGITAL INPUT Input High Voltage, VINH 2. V min Input Low Voltage, VINL.8 V max Input Current, IINL or IINH.5 μa typ VIN = VINL or VINH ±.1 μa max igital Input Capacitance, CIN 2.5 pf typ YNAMIC CHARACTERITIC 2 ton 14 ns typ RL = 3 Ω, CL = 35 pf 17 2 23 ns max V = 1 V; see Figure 26 toff 9 ns typ RL = 3 Ω, CL = 35 pf 15 13 141 ns max V = 1 V; see Figure 26 Charge Injection.8 pc typ V = V, R = Ω, CL = 1 nf; see Figure 27 Off Isolation 8 db typ RL = 5 Ω, CL = 5 pf, f = 1 MHz; see Figure 23 Total Harmonic istortion + Noise.15 % typ RL = 1 kω, 5 V rms, f = 2 Hz to 2 khz 3 db Bandwidth 66 MHz typ RL = 5 Ω, CL = 5 pf; see Figure 24 C (Off) 2.4 pf typ V = V, f = 1 MHz 3 pf max V = V, f = 1 MHz C (Off) 2.8 pf typ V = V, f = 1 MHz 3.3 pf max V = V, f = 1 MHz C, C (On) 4.7 pf typ V = V, f = 1 MHz 5.6 pf max V = V, f = 1 MHz POWER REQUIREMENT V = +16.5 V, V = 16.5 V I.1 μa typ igital inputs = V or V 1. μa max I 6 μa typ igital inputs = 5 V 95 μa max I.1 μa typ igital inputs = V, 5 V or V 1. μa max V/V ±5 to ±16.5 V min/max GN = V 1 Temperature range for B version is 4 C to +125 C. 2 Guaranteed by design, not subject to production test. Rev. Page 3 of 16
INGLE UPPLY V = 12 V ± 1%, V = V, GN = V, unless otherwise noted. Table 2. Parameter 25 C B Version 1 4 C to +85 C 4 C to +125 C Unit Test Conditions/Comments ANALOG WITCH Analog ignal Range V to V V On Resistance (RON) 3 Ω typ V = 1.8 V, V = V 475 567 625 Ω max V = V to 1 V, I = 1 ma; see Figure 2 On Resistance Flatness (RFLAT(ON)) 6 Ω typ V = 3 V, 6 V, and 9 V, I = 1 ma LEAKAGE CURRENT V = 13.2 V, V = V ource Off Leakage, I (Off) ±.6 na typ V = 1 V or 1 V, V = 1 V or 1 V; see Figure 21 ±.1 ±.6 ±1 na max rain Off Leakage, I (Off) ±.6 na typ V = 1 V or 1 V, V = 1 V or 1 V; see Figure 21 ±.1 ±.6 ±1 na max Channel On Leakage, I, I (On) ±.4 na typ V = V = 1 V or 1 V; see Figure 22 ±.15 ±.6 ±1 na max IGITAL INPUT Input High Voltage, VINH 2. V min Input Low Voltage, VINL.8 V max Input Current, IINL or IINH.1 μa typ VIN = VINL or VINH ±.1 μa max igital Input Capacitance, CIN 3 pf typ YNAMIC CHARACTERITIC 2 ton 19 ns typ RL = 3 Ω, CL = 35 pf 25 295 34 ns max V = 8 V; see Figure 26 toff 12 ns typ RL = 3 Ω, CL = 35 pf 155 19 21 ns max V = 8 V; see Figure 26 Charge Injection.8 pc typ V = 6 V, R = Ω, CL = 1 nf; see Figure 27 Off Isolation 8 db typ RL = 5 Ω, CL = 5 pf, f = 1 MHz; see Figure 23 3 db Bandwidth 52 MHz typ RL = 5 Ω, CL = 5 pf; see Figure 24 C (Off) 2.7 pf typ V = 6 V, f = 1 MHz 3.3 pf max V = 6 V, f = 1 MHz C (Off) 3.1 pf typ V = 6 V, f = 1 MHz 3.6 pf max V = 6 V, f = 1 MHz C, C (On) 5.3 pf typ V = 6 V, f = 1 MHz 6.3 pf max V = 6 V, f = 1 MHz POWER REQUIREMENT V = 13.2 V I.1 μa typ igital inputs = V or V 1. μa max I 6 μa typ igital inputs = 5 V 95 μa max V +5/+16.5 V min/max V = V, GN = V 1 Temperature range for B version is 4 C to +125 C. 2 Guaranteed by design, not subject to production test. Rev. Page 4 of 16
ABOLUTE MAXIMUM RATING TA = 25 C, unless otherwise noted. Table 3. Parameter Rating V to V 35 V V to GN.3 V to +25 V V to GN +.3 V to 25 V Analog Inputs 1 V.3 V to V +.3 V or 3 ma, whichever occurs first igital Inputs 1 GN.3 V to V +.3 V or 3 ma, whichever occurs first Peak Current, or 1 ma (pulsed at 1 ms, 1% duty cycle maximum) Continuous Current per 3 ma Channel, or Operating Temperature Range 4 C to +125 C Industrial (B Version) torage Temperature Range 65 C to +15 C Junction Temperature 15 C 6 Lead OT-23 θja,thermal Impedance 229.6 C/W θjc, Thermal Impedance 91.99 C/W Reflow oldering Peak 26 C Temperature, Pb-free tresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. E CAUTION 1 Overvoltages at IN,, or are clamped by internal diodes. Current should be limited to the maximum ratings given. Rev. Page 5 of 16
PIN CONFIGURATION AN FUNCTION ECRIPTION V 1 GN 2 V 3 AG121/ AG122 TOP VIEW (Not to cale) IN Figure 2. OT-23 Pin Configuration 6 5 4 6576-2 Table 4. Pin Function escriptions Pin No. Mnemonic escription 1 V Most Positive Power upply Potential. 2 GN Ground ( V) Reference. 3 V Most Negative Power upply Potential. 4 ource Terminal. Can be an input or output. 5 rain Terminal. Can be an input or output. 6 IN Logic Control Input. Table 5. AG121/AG122 Truth Table AG121 IN AG122 IN witch Condition 1 On 1 Off Rev. Page 6 of 16
TYPICAL PERFORMANCE CHARACTERITIC ON REITANCE (Ω) 2 18 16 14 12 1 8 6 T A = +25ºC V = +13.5V V = 13.5V V = +15V V = 15V V = +16.5V V = 16.5V ON REITANCE (Ω) 25 2 15 1 V = +15V V = 15V T A = 4 C T A = +125 C T A = +85 C T A = +25 C 4 5 ON REITANCE (Ω) 2 18 15 12 9 6 3 3 6 9 12 15 18 OURCE OR RAIN VOLTAGE (V) Figure 3. On Resistance as a Function of V (V) for ual upply 45 4 35 3 25 2 15 1 5 T A = +25 C V = +5.5V V = 5.5V 5 4 3 2 1 1 2 3 4 5 OURCE OR RAIN VOLTAGE (V) Figure 4. On Resistance as a Function of V (V) for ual upply 6576-3 6576-4 ON REITANCE (Ω) 15 1 5 5 1 15 OURCE OR RAIN VOLTAGE (V) Figure 6. On Resistance as a Function of V (V) for ifferent Temperatures, ual upply 6 5 4 3 2 1 V = +12V V = V T A = +85 C T A = 4 C T A = +25 C T A = +125 C 2 4 6 8 1 12 OURCE OR RAIN VOLTAGE (V) Figure 7. On Resistance as a Function of V (V) for ifferent Temperatures, ingle upply 6576-6 6576-7 ON REITANCE (Ω) 45 4 35 3 25 2 15 1 5 T A = 25 C V = 1.8V V = V V = 13.2V V = V V = 12V V = V 2 4 6 8 1 12 OURCE OR RAIN VOLTAGE (V) 6576-5 LEAKAGE CURRENT (pa) 2 15 1 5 5 1 15 2 25 3 35 4 V = +15V V = 15V V BIA = ±1V I (OFF) + I (OFF) + I (OFF) + I (OFF) + I, I (ON) + + I, I (ON) 45 2 4 6 8 1 12 TEMPERATURE (ºC) 6576-28 Figure 5. On Resistance as a Function of V (V) for ingle upply Figure 8. Leakage Currents as a Function of Temperature, ual upply Rev. Page 7 of 16
LEAKAGE CURRENT (pa) 15 1 5 5 1 15 V = +5V V = 5V V BIA = ±4.5V I (OFF) + I (OFF) + 2 I (OFF) + I (OFF) + I, I (ON) + + I, I (ON) 25 2 4 6 8 1 12 TEMPERATURE (ºC) Figure 9. Leakage Currents as a Function of Temperature, ual upply 6576-26 CHARGE INJECTION (pc).5.4.3.2.1.1.2.3.4 T A = 25ºC V = +15V V = 15V V = +5V V = 5V V = 12V V = V.5 15 1 5 5 1 15 INPUT VOLTAGE (V) Figure 12. Charge Injection vs. ource Voltage 6576-22 3 25 2 V = 12V V = V V BIA = 1/1V 3 25 15V t OFF 15V t ON 12V t OFF 12V t ON LEAKAGE CURRENT (pa) 15 1 5 5 TIME (ns) 2 15 1 1 I (OFF) + I (OFF) + 15 I (OFF) + I (OFF) + I, I (ON) + + I, I (ON) 2 2 4 6 8 1 12 TEMPERATURE (ºC) 6576-27 5 4 2 2 4 6 8 1 12 TEMPERATURE (ºC) 6576-23 Figure 1. Leakage Currents as a Function of Temperature, ingle upply Figure 13. TON/TOFF Times vs. Temperature 12 1 I PER CHANNEL T A = 25ºC 2 V = 15V V = 15V T A = 25ºC I (µa) 8 6 4 V = +15V V = 15V OFF IOLATION (db) 4 6 8 2 V = 12V V = V 2 4 6 8 1 12 14 LOGIC LEVEL, INx (V) 6576-21 1 12 1k 1k 1M 1M 1M FREQUNCY (Hz) 1G 6576-16 Figure 11. I vs. Logic Level Figure 14. Off Isolation vs. Frequency Rev. Page 8 of 16
6 INERTION LO (de) 2 4 6 8 1 V = 15V V = 15V T A = 25ºC CAPACITANCE (pf) 5.5 5 4.5 4 3.5 3 OURCE/RAIN ON RAIN OFF V = 12V V = V T A = 25ºC 12 14 1k 1k 1M 1M 1M 1G 6576-17 2.5 OURCE OFF 2 2 4 6 8 1 12 6576-19 FREQUNCY (Hz) INPUT VOLTAGE (V) Figure 15. On Response vs. Frequency Figure 18. Capacitance vs. Input Voltage, ingle upply 1 LOA = 1kΩ T A = 25 C 1 2 V = +15V V = 15V Vp-p =.63V T A = 25ºC NO ECOUPLING CAP ON 1 3 TH + N (%).1 V = +5V, V = 5V, V = +3.5V rms V = +15V, V = 15V, V = +5V rms ACPRR (db) 4 5 6 7 ECOUPLING CAP ON 8.1 1 1 1k 1k 1k FREQUENCY (Hz) Figure 16. TH + N vs. Frequency 6576-24 9 1 1k 1M 1M FREQUENCY (Hz) Figure 19. ACPRR vs. Frequency 6576-25 1M 6 5.5 5 V = 15V V = 15V T A = 25ºC CAPACITANCE (pf) 4.5 4 3.5 OURCE/RAIN ON 3 RAIN OFF 2.5 OURCE OFF 2 15 1 5 5 1 15 INPUT VOLTAGE (V) Figure 17. Capacitance vs. Input Voltage, ual upply 6576-18 Rev. Page 9 of 16
TET CIRCUIT V.1µFV.1µF V V NETWORK ANALYZER I IN 5Ω 5Ω V V1 V IN GN R L 5Ω V OUT V R ON = V1/I 6576-8 OFF IOLATION = 2 LOG V OUT V 6576-13 Figure 2. On Resistance Figure 23. Off Isolation V.1µFV.1µF V V NETWORK ANALYZER IN 5Ω V I (OFF) A I (OFF) A V IN GN R L 5Ω V OUT V Figure 21. Off Leakage V 6576-9 INERTION LO = 2 LOG V OUT WITH WITCH V OUT WITHOUT WITCH Figure 24. Bandwidth 6576-14 V.1µFV.1µF V V AUIO PRECIION R NC NC = NO CONNECT I (ON) A V 6576-1 V IN IN GN R L 1kΩ V OUT V V p-p 6576-15 Figure 22. On Leakage Figure 25. TH + Noise Rev. Page 1 of 16
V.1µFV.1µF V V V IN AG121 5% 5% V IN R L 3Ω V OUT C L 35pF V IN V OUT AG122 5% 5% 9% 9% GN t ON t OFF 6576-11 Figure 26. witching Times V V R V V V OUT V IN AG121 ON OFF V IN C L 1nF V IN AG122 GN V OUT Q INJ = C L ΔV OUT ΔV OUT 6576-12 Figure 27. Charge Injection Rev. Page 11 of 16
TERMINOLOGY I The positive supply current. I The negative supply current. V (V) The analog voltage on Terminal and Terminal. RON The ohmic resistance between and. RFLAT(ON) Flatness is defined as the difference between the maximum and minimum value of on resistance, as measured over the specified analog signal range. I (Off) The source leakage current with the switch off. I (Off) The drain leakage current with the switch off. I, I (On) The channel leakage current with the switch on. VINL The maximum input voltage for Logic. VINH The minimum input voltage for Logic 1. IINL (IINH) The input current of the digital input. C (Off) The off switch source capacitance, measured with reference to ground. C (Off) The off switch drain capacitance, measured with reference to ground. C, C (On) The on switch capacitance, measured with reference to ground. CIN The digital input capacitance. ton The delay between applying the digital control input and the output switching on. ee Figure 26. toff The delay between applying the digital control input and the output switching off. ee Figure 26. Charge Injection A measure of the glitch impulse transferred from the digital input to the analog output during switching. Off Isolation A measure of unwanted signal coupling through an off switch. Crosstalk A measure of unwanted signal that is coupled through from one channel to another as a result of parasitic capacitance. Bandwidth The frequency at which the output is attenuated by 3 db. On Response The frequency response of the on switch. Insertion Loss The loss due to the on resistance of the switch. TH + N The ratio of the harmonic amplitude plus noise of the signal to the fundamental. ACPRR (AC Power upply Rejection Ratio) Measures the ability of a part to avoid coupling noise and spurious signals that appear on the supply voltage pin to the output of the switch. The dc voltage on the device is modulated by a sine wave of.62 V p-p. The ratio of the amplitude of signal on the output to the amplitude of the modulation is the ACPRR. Rev. Page 12 of 16
OUTLINE IMENION 2.9 BC 6 5 4 1.6 BC 2.8 BC 1 2 3 PIN 1 INICATOR.95 BC 1.3 1.15.9 1.9 BC.15 MAX.5.3 1.45 MAX EATING PLANE.22.8 1 4.6.45.3 COMPLIANT TO JEEC TANAR MO-178-AB Figure 28. 6-Lead mall Outline Transistor Package [OT-23] (RJ-6) imensions shown in millimeters ORERING GUIE Model Temperature Range Package escription Package Option Branding AG121BRJZ-R2 1 4 C to +125 C 6-Lead mall Outline Transistor Package [OT-23] RJ-6 25 AG121BRJZ-REEL7 1 4 C to +125 C 6-Lead mall Outline Transistor Package [OT-23] RJ-6 25 AG122BRJZ-R2 1 4 C to +125 C 6-Lead mall Outline Transistor Package [OT-23] RJ-6 26 AG122BRJZ-REEL7 1 4 C to +125 C 6-Lead mall Outline Transistor Package [OT-23] RJ-6 26 1 Z = RoH Compliant Part. Rev. Page 13 of 16
NOTE Rev. Page 14 of 16
NOTE Rev. Page 15 of 16
NOTE 28 Analog evices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 6576--2/8() Rev. Page 16 of 16