CHAPTER 3 DESIGN OF PIPELINED ADC USING SCS-CDS AND OP-AMP SHARING TECHNIQUE

CHAPTER 3 DESIGN OF PIPELINED ADC USING SCS-CDS AND OP-AMP SHARING TECHNIQUE 3.1 INTRODUCTION An ADC is a device which converts a continuous quantity into discrete digital signal. Among its types, pipelined ADC is a popular architecture which achieves high speed, high resolution while maintaining better area efficiency and low power consumption. The techniques used in this architecture are split-capacitor sharing Correlated Double Sampling (SCS-CDS) and op-amp sharing technique to reduce power consumption. Programmable Gain Amplifier (PGA) (Huy-Hieu et al. 2009) is integrated with first stage of ADC to reduce double loading problem. 3.2 ARCHITECTURE OF THE PIPELINED ADC USING SCS-CDS AND OP-AMP SHARING TECHNIQUE Each stage of the pipelined ADC considered in this investigation includes a 1.5b/stage sub ADC and a Multiplying DAC (MDAC). Figure 3.1 shows the architecture of pipelined ADC which uses SCS-CDS in first four stages and op-amp sharing techniques in the remaining stages to reduce the power consumption. The last stage of pipelined ADC is 2-bit Flash ADC. 25

Figure 3.1 Architecture of 10-bit pipelined ADC with SCS CDS and op-amp sharing technique with its timing scheme 3.2.1 Sample and hold circuit Most pipelined ADCs have an on-chip sample and hold circuit in front of the pipeline stages to buffer the input signal. This front SHA circuit can give some isolation between the pipelined ADC and its driving circuit. So the driver suffers less kick-back noise from the comparators in the pipelined ADC. Two CMOS SHA architectures are used widely in the pipelined ADC design. The differential sample and hold circuit samples the input signal and gives two outputs. Two switches S1 and S2 samples the input signal. Figure 3.2 shows differential sample and hold circuit. Figure 3.2 Differential sample and hold circuit 26

3.2.2 Split Capacitor Sharing Correlated Double Sampling (SCS-CDS) technique The power techniques such as split capacitor sharing CDS technique are applied in the first four stages and op-amp sharing technique in the remaining stages. In order to perform power and area comparison the conventional split capacitor CDS technique is integrated with the op-amp sharing technique and all the analysis is done. The proposed technique is composed of a split capacitor sharing CDS technique in the first four stages and op-amp sharing technique in the remaining stages. Each stage of the 10-bit pipelined ADC has a 1-5-bit stage architecture to reduce the complexity. Normally, the accuracy requirement of the pipelined ADC is reduced to a great extent as the residue signal propagates through the pipeline stages. The op-amps mainly consume less power when op-amps are shared between two stages. 2-bit Flash ADC are used at the last stage and are scaled down and designed properly to reduce the power consumption and area when compared with the conventional technique. The digital outputs are provided to the digital correction logic which uses redundancy in order to remove offset errors in the comparator. In order to overcome the limitations of SC-CDS technique, a new SCS-CDS technique is proposed. In phase1, C F and C S are the main capacitors to sample the amplifying output from its previous stage. Therefore C F, C S and C 1 act as the main amplifying outputs corresponding to V inn. In Phase 2 the feedback capacitor C F is therefore split into C Fx,p and C Fy,p, and are connected in the feedback path. Here the residue value which is generated by the op-amp is not transferred to the sampling capacitor of the next stage. But, the residue signal is held on the two feedback capacitors C Fx,p and C Fy,p, which is split into equal halves. During the next phase of Φ1, the next residue signal is generated based on the stored value on the feedback capacitors and is transferred to the sampling capacitors of the following stage. The main advantage of the split capacitor 27

sharing CDS technique is that the capacitive load on the op-amp is reduced to a great extent. In addition, the charge on the feedback capacitors is reused in the following stage MDAC which in turn reduces the power consumption of the 10-bit pipelined ADC. The feedback capacitor is designed to complete the amplification of the predictive signal of stage1. Since the gain of the op-amp is boosted, the predictive output signal of the MDAC has low gain error. Normally the gain of the MDAC is determined by the capacitance ratio C S /C F. Therefore, careful design is made to overcome capacitance mismatch and also to eliminate the error which is generated in the residue output. The output voltage which is stored on the capacitance C 1 reduces the error voltage by reducing the voltage on the summing nodes (the capacitor C 1 connected between the negative input of the op-amp and the node that joins with the capacitance C F and C S ). In the proposed CDS technique the input-referred noise and the maximum output swing is reduced. Also the matching requirement of the capacitor is improved and the value of sample and feedback capacitor is properly designed in order to reduce the power consumption of 10-bit pipelined ADC. Since the clock phases are limited to two, this MDAC provides a speed improvement over other CDS techniques. Figure 3.3 shows the proposed Split capacitor sharing CDS technique. Figure 3.3 Proposed split capacitor sharing CDS technique 28

During the main sampling phase the sampling capacitor C S and the feedback capacitor C F are connected to the input signal V inn and sampling the input signal on the capacitors. During this sampling phase the total charge stored on both the capacitors C S and C F (Seung-Tak Rye et al. 2007) is ) (3.1) During the predictive amplification phase the feedback capacitor C F is connected with the output of the op-amp and the sampling capacitor C SP is connected with the V DACinp or with ground which depends on the output of a sub-adc. The total charge during this phase is (Seung-Tak Rye et al. 2007) (3.2) V - is the negative input of the op-amp and V DAC is the output signal of the Sub-Digital to Analog Converter (Sub-DAC).By equating equations (3.1) and (3.2) the output signal V out is obtained as(li J., Moon U.K., 2004) (3.3) C eq is called the equivalent capacitance which is equal to C Fx, P and C Fy, P. The feedback factor β determines how much the output voltage of op-amp is feedback to the op-amp input. The feedback factor is given as (Yunchiu et al.2004) (3.4) C s is known as sampling capacitance and C F is called as feedback capacitance. The DC gain of the op-amp is normally determined by equation (3.4). The error obtained by the op-amp gain should be less than ¼ LSB of the remaining resolution. The gain of the op-amp is boosted in order to reduce the op-amp gain error of the predictive signal in MDAC. 29

3.2.3 Op-amp sharing technique Since op-amps are the most important power-hungry analog circuits in the pipelined ADC, various op-amp sharing techniques (Krishnaswamy Nagaraj et al.1997) have been proposed to minimize the power consumption in the pipelined ADCs. During the sampling phase, the op-amp is not active, so that the op-amp is used for calculating the residue of the next stage. In this proposed 10-bit pipelined ADC, op-amp is shared between stages 5 and stages 6 and also between stages 7 and stages 8.Therefore, the number of operational amplifiers is reduced to a half and the op-amp operates only a half of a full clock cycle. During the first clock phase (Φ 1 ), the input signal is converted into 1.5 bits and also the residue signal of the op-amp is sampled on the capacitors. During the clock phase (Φ 2 ) the residue signal is calculated by the operational amplifier in the fifth stage. At the end of the phase the residue signal of the op-amp is obtained at V out.the V out signal is sampled by the sampling circuit of the next stage (Chun-Hsien Kuo et al. 2010). Figure 3.4 Op-amp sharing technique 30

If one op-amp is shared between two successive stages as shown in Figure 3.4 the power consumption of the pipelined ADC is significantly reduced. But there are certain drawbacks in the op-amp sharing technique. Since the op-amp is always active, the off-set voltage of the amplifier cannot be cancelled. Also the additional switches establish series resistance which in combination with the input capacitance affects the settling behavior of the stages. In order to overcome or reduce the effect of offset, the output of the fifth stage is connected to the input of the sixth stages of the 10-bit pipelined ADC with reverse polarity. Also the cross talk can be reduced by the introduction of additional switches. The transfer function of 1.5 bit per stage pipelined ADC is given by (Abo A.M. et al.1999) (3.5) Where C S and C F are the sampling and feedback capacitance, where both of the capacitance is assigned equal value to have a gain of two. Simulation results show that the total power obtained for the op-amp sharing technique is 2.56mW and the average power obtained is 509.0µW, where there is significant reduction in the power consumption. Hence the new architecture of the 10-bit pipelined ADC with split capacitor sharing CDS and op-amp sharing technique is suitable for wireless application. 31

3.2.4 Design of pseudo differential class-ab telescopic cascoded op-amp An operational amplifier is the most important block of analog systems, as it is the main contributor for the power consumption (Sima payami 2012). The SCS-CDS technique allows the correction of finite op-amp gain error of low-gain amplifiers. So only low -to-medium gain op-amps are employed in this technique. The need of telescopic cascode op-amp in this pipelined ADC is that, it has a better performance in terms of power consumption and bandwidth when compared with other operational amplifiers. Additionally the slew rate and speed of the op-amp is also improved by applying the pseudo-class-ab approach in a telescopic-cascode op-amp. Because of this reason, the telescopic op-amp is a better choice for low power consumption and low noise applications. In this op-amp, class-ab capacitors C 1 and C 2 are used to further more improve the bandwidth and the dc gain of the operational amplifier. The need to use pseudo differential class- AB telescopic cascoded op-amp is that the op-amp has less signal swing, less dynamic range which is further more compensated by the low noise factor. The telescopic op-amp is smaller than that of folded cascode Operational Transconductance Amplifier (OTA), since the tail transistor directly cuts into output swing from both sides of the operational amplifier. During the sampling phase the two capacitors are charged with the bias voltage of the PMOS and NMOS device. During the amplifying phase, the charge across the capacitor is very less and the PMOS current source is biased with a signal-dependent voltage. To ensure that the voltage across the level-shifting capacitor remains unchanged, the capacitor value is chosen larger than the parasitic capacitance at the gate node of the PMOS device. The equivalent transconductance G m of the amplifier is given by (Jin-Fu Lin 2010) (3.6) 32

The transconductance is proportional to the ratio of the parasitic capacitance of PMOS (C p ) and the class-ab capacitor (C 1 + C 2 ). The transconductance of the single stage op-amp is proportional to C L /t settling, where C L is the output loading and t settling is the settling time. For a supply voltage of 1.8V, an initial power budget of 1mW was allotted, which gives total biasing current of 0.5 ma. This is the total current from rail to rail which should be divided into two branches. Then 0.25mA was distributed between two branches of the telescopic op-amp. Generally, the overdrive of PMOS should be higher than NMOS as the mobility of PMOS is approx. 2.5 times less than NMOS. The overdrive voltage of PMOS is 270 mv and overdrive voltage of NMOS is 180 mv which is assigned after a careful analysis. Initial W/L values (in μm) can be chosen by using the current expression in saturation region operation. The initial values assumed for µ n *C ox is 150 µa/v 2 and µ p *C ox is 60 µa/v 2 for first iteration. The saturation region current expression is used to calculate the aspect ratios (W/L) of transistors as the current through them is known and overdrive voltage is assigned. The structure will improve the equivalent value of the stage transconductance leading to more gain and bandwidth for the op-amp. This is an important advantage of this structure. The maximum slew rate that can be obtained by the op-amp is given by (Rudyvande Plassche 2003). (3.7) Figure 3.5 shows the pseudo differential class - AB telescopic cascoded op-amp (Shylu et al. 2014). In this op-amp all transistors are biased in saturation region. Transistors M 1 - M 2, M 7 -M 8 have at least V dsat to offer good common mode rejection, frequency response and gain. 33

Figure 3.5 Pseudo differential class - AB telescopic cascoded op-amp with proposed CMFB circuit The switch is disconnected and assuming little charge leakage for the capacitor, the PMOS current source is biased with a suitable voltage that is signal-dependent as well. The capacitor value is chosen larger than the parasitic capacitance at the gate node of the PMOS device to make sure that the voltage across the level-shifting capacitor remains unchanged. The cascades are connected in series between the power supplies resulting in a structure in which the transistors in a branch are connected in a line, so the structure of the op-amp is called as telescopic. Here in the modified op-amp the gain is increased to 43 db when compared to the conventional op-amp. Figure 3.6 shows the AC response of the modified pseudo differential class-ab telescopic op-amp. Figure 3.7 shows the proposed external bias based common mode stabilization method. 34

Figure 3.6 AC response of modified pseudo differential class-ab telescopic op-amp Figure 3.7 Proposed external bias based common mode stabilization method using differential output op-amps 35

The basic purpose of common-mode stabilization is to maintain the common mode voltage half way between the limits of signal swing. This can be achieved by external common-mode feedback circuit. During the sampling phase, even though the differential gain of this circuit is two, the common mode gain of this MDAC is unity. This is because the two capacitor pairs C 2 and C 3 are connected with a floating switch (i.e. they are sampled without using a commonmode reference voltage).the common mode disturbance is transferred directly to the output without any amplification. In order to stabilize the common-mode output voltage external bias is used. Normally, the op-amp is used only during the amplification phase Φ 2.The common-mode input voltage is determined by CM bias node. During the phase Φ 1 the two capacitors named as C cm are charged to the output common-mode voltage, V cmbias. During this phase the common-mode output voltage V cmbias is connected to the CM bias. But during the phase Φ 2 the capacitors pair C cm are connected between the CM bias node and the differential outputs. In addition, the charge injection from the switches is also reduced. 3.2.5 Design of charge distribution dynamic comparator In high resolution A/D converters, precision comparators are used. However, the error from a large comparator offset in flash A/D section of pipeline ADC can be compensated with digital error correction technique. The power can be saved by using simple dynamic comparator in low resolution flash A/D converter instead of using a pre-amplifier comparator. Figure 3.8 shows the charge distribution dynamic comparator. The sub-adc in each 1.5 bits per stage consists of two fully differential comparators. Sub-ADC used is an important component of the pipelined stage. A 2 bits per stage flash ADC consists of 3 comparators. By using clk 2p, which falls earlier than clk 2, the bottom-plate sampling of reference voltage is done. When clk 1p goes high, the comparator s outputs are reset. When clk 1p goes low, the transistor Mc is turned on, and the outputs are generated by the positive feedback of M 3 -M 6. 36

In 1.5 bits per pipeline stage, there are two comparators. One generates a threshold voltage +V ref /4 and other generates a threshold voltage of -V ref /4. However the positions of the threshold voltages are interchanged to generate the threshold voltage of -V ref /4. The comparators are the major component of sub- ADC and flash ADC in pipelined ADC. Sub-ADC used in the design consists of 1.5 bits per stage. The digital outputs of 1.5 bits per stage are 00, 01 and 10 before digital error correction. VDD CLKLATCH CLKLATCH VOUTN VOUTP CLK1 CLK1 VIN N1 NO VINN CLK2 CLK1E CLK1E CLK2 VTHP VCOM VCOM VTHN CLKLATCH N2 Figure 3.8 Charge distribution dynamic comparator 3.3. PROPOSED 10-BIT PIPELINED ADC WITH PGA Each stage of the pipelined ADC includes a 1.5b/stage sub ADC and a Multiplying Digital-to-Analog-Converter (MDAC). Figure 3.9 shows the proposed architecture of the pipelined ADC with PGA which uses the SCS-CDS in first four stages and op-amp sharing techniques in the remaining stages to reduce the power consumption. The last stage of pipelined ADC is 2-bit flash ADC. The sub ADC resolves 2 bits from an input sample and the MDAC is 37

responsible for reconstructing these bits into analog sample, comparing it to the input sample, generating an error signal and amplifying the error signal to be applied to the next stage. Figure 3.9 Architecture of pipelined ADC with PGA integrated in the first stage To reduce power consumption Sample and Hold Amplifier (SHA) is avoided in the front end of the ADC. It uses low gain amplifiers and need two operating phases to avoid double loading problem. The speed increases due to two operating phases. By properly adjusting the operational amplifier transistor size (W/L), bias current and by scaling the capacitor sizes the power consumption of the pipelined ADC is significantly reduced. 3.4. RESULTS AND DISCUSSION In this work, a 10-bit low power pipelined ADC was designed in a 180nm CMOS process with a differential input signal of 1.6V pp, 2/20MHz input frequency, and the supply voltage of 1.8V. A merged split capacitor sharing CDS and op-amp sharing technique was used to reduce the power consumption of 38

pipelined ADC. A split-capacitor sharing CDS technique is used in pipelined ADC to overcome the double-loading problem of the time-aligned CDS technique. A modified class-ab pseudo differential telescopic op-amp was developed because of its high power efficiency (Shylu D.S. et al. 2012). The memory effect in the amplifier sharing MDAC is eliminated by using a differential input pair op-amp and adding additional clock resetting phase. By properly adjusting the operational amplifier transistor size (W/L), bias current and by scaling the capacitor sizes, the power consumption has been reduced significantly. 3.4.1 Sample and hold circuit The schematic of sample and hold circuit is shown in Figure 3.10. The amplitude of V in + is 0.8V. The amplitude of V in - is 0.8V. Figure 3.10 Schematic of sample and hold circuit 39

Figure 3.11 Output waveform of sample and hold circuit for 60MSPS Figure 3.11 and Figure 3.12 shows the transient response of sample and hold circuit for 60 MSPS and 100 MSPS. A sampling clock of time period 0.016μs gives a sampling rate of 60MSPS. A sampling clock of time period 0.01μs gives a sampling rate of 100MSPS. Figure 3.12 Output waveform of sample and hold circuit for 100MSPS 40

Figure 3.13 Settling time of fully differential sample and hold circuit Figure 3.13 shows the settling time of sample and hold circuit. The settling time is obtained as 6.62μs 6.392μs. So settling time is 0.2μs for the designed fully differential sample and hold circuit. The circuit consumes a power of 56μW. 3.4.2 Charge distribution type dynamic comparator The schematic of the comparator circuit is shown in Figure 3.14. The comparator circuit used is charge distribution type comparator which is suitable for pipelined ADCs. 41

Figure 3.14 Schematic of charge distribution type dynamic comparator Figure 3.15 Transient response of dynamic comparator Figure 3.15 shows the transient response of dynamic comparator. The inputs given to the comparator are analog in nature which is of 1.6V pp. The comparator compares the two inputs and if the positive input is greater than the negative input the output becomes logic1otherwise it becomes logic 0. 42

Figure 3.16 shows the power obtained for the comparator. The power obtained for the comparator circuit is 557.63872µw and an average power of 1.347 µw. Figure 3.16 Power obtained for dynamic comparator 3.4.3 Sub ADC The schematic of sub-adc is shown in Figure 3.17. The sub- ADC block is formed by using two comparators and a XNOR block. The inputs are given to the comparator circuit, and the digital outputs are obtained based on the difference in the inputs given to the comparators. Figure 3.17 Schematic of sub ADC 43

Figure 3.18 Transient response of sub - ADC Figure 3.18 shows the transient response of sub-adc. The sub - ADC converts the analog input to a digital value. Sub-ADC used in the design consists of 1.5 bits per stage. The digital outputs of 1.5 bits per stage are 00, 01 and 10 before digital error correction. After digital correction, digital outputs 00, 01, 10, 11 are produced. There is no digital code 11 before correction. Hence it is called 1.5 bits per stage. Sub- ADC requires only 2 comparators. One generates a threshold voltage +V ref /4 and other generates a threshold voltage of -V ref /3. The positions of the threshold voltages are interchanged to generate the threshold voltage -V ref /3, two outputs a MSB bit and a LSB bit. Figure 3.19 shows the power obtained of sub-adc. The sub-adc has a power consumption of 565.6387µm and an average power of 9.843 µm. Figure 3.19 Power obtained for sub-adc 44

3.4.4 Design and simulation of sub-dac Figure 3.20 shows the sub-dac. The control signals x, y, z generated by the sub-adc digital circuit is used to control the sub-dac to get the required analog output. The DAC-output follows the analog input. Fig 3.20 Circuit diagram of sub-dac Figure 3.21 Schematic of sub-dac 45

The DAC unit consists of a sub-adc and an XNOR gate. The schematic of the Sub-DAC is shown in Figure 3.21. Figure 3.22 Transient response of sub-dac Transient response of DAC unit is shown in Figure 3.22.The digital input is converted into an analog signal. Figure 3.23 shows the power consumption for DAC unit. The power obtained for the DAC unit is 619.3406µW and an average power of 126.7 µw. Figure 3.23 Power consumption obtained for DAC 46

3.4.5 Pseudo differential class-ab telescopic cascoded op-amp The schematic of telescopic cascoded op-amp is shown in Figure 3.24. Figure 3.25 shows the transient response of telescopic op-amp. The inputs Vin+ and Vin- are of 1.6 V pp and the outputs V o + and V o - have a peak to peak of 1.8V. Figure 3.24 Schematic of telescopic cascoded op-amp 3.25 Transient waveform of telescopic op-amp 47

The AC response of the operational amplifier is shown in Figure 3.26. It is observed that the dc gain of the pseudo differential class-ab telescopic operational amplifier is improved to 43.4147dB.The phase margin of the designed pseudo differential class-ab telescopic op-amp is 91.19747. The phase degree at which the dc gain becomes zero is known as the phase margin of an operational amplifier. Figure 3.26 AC response of pseudo differential class-ab telescopic op-amp Figure 3.27 shows the test circuit used for obtaining the CMRR and the slew rate. Figure 3.27 Op-amp test circuit 48

Figure 3.28 shows Common mode rejection ratio (CMRR) of op-amp. The CMRR of the operational amplifier obtained is 43.4dB. The value is almost equal to the dc gain of the operational amplifier. The CMRR of an op-amp is the rejection by the device of unwanted input signals common to both input leads, relative to the wanted difference signal. 43.4 db Figure 3.28 CMRR of op-amp Figure 3.29 Slew rate of op-amp The output waveform of the slew rate is shown in Figure 3.29. The maximum slew rate that can be obtained by the operational amplifier is given by, 2πV peak f max which is 2*3.14*1.6*10MHz. The theoretical value 49

obtained is 100.48V/µs. The slew rate of the pseudo differential op-amp is given by where is the tail current and is the load capacitance. The slew rate obtained is 165.4544V/µs. The slew rate can be a value greater than or equal to the maximum slew rate of an operational amplifier. Slew rate is defined as the maximum rate of change of output voltage per unit time and is expressed as volt per micro second. The settling time of an amplifier is the time elapsed from the application of an ideal instantaneous step input to the time at which the amplifier output has entered and remained within a specified error band, usually symmetrical about the final value. The settling time of the pseudo differential class-ab telescopic operational amplifier is 1.952 µs. Table 3.1 shows the performance summary of pseudo differential telescopic cascoded operational amplifier. Table 3.1 Performance summary of pseudo differential telescopic cascoded operational amplifier Parameters Technology Values 180nm Supply voltage 1.8V Input range 1.6Vpp Phase margin 91.19747 0 Unity gain bandwidth DC gain CMRR Slew rate 820.462MHz 43.4147dB 43.4dB 165.4544V/µs Settling time 1.952 µs 50

3.4.6 Op-amp sharing MDAC stage The schematic of the op-amp sharing MDAC is shown in Figure 3.30.The schematic shown is used for stage 5 and stage 6. Since the op-amp is used for both the stages, power consumption can be reduced for a certain limit (Beom-Soo Park et al. 2009) Figure 3.30 Schematic of op-amp sharing MDAC The output waveform obtained for the op-amp sharing MDAC stage is shown in Figure 3.31. The residue outputs of the stages are V outn and V outp. The power output obtained for the MDAC stage is shown in Figure 3.32. The total power obtained for the stage is 2.56862mW and the average power obtained is 509.0µW. Figure 3.31 Output waveform of op-amp sharing MDAC 51

2.56862mW Figure 3.32 Power consumption obtained for op-amp sharing MDAC 3.4.7 Flash ADC The schematic of Flash ADC is shown in Figure 3.33. Flash ADC is a type of analog to digital converter which consists of resistor ladder network along with to compare the input voltage to successive reference voltages (Beom-Soo Park et al. 2009). Often these reference ladders are constructed of many resistors. A Flash converter requires 2 n -1 comparators for an n-bit conversion. For a 2-bit Flash ADC, 3 comparators are required. Figure 3.33 Schematic of Flash ADC 52

Figure 3.34 Output waveform of Flash ADC Figure 3.34 shows the output waveform of Flash ADC. The power obtained for the Flash ADC circuit using the dynamic comparator is 1.77788µW and an average power of 33.85 µw. Figure 3.35 shows the power consumption of Flash ADC. 1.77788µW Figure 3.35 Power consumption of Flash ADC 53

3.4.8 Digital error correction logic Figure 3.36 shows the schematic of digital error correction logic circuit for the pipelined ADC with D flip-flops and full adders. 1.77788µW Figure 3.36 Schematic of digital error correction logic circuit Figure 3.37 shows the schematic of the full adder circuit for the digital error correction circuit. Figure 3.37 Schematic of full adder circuit 54

Figure 3.38 shows the output waveform of the full adder. Sum and carry outputs are obtained based on the inputs a, b and cin. Figure 3.38 Output of full adder circuit Figure 3.39 shows the schematic of the D flip-flop used in the digital error correction logic. Figure 3.39 Schematic of D flip-flop 55

Figure 3.40 Output of D flip-flop Figure 3.40 shows the output of D-flip-flop. Based on the clock input the output follows the input. 3.4.9 10-bit pipelined ADC Figure 3.41 shows the schematic of 10-bit pipelined ADC using SCS-CDS and op-amp sharing technique. All the sub blocks including Sub-ADC, Sub-DAC, Dynamic comparator, op-amp, Digital error correction logic and Flash ADC are integrated to form 10-bit pipelined ADC. Figure 3.41 Schematic of 10-bit pipelined ADC using SCS-CDS and op-amp sharing technique 56

The transient response for the 10-bit pipelined ADC is shown in Figure 3.42. The 10-bit digital output is obtained for the analog input voltage. The power consumption obtained for 10-bit pipelined ADC is shown in Figure 3.43. The power consumption obtained is 7.629mW. Figure 3.42 Transient response of 10-bit pipelined ADC 7.629 mw Figure 3.43 Power consumption of 10-bit pipelined ADC 57

Table 3.2 Power consumption obtained for sub-circuits Sub-circuits Total Power obtained Sample and hold 56µW Comparator 557.63872µW Sub ADC 565.6387µW DAC 619.3406 µw Op-amp sharing stage 2.56862mW Stage1 902.39 µw Flash ADC 1.77788mW 10-bit pipelined ADC 7.629mW The static performance of the pipelined ADC is given by the differential nonlinearity (DNL) and integral nonlinearity (INL) respectively. (3.8) The obtained differential nonlinearity (DNL) is illustrated in Figure 3.44. Figure 3.44 Obtained DNL 58

Figure 3.45 Obtained INL The obtained integral nonlinearity (INL) is illustrated in Figure 3.45. The DNL is within +0.31/-0.31 LSB, the INL is within +0.74/-0.74 LSB at 100 MSPS. Figure 3.46 FFT Spectrum of 10 bit pipelined ADC The obtained output Fast Fourier Transform (FFT) spectrum with a 20 MHz sinusoidal input at 1.8V and 100MSPS is plotted in Figure 3.46. The obtained the SFDR is about 62.9dB, the SNDR is about 56.15 db, Figure of 59

merit is 0.133pJ/step and ENOB is about 9.0343. The obtained dynamic performance versus input frequency is shown in Figure 3.47. In general, conversion time depends on the clock frequency and the resolution. In this design, since the clock frequency is 100MSPS and the resolution is 10 bit, the conversion time was found to be 1ns. The obtained dynamic performance versus MSPS of 100MSPS is shown in Figure 3.48. Conversion time can be calculated based on the equation (3.9) and it depends on clock frequency and resolution. (3.9) Figure 3.47 Obtained SNDR, SFDR and ENOB with input frequency (@ 100 MSPS) Figure 3.48 Obtained SNDR, SFDR and ENOB with MSPS (@f in =20 MHz) 60

The FOM of the proposed pipelined ADC is 0.133pJ/s. The equation for FOM is given below (Meganathan et al. 2009). 3.4.10 Layout area (3.10) A 10 bit pipelined ADC at 100 MSPS is designed using split-capacitor sharing correlated double sampling (SCS-CDS) and op-amp sharing technique to improve the performance of ADC. This architecture solves all the drawbacks of conventional CDS technique and reduces the power consumption. Simulation result shows that a new architecture of pipelined ADC consumes less power and therefore this pipelined ADC suitable for wireless applications. Figure 3.49 shows the layout of the designed 10-bit pipelined ADC. Figure 3.50 shows the layout of Programmable Gain Amplifier by using switched capacitor topology. The area obtained for the programmable gain amplifier using switched capacitor topology is 36.01*37.29=3142.81µm 2. Figure 3.49 Layout of the designed 10-bit pipelined ADC 61

Figure 3.50 Layout of programmable gain amplifier 3.4.11 Area of various sub-circuits using switched capacitor topology The area obtained for various sub-circuits is shown in Table 3.3. Table 3.3 Area obtained for various sub-circuits Name of the sub-circuits Area (mm 2 ) Sample and hold 0.00001835 Dynamic comparator 0.00003372 D flip-flop 0.0008591 Sub ADC 0.003429 Full adder 0.01178 2-bit Flash ADC 0.01478 Sub DAC 0.009011 Op-amp sharing stage 0.01115 SCS-CDS 0.0098 Digital error correction logic 0.074 PGA 0.0031 10-bit pipelined ADC 0.50225 62

Table 3.4 Performance summary of 10 bit pipelined ADC using SCS-CDS and op-amp sharing technique Parameters Power Supply Input Frequency Input Range Power consumption Power consumption with PGA Sampling rate DNL INL SFDR SNDR FOM ENOB Values 1.8 V 20 MHz 1.6Vpp 7.629mW 25.54mW 100 MSPS +0.31/-0.31 LSB +0.74/-0.74LSB 62.9 db 56.15dB 0.133pJ/step 9.03 bits Area 0.5031mm 2 Conversion Time 1ns Table 3.4 shows the performance comparison of the designed pipelined ADC with reported ADC and the performance comparison of the designed pipelined ADC with few reported ADC from literature is presented in Table 3.5. 63

Table 3.5 Performance comparison of the designed pipelined ADC with reported ADCs Reference Supply Voltage(V) Technology (nm) Resolution (bits) Sampling (MSPS) SFDR(dB) SNDR(dB) FOM pj/conv.step DNL/LNL (LSB) Power (mw) Area(mm 2 ) Li et al. (2002) 1.8 180 10 100 63.0 51.0 360 fj/ conv step -0.8/1.6 67.0 2.50 Kim et al. (2008) 1.8 180 10 100 70.0 56.2 0.59 0.48/0.95 31.0 1.28 Lin et al. (2010) Jin-Fu et al. (2010) 1.8 180 10 100 60.6 50.3 0.77 0.97/1,09 50.0 1.98 1.8 180 10 60 64.8 53.6 0.77 0.8/2/2 92.0 6.30 Megnathan et al. (2010) 1.8 180 10 50 89.0 59.8 1.10 +0.28/-0.17/ +0.42/-0.41 24.5 - Present work 1.8 180 10 100 62.9 56.15 0.13 +0.31/-0.31/ +0.74/-0.74 7.62 0.50 A 10 bit pipelined ADC at 100 MSPS is designed using a split-capacitor sharing correlated double sampling (SCS-CDS) technique and op-amp sharing technique to improve the performance of ADC. Simulation result shows that a new architecture of pipelined ADC with the integration of Split-Capacitor CDS and op-amp sharing technique consumes less power and therefore this pipelined ADC is suitable for wireless applications. 64

3.5 POST LAYOUT SIMULATION Pipelined ADC has various blocks such as sample and hold circuit, comparator, MDAC, sub-adc, sub-dac, op-amp, digital error correction circuit and Flash ADC. 3.5.1 Post layout simulation of 10-bit pipelined ADC Figure 3.51 show the Layout versus Schematic (LVS) of 10 bit pipelined ADC. Figure 3.52 shows the post layout simulation of 10-bit pipelined ADC using SCS-CDS technique. Figure 3.51 Layout versus schematic of 10- bit pipelined ADC 65

Figure 3.52 Post layout simulation of 10- bit pipelined ADC 3.6 SUMMARY This work describes a 10 bit 100MSPS low power pipelined analog to digital converter. This architecture employs split capacitor sharing CDS and opamp sharing MDAC circuits for power reduction. The sub circuits of various stages were integrated to form the single bit stage which was then cascaded to form the 10-bit pipelined ADC. A 2-bit Flash ADC used at the last stage of the 10-bit pipelined ADC was designed using a resistor divider branch and three clocked dynamic comparators. To correct the output of analog chain which generates 18 bits, delay elements and full adders are included, as the digital correction which generates the final 10 bit output. Simulation results show that there is 16% of power reduction with the proposed split capacitor sharing CDS technique in 10-bit pipelined ADC. Also the Layout Versus Schematic (LVS) and the post layout simulation of the proposed system have been completed and Graphical Data Stream Information Interchange (GDS-II) file was obtained. 66