ECE380 Digital Logic Implementation Technology: NMOS and PMOS Transistors, CMOS logic gates Dr. D. J. Jackson Lecture 13-1 Logic values as voltage levels V ss is the minimum voltage that can exist in the system. We will use V ss =0V. is the power supply voltage. We will use =+5V. =+3.3V is also common. Exact levels o V 0,max and V 1,min depend on the implementation technology V 1,min V 0,max V ss (Gnd) Logic value 1 Undeined Logic value 0 Dr. D. J. Jackson Lecture 13-2 1
Transistor switches Logic circuits are built with transistors We will assume a transistor operates as a simple switch controlled by a logic signal x The most popular type o transistor or implementing a simple switch is the metal oxide semiconductor ield eect transistor (MOSFET) Two types o MOSFETs N-channel (NMOS) P-channel (PMOS) Early circuits relied on NMOS or PMOS transistors, but not both Current circuits use both NMOS and PMOS transistors in a coniguration called complementary MOS (CMOS) Dr. D. J. Jackson Lecture 13-3 NMOS transistor as a switch x= low x= high A simple switch controlled by the input x Gate Source Drain Substrate (Body) NMOS transistor Simpliied NMOS symbol Dr. D. J. Jackson Lecture 13-4 2
NMOS transistor as a switch = low = high The transistor operates by controlling the voltage at the gate terminal I is low, there is no connection between the source and the drain terminals. The transistor is turned o. I is high, the transistor is turned on and acts as a closed switch between the source and drain terminals. Dr. D. J. Jackson Lecture 13-5 PMOS transistor as a switch x= high x= low A simple switch controlled by the input x Gate Drain V Substrate (Body) DD PMOS transistor Source Simpliied PMOS symbol Dr. D. J. Jackson Lecture 13-6 3
PMOS transistor as a switch = high = low The transistor operates by controlling the voltage at the gate terminal I is high, there is no connection between the source and the drain terminals. The transistor is turned o. I is low, the transistor is turned on and acts as a closed switch between the source and drain terminals. Dr. D. J. Jackson Lecture 13-7 NMOS and PMOS in logic circuits = 0 V NMOS transistor = 0 V = Closed switch when = Open switch when =0V PMOS transistor Open switch when = = Closed switch when =0V Dr. D. J. Jackson Lecture 13-8 4
NMOS and PMOS in logic circuits When the NMOS transistor is turned on, its drain is pulled down to Gnd When the PMOS transistor is turned on, its drain is pulled up to Because o the way transistors operate: An NMOS transistor cannot be used to pull its drain terminal completely up to A PMOS transistor cannot be used to pull its drain terminal completely down to Gnd Thereore, NMOS and PMOS transistors are commonly used in pairs in CMOS circuits Dr. D. J. Jackson Lecture 13-9 CMOS logic gates A CMOS logic gate involves NMOS transistors in a pull-down network (PDN) and PMOS transistors in a pull-up network (PUN) The unctions realized by the PDN and PUN networks are complements o one another The PDN and PUN have equal numbers o transistors, which are arranged so that the two networks are duals o one another Wherever the PDN has NMOS transistors in series, the PUN has PMOS transistors in parallel, and vice versa Dr. D. J. Jackson Lecture 13-10 5
CMOS logic gates For any given valuation o the input signals, either the PDN pulls down to Gnd or the PUN pulls up to Pull-up network (PUN) PMOS transistors V X1 V Xn Pull-down network (PDN) NMOS transistors Dr. D. J. Jackson Lecture 13-11 CMOS NOT gate T 1 V x T 2 0 1 1 0 x T1 T2 0 On O 1 1 O On 0 2 transistors Dr. D. J. Jackson Lecture 13-12 6
CMOS NAND gate T1 T2 X1 X2 T1 T2 T3 T4 0 0 On On O O 1 V X1 T3 0 1 On O O On 1 1 0 O On On O 1 V X2 T4 1 1 O O On On 0 4 transistors Dr. D. J. Jackson Lecture 13-13 CMOS NOR gate V X1 V X2 T1 T2 X1 X2 T1 T2 T3 T4 0 0 On On O O 1 0 1 On O O On 0 1 0 O On On O 0 T3 T4 1 1 O O On On 0 4 transistors Dr. D. J. Jackson Lecture 13-14 7
CMOS AND gate T1 T2 V X1 T3 V X2 T4 6 transistors Dr. D. J. Jackson Lecture 13-15 CMOS OR gate V X1 T1 V X2 T2 T3 T4 6 transistors Dr. D. J. Jackson Lecture 13-16 8
CMOS non-inverting buer x V x =x A non-inverting buer 4 transistors Dr. D. J. Jackson Lecture 13-17 CMOS transmission gate s s s x s x s 0 Z 1 x 2 transistors Dr. D. J. Jackson Lecture 13-18 9
CMOS tri-state buer e e x x e x 0 0 Z 0 1 Z 1 0 0 1 1 1 8 transistors Dr. D. J. Jackson Lecture 13-19 10