Two Dimensional Analytical Threshold Voltages Modeling for Short-Channel MOSFET Sanjeev kumar Singh, Vishal Moyal Electronics & Telecommunication, SSTC-SSGI, Bhilai, Chhatisgarh, India Abstract- The aim of this paper is to research the impact of physical parameters which characterize the MOSFET transistors structure on the threshold voltage value. It will also analyse the role of substrate (the body effect) of MOSFETs on the threshold voltage. The MOSFET threshold voltage value has influenced in the dynamic and static work regime (mode) of device. Based on the outcome obtained and further observe impact of each single physical parameter on the total value of threshold voltage. Besides it can be observe which of these parameters would have significant and small impact on the threshold voltage. Hence, considering set the values of MOSFET physical parameters to reach the accepted threshold voltage. In this paper an analytical model for threshold voltage of short-channel MOSFETs is purposed. For such devices, the depletion regions due to source/drain junctions occupy a large portion of the channel, and hence are very important for precise Analytical threshold voltage modeling. The proposed analytical model can calculate the threshold voltage variation drain induced barrier lowering (DIBL) effect and hence, the threshold voltage roll-off natures quite accurately. The model results are verified against the simulator MATLAB. 1.1 MOS (Metal Oxide Semiconductor) A MOS (Metal Oxide Semiconductor) diode is a structure where a thin layer of oxide is grown on top of semiconductor substrate, and after that, a metal layer is deposited on the oxide, as is shown in Figure. 1. In the MOS diode the voltage applied to the gate controls the state of the Si-surface underneath. There are two states of the MOS diode that can be used to make a voltage-controlled switch accumulation and inversion. The MOS diode is in an accumulation state when a negative gate voltage is applied, that attracts the holes from the p-type silicon to the surface; and in the inversion state when a positive voltage (larger than the threshold voltage) is applied, creating an inverted layer of electrons at the surface. The threshold voltage is the gate voltage when the channel just starts to form at the oxide-substrate interface. There are two modes of the switch: on and off that correspond to the existence or absence of the electron layer (the channel). Index Terms- MATLAB, DIBL, MOSFETs. I. INTRODUCTION This paper aims at developing Charge sharing model have been used to model the short-channel effects (SCEs). Two-dimensional analysis has accurately predicts the values of threshold voltage of short channel MOSFET s and breakdown voltage. In this chapter, the details of MOSFET s are presented along with the discussion for source of MOS gate and operating region of MOSFET of the thesis. In the next section, discuss various scaling approaches, the effect of scaling on initial device characteristics, the limits imposed by reliability concerns in scaled-down MOSFET technologies, techniques to control short channel effects and unconventional approaches to MOSFET scaling. Figure.1: Cross-section of a MOS diode [2]. When the gate voltage is below the threshold voltage there is no channel and the source and drain n+ regions are isolated by the p-type substrate. This is the off-mode of the switch. When the gate voltage is higher than the threshold voltage (on-mode) the current flows through the surface and the channel appears [1, 2]. IJIRT 102406 INTERNATIONAL JOURNAL OF INNOVATIVE RESEARCH IN TECHNOLOGY 304
1.2 TECHNOLOGY SCALING AND THRESHOLD VOLTAGE VARIATION With technology scaling, the MOSFET s channel length is reduced. As the channel length approaches the source-body and drain-body depletion widths, the charge in the channel due to these parasitic diodes become comparable to the depletion charge due to the MOSFET gate-body voltage [3], rendering the gate and body terminals to be less effective. As the band diagram illustrates in Figure 2, the finite depletion width of the parasitic diodes do not influence the energy barrier height to be overcome for inversion formation in a long channel device. However, as the channel length becomes shorter both channel length and drain voltage reduce this barrier height. This two dimensional effect makes the barrier height to be modulated by channel length variation resulting in threshold voltage variation as shown in Figure 2. The amount of barrier height lowering, threshold voltage variation, and gate and body terminal s channel control loss will directly depend on the charge contribution percentage of the parasitic diodes to the total channel charge. voltage variation due to random dopant fluctuation effect. Random dopant fluctuation effect is expected to be one of the significant sources of threshold voltage variation in devices of small area [4]. II. CALCULATION OF THRESHOLD VOLTAGE 2.1 CALCULATION OF THRESHOLD VOLTAGE FOR NMOS WITH LONG-CHANNEL To calculate the threshold voltage we must consider physical parameters of MOSFET structure which have the impact in value of the threshold voltage by considering the various components of Vt(when VSB = 0V, the threshold voltage will indicate V t0 ). For practical purposes, we can identify four physical components of the threshold voltage: the work function difference between the gate and channel (Φ GC ), the gate voltage component to change the surface potential (-2F), the gate voltage component to offset the deletion region charge of the fixed acceptor ions near surface (-Q B /C Ox ) and gate voltage component to offset the fixed charges in the gate oxide and in silicon oxide interface (-Qox/Cox) [5, 6].Now, we combine all of these voltage components to find the threshold voltage. For zero substrate, bias voltage (VSB = 0V) will have this expression [5, 6]: Φ (1) Where: Φ (2) (3) Figure 2: Barrier height lowering due to channel length reduction and drain voltage increase in an nmosfet. It is essential to mention that in sub-micron technologies variation in several physical and process parameters lead to variation in the electrical behavior of the MOS device. The discussions in this thesis will address variation in the electrical behavior manifested as threshold voltage variation because of parameter variation. In addition, the threshold voltage variations addressed here are due to short channel effect in scaled MOS devices and not on threshold (4) For nonzero substrate bias voltage (VSB> 0), the depletion charge density term must be modified [25, 26] as: (5) Now the generalized form of threshold voltage will be: (6) Φ IJIRT 102406 INTERNATIONAL JOURNAL OF INNOVATIVE RESEARCH IN TECHNOLOGY 305
(7) - Is the body-effect parameter. Where: Φ F - the substrate Fermi potential, q- Electron charge, Si dielectric constant of silicon (Si), Q B the depletion region charge density at surface inversion ( S = F ), C ox the gate oxide capacitance per unit area. Based in acquired values at Fig.3 and Fig.4 is represented dependence of the threshold voltage Vt0 (when source and body have same potential) on thickness of oxide layer tox, for parametric values of substrate doping density NA and oxide-interface fixed charge density Nox. Figure 4 the dependence of the threshold voltage Vt0 on thickness of oxide layer tox for parametric values of substrate doping density NA, when Nox= 1010cm- 2. [7] Figure 3 Threshold voltage Vt0 on thickness of oxide layer t ox for parametric values of oxide-interface fixed charge density N ox, when N A = 10 16 cm -3 [8]. From Figure 3 and Figure 4based on acquired values we can see influence of t ox, N A and N ox in values of threshold voltage. For larger value of each parameter: t ox, or N A the value of threshold voltage will increase. But for larger value of N ox the value of threshold voltage will decrease, which is not significant. Influence of substrate bias voltage (the body effect) on the threshold voltage is shown in Figure 6 Figure 5 shows dependence of threshold voltage on the polarization voltage VSB for which results the higher values of the threshold voltage for higher value of VSB in comparison with Vt0 (as in case of integrated circuits). Figure 5 Variation of the threshold voltage V t as a function of the source-to-substrate (V SB ) voltage for parametric values of thickness oxide layers t ox, when N A = 10 16 cm -3 and N ox = 4*10 10 cm -3 [2,8]. 2.2 CALCULATION OF THRESHOLD VOLTAGE OF NMOS WITH NARROW-CHANNEL: A MOSFET transistor is defined as a narrow-channel device if its channel width is on the same order of magnitude as the maximum depletion regions thickness into the substrate (xdm). This effect will have influence in the threshold voltage and results in higher value for OV t0 if compared with long-channel device [25, 26]. Vt0(narrow-channel)=Vt0+ΔVt0 (8) (9) In Figure 6 is shown the dependence of voltage term ΔV t on the channel width and we can say: when W x dm the IJIRT 102406 INTERNATIONAL JOURNAL OF INNOVATIVE RESEARCH IN TECHNOLOGY 306
ΔV t term will have influence in the increase of the total Figure 6 The dependence of ΔV t0 on channel width (W) for parametric values of N A, when N D = 10 18 cm - 3 and t ox = 20 nm [1,8]. threshold voltage, while W >>x dm the ΔV t term is not significant. 2.3 CALCULATION OF THRESHOLD VOLTAGE OF NMOS WITH SHORT CHANNEL: A MOSFET transistor is defined as a short-channel device if its channel length is on the same order of magnitude as the depletion regions thicknesses of source and drain junction. Otherwise MOSFET can be defined as a short-channel device if effective channel length L eef is approximately equal to the S and D junction depth x j, Figure 7. When NMOS is defined as a short-channel device the length of channel will have impact on the threshold voltage. A short-channel will reduce the threshold voltage of ΔV t compare with long-channel device [5, 6, 9, and 10]. V t0(short-channel) =V t0 +ΔV t0 (10) Let ΔLS and ΔLD represent the lateral extend of the depletion regions associated with the source junction and the drain junction, as in Fig 8. Then, the bulk depletion region charge contained within the trapezoidal region is: Δ Δ (11) Figure 7 Simplified geometry of the MOSFET channel region, with gate-induced bulk depletion region and the pn-junction depletion regions. (b) Close-up view of the drain diffusion edge. -x ds, x dd represent the depth of depletion regions at source and drain as results of pn- junction, respectively. Influence of the length channel L, the depth xj of drain (source) regions and drain-to-source voltage (V DS ) on the voltage term ΔV t0, are shown in Figure 7, Figure 8 and Figure 9. After calculation the ΔLS and ΔLD, the amount of threshold voltage reduction ΔVt0 can be found as [5, 9]: (12) Figure 8 The dependence of the ΔV t0 on the length L for parametric values of depth xj, when N A = 10 16 cm - 3, N D = 10 18 cm -3, t ox = 20 nm and V DS = 0V. IJIRT 102406 INTERNATIONAL JOURNAL OF INNOVATIVE RESEARCH IN TECHNOLOGY 307
Figure 9 The dependence of the ΔV t0 on N D (source and drain doping density), when N A =10 16 cm -3, L=1μm, t ox =20nm, xj=1μm and V DS =0 V[13]. Based in acquired values which are represented in Fig.8, Fig.9 and Fig.10, for L xj the ΔV t0 will have influence in reduction of the threshold voltage Vt0. While if L >>x j the ΔV t0 is not significant, the NMOS is defined as long-channel device. The increase the value of parameters NA and x j will have small influence in term of the threshold voltage ΔV t0. The V DS voltage will have significant influence in the term ΔV t0, which results in larger value for higher value of V DS. Figure 11 Electron and hole mobilizes in silicon at room temperature plotted as function of impurity concentration. Figure 10 The dependence ofδv t0 on V DS voltage, when N A = 10 16 cm -3, N D = 10 18 cm -3, tox = 20 nm, xj = 1 μm and L = 0.7 μm [13]. The threshold voltage of this short-channel MOS transistor is calculated as VT0 = 0.855V - Δ VTO Figure 12 Variation of the charges (Q i, Q B, Q S ) of MOS along the surface potential. III. RESULTS AND DISCUSSION The threshold voltage of this short-channel MOS transistor is calculated as VT0 = 0.855V - Δ VTO IJIRT 102406 INTERNATIONAL JOURNAL OF INNOVATIVE RESEARCH IN TECHNOLOGY 308
increases the threshold voltage in MOSFET The channel potential profile is dependent on the difference between gate material work-functions and the length of gate. The threshold voltage roll-off along the channel length is plotted for different drain to source voltage and threshold voltage roll-off is minimum for the thinnest silicon body REFERENCES Figure 13 Variation of the threshold voltage along the channel length for different drain to source voltage ( Vds =1V, Vds =3 V, Vds = 5 V) Figure: 14 Variation of threshold voltage reduction with Channel Length. IV. CONCLUSION From the comparisons of the results with MATLAB, it can be concluded that the proposed analytical approach has the accuracy of near two dimensional numerical results. The model includes the effect of various MOS parameters like body doping concentration, applied drain and substrate biases, the thicknesses of thin silicon film, front gate oxide and back gate air. An increase in channel doping [1] Sima Dimitrijev, Principles of Semiconductor Devices, ISBN-10: 0195161130, ISBN-13: 978-0195161137, Oxford University Press, USA, p. 578, 2005. [2] Andrey Prokhorov and Olesya Gerzheva, Model of MOSFET in Delphi, Technical report, SIC and Electrical Engineering IDE1066, February 2011. [3] H.C. Poon, L.D. Yau, R.L. Johnston, D. Beecham, DC Model for Short-Channel IGFET's, Intl. Electron Devices Meeting, pp. 156-159, Dec. 1973. [4] A. Asenov, G. Slavcheva, A.R. Brown, J.H. Davies, and S. Saini, Increase in the Random Dopant Induced Threshold Fluctuations and Lowering in Sub-100 nm MOSFETs due to Quantum Effects: A 3-D Density-Gradient Simulation Study, IEEE Transactions on Electron Devices, vol. 48, no. 4, pp. 722-729, April 2001. [5] Kang, S. M. and Y. Leblebici, CMOS Digital Integrated Circuits, 3th edition, McGraw-Hill, 2003 [6] Tsividis, Y. P., Operation and Modelling of the MOS Transistor, New York: Oxford University Press, 1999. [7] S. Wolf, Microchip Manufacturing, Lattice Press, 2004. [8] Milaim Zabeli, Nebi Caka, Myzafere Limani and Qamil Kabashi, The impact of MOSFET s physical parameters on its threshold voltage" Proceedings of the 6th WSEAS International Conference on Microelectronics, Nano-electronics, Optoelectronics, Istanbul, Turkey, May 27-29, 2007. [9] Neamen, D. A. Electronic Circuit Analysis and Design, 2nd edition, New York: McGraw-Hill, 2001. [10] Sedra, A. C. and K. C. Smith, Microelectronic Circuits, 5th edition, Oxford University Press, 2004. [11] A. Benfdila, and F.Balestra, On the drain current saturation in short channel MOSFETs, Microelectronics Journal, vol. 37, pp. 635-641, 2006. IJIRT 102406 INTERNATIONAL JOURNAL OF INNOVATIVE RESEARCH IN TECHNOLOGY 309
[12] Wikipedia Encyclopedia <http://www.wikipedia.org>. [13] Sima Dimitrijev, Principles of Semiconductor Devices, ISBN-10: 0195161130, ISBN-13: 978-0195161137, Oxford University Press, USA, p. 578, 2005. [14] Andrey Prokhorov and Olesya Gerzheva, Model of MOSFET in Delphi, Technical report, SIC and Electrical Engineering IDE1066, February 2011 [15] Narain Arora, MOSFET Modeling for VLSI Simulation: Theory and Practice, ISBN-13: 978-981-256-862-5, ISBN-10: 981-256-862-X, World Scientific Publishing Co. Pte. Ltd., Singapore, p. 632, 2007. [16] G. E. Moore, Cramming more components onto integrated circuits, Electronics, Vol. 38, number 8, April 19, 1965. IJIRT 102406 INTERNATIONAL JOURNAL OF INNOVATIVE RESEARCH IN TECHNOLOGY 310