AD7 Bit, Multiplying D/A Converter OBSOLETE PRODUCT POSSIBLE SUBSTITUTE PRODUCT AD7 DATASHEET FN07 Rev..00 The AD7 is a monolithic, low cost, high performance, bit accurate, multiplying digitaltoanalog converter (DAC). Intersil wafer level lasertrimmed thinfilm resistors on CMOS circuitry provide true bit linearity with TTL/CMOS compatible operation. Special tabbedresistor geometries (improving time stability), full input protection from damage due to static discharge by diode clamps to V and ground, large and bus lines (improving superposition errors) are some of the features offered by Intersil AD7. Features Bit Linearity 0.0% Pretrimmed Gain Low Gain and Linearity Tempcos Full Temperature Range Operation Full Input Static Protection TTL/CMOS Compatible V to V Supply Range 0mW Low Power Dissipation Current Settling Time s to 0.0% of FSR Four Quadrant Multiplication Pinout AD7 (PDIP) TOP VIEW Functional Block Diagram IN 0k 0k 0k 0k (7) 8 R FEEDBACK 0k 0k 0k 0k 0k 0k 7 IN V () BIT BIT BIT BIT 7 8 BIT (LSB) BIT BIT 0 BIT 9 BIT 8 SPDT NMOS SWITCHES MSB () BIT BIT () () 0k () () R FEEDBACK (8) BIT 9 0 BIT 7 NOTE: Switches shown for digital inputs High. Part Number Information PART NUMBER NONLINEARITY TEMP. RANGE ( o C) PACKAGE PKG. NO. AD7JN 0.0% (Bit) 0 to 70 8 Ld PDIP E8. AD7KN 0.0% (Bit) 0 to 70 8 Ld PDIP E8. FN07 Rev..00 Page of 8
AD7 Absolute Maximum Ratings Supply Voltage (V to ).......................... 7V............................................ V Digital Input Voltage Range....................... V to Output Voltage Compliance..................... 00mV to V Operating Conditions Temperature Range........................... 0 o C to 70 o C Thermal Information Thermal Resistance (Typical, Note ) JA ( o C/W) PDIP Package............................. 80 Maximum Junction Temperature.......................0 o C Maximum Storage Temperature............... o C to 0 o C Maximum Lead Temperature (Soldering 0s).............00 o C CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE:. JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB79 for details. Electrical Specifications V = V, = 0V, = = 0V, T A = o C, Unless Otherwise Specified T A = o C T A MINMAX PARAMETER TEST CONDITIONS MIN TYP MAX MIN MAX UNITS SYSTEM PERFORMANCE (Note ) Resolution Bits Nonlinearity J 0V 0V 0.0 0.0 % of FSR K = = 0V See Figure (Note ) 0.0 0.0 % of FSR Monotonicity Guaranteed Gain Error 0V 0V (Note ) 0. 0. % of FSR Output Leakage Current (Either Output) = = 0 0 00 na DYNAMIC CHARACTERISTICS Power Supply Rejection V =.V to.v See Figure (Note ) 0.00 0.0 % of FSR/% of V Output Current Settling Time Feedthrough Error REFERENCE INPUTS Input Resistance ANALOG OUTPUT Voltage Compliance To 0.% of FSR See Figure 9 (Note ) = 0V PP, 0kHz All Digital Inputs Low See Figure 8 (Note ) All Digital Inputs High at Ground Both Outputs, See Maximum Ratings (Note 7) s mv PP 0 0 0 k 00mV to V Output Capacitance C OUT All Digital Inputs High 00 00 pf See Figure 7 (Note ) C OUT 0 0 pf C OUT All Digital Inputs Low 0 0 pf See Figure 7 (Note ) C OUT 00 00 pf Output Noise (Both Outputs) See Figure Equivalent to 0k Johnson Noise FN07 Rev..00 Page of 8
AD7 Electrical Specifications V = V, = 0V, = = 0V, T A = o C, Unless Otherwise Specified (Continued) T A = o C T A MINMAX PARAMETER TEST CONDITIONS MIN TYP MAX MIN MAX UNITS DIGITAL INPUTS Low State Threshold, V IL (Notes, ) 0.8 0.8 V High State Threshold, V IH.. V Input Current V IN = 0V or V (Note ) A Input Coding See Tables and (Note ) Binary/Offset Binary Input Capacitance (Note ) 8 8 pf POWER SUPPLY CHARACTERISTICS Power Supply Voltage Range Accuracy Is Not Guaranteed Over This Range to V I All Digital Inputs High or Low (Excluding Ladder Network).0. ma Total Power Dissipation (Including Ladder Network) 0 mw NOTES:. The digital control inputs are zener protected; however, permanent damage may occur on unconnected units under high energy electrostatic fields. Keep unused units in conductive foam at all times.. Do not apply voltages higher than V DD or less than potential on any terminal except and R FEEDBACK.. Full scale range (FSR) is 0V for unipolar and 0V for bipolar modes.. Using internal feedback resistor, R FEEDBACK.. Guaranteed by design or characterization and not production tested. 7. Accuracy not guaranteed unless outputs at ground potential. Definition of Terms Nonlinearity: Error contributed by deviation of the DAC transfer function from a best fit straight line function. Normally expressed as a percentage of full scale range. For a multiplying DAC, this should hold true over the entire range. Resolution: Value of the LSB. For example, a unipolar converter with n bits has a resolution of LSB = ( )/ N. A bipolar converter of N bits has a resolution of LSB = ( )/ (N). Resolution in no way implies linearity. Settling Time: Time required for the output function of the DAC to settle to within / LSB for a given digital input stimulus, i.e., 0 to Full Scale. Gain Error: Ratio of the DAC s operational amplifier output voltage to the nominal input voltage value. Feedthrough Error: Error caused by capacitive coupling from to output with all switches OFF. Output Capacitance: Capacitance from, and terminals to ground. Output Leakage Current: Current which appears on, terminal when all digital inputs are LOW or on terminal when all inputs are HIGH. Detailed Description The AD7 is a bit, monolithic, multiplying D/A converter. A highly stable thin film RR resistor ladder network and NMOS SPDT switches form the basis of the converter circuit. CMOS level shifters provide low power TTL/CMOS compatible operation. An external voltage or current reference and an operational amplifier are all that is required for most voltage output applications. A simplified equivalent circuit of the DAC is shown on page, (Functional Diagram). The NMOS SPDT switches steer the ladder leg currents between and buses which must be held at ground potential. This configuration maintains a constant current in each ladder leg independent of the input code. Converter errors are further eliminated by using wider metal interconnections between the major bits and the outputs. Use of high threshold switches reduces the offset (leakage) errors to a negligible level. Each circuit is lasertrimmed, at the wafer level, to better than bits linearity. For the first four bits of the ladder, special trimtabbed geometries are used to keep the body of the resistors, carrying the majority of the output current, undisturbed. The resultant time stability of the trimmed circuits is comparable to that of untrimmed units. The level shifter circuits are comprised of three inverters with a positive feedback from the output of the second to first FN07 Rev..00 Page of 8
AD7 (Figure ). This configuration results in TTL/COMS compatible operation over the full military temperature range. With the ladder SPDT switches driven by the level shifter, each switch is binary weighted for an ON resistance proportional to the respective ladder leg current. This assures a constant voltage drop across each switch, creating equipotential terminations for the R ladder resistor, resulting in accurate leg currents. V TTL/CMOS INPUT Typical Applications General Recommendations Static performance of the AD7 depends on and (pin and pin ) potentials being exactly equal to (pin ). The output amplifier should be selected to have a low input bias current (typically less than 7nA), and a low drift (depending on the temperature range). The voltage offset of the amplifier should be nulled (typically less than 00 V). The bias current compensation resistor in the amplifier s noninverting input can cause a variable offset. Noninverting input should be connected to with a low resistance wire. Groundloops must be avoided by taking all pins going to to a common point, using separate connections. The V (pin ) power supply should have a low noise level and should not have any transients exceeding 7V. Unused digital inputs must be connected to or V for proper operation. A high value resistor (~M ) can be used to prevent static charge accumulation, when the inputs are opencircuited for any reason. When gain adjustment is required, low tempco (approximately 0ppm/ o C) resistors or trimpots should be selected. Unipolar Binary Operation The circuit configuration for operating the AD7 in unipolar mode is shown in Figure. With positive and negative values the circuit is capable of Quadrant multiplication. The Digital Input Code/Analog Output Value table for unipolar mode is given in Table. A Schottky diode (HP088 or equivalent) prevents from negative excursions which 7 TO LADDER 8 9 FIGURE. CMOS LEVEL SHIFTER AND SWITCH could damage the device. This precaution is only necessary with certain high speed amplifiers. 0V DIGITAL INPUT BIT (LSB) Zero Offset Adjustment. Connect all digital inputs to.. Adjust the offset zero adjust trimpot of the output operational amplifier for 0V 0.mV (Max) at. Gain Adjustment V 7 R FEEDBACK 8 AD7 I CR OUT. Connect all digital inputs to V DD.. Monitor for a ( / ) reading.. To increase, connect a series resistor, (0 to 0 ), in the amplifier feedback loop.. To decrease, connect a series resistor, (0 to 0 ), between the reference voltage and the terminal. TABLE. CODE TABLE UNIPOLAR BINARY OPERATION DIGITAL INPUT ANALOG OUTPUT ( / ) 0000000000 ( / / ) 00000000000 / 0 ( / / ) 00000000000 ( / ) 000000000000 0 Bipolar (Offset Binary) Operation FIGURE. UNIPOLAR BINARY OPERATION (QUADRANT MULTIPLICATION) The circuit configuration for operating the AD7 in the bipolar mode is given in Figure. Using offset binary digital input codes and positive and negative reference voltage values FourQuadrant multiplication can be realized. The Digital Input Code/Analog Output Value table for bipolar mode is given in Table. A Logic input at any digital input forces the corresponding ladder switch to steer the bit current to bus. A Logic 0 input forces the bit current to bus. For any code the and bus currents are complements of one another. The current amplifier at changes the polarity of current and the transconductance amplifier at output sums the two currents. This configuration doubles the output range of the DAC. The difference current resulting at zero offset binary code, A FN07 Rev..00 Page of 8
AD7 (MSB = Logic, All other bits = Logic 0 ), is corrected by using an external resistive divider, from to. Offset Adjustment. Adjust to approximately 0V.. Set R to zero.. Connect all digital inputs to Logic.. Adjust amplifier offset zero adjust trimpot for 0V 0.mV at amplifier output.. Connect a short circuit across R.. Connect all digital inputs to Logic 0. 7. Adjust amplifier offset zero adjust trimpot for 0V 0.mV at amplifier output. 8. Remove short circuit across R. 9. Connect MSB (Bit ) to Logic and all other bits to Logic 0. 0. Adjust R for 0V 0.mV at. Gain Adjustment. Connect all digital inputs to V DD.. Monitor for a ( / ) volts reading.. To increase, connect a series resistor, (0 to 0 ), in the amplifier feedback loop.. To decrease, connect a series resistor, (0 to 0 ), between the reference voltage and the terminal. TABLE. CODE TABLE BIPOLAR (OFFSET BINARY) OPERATION DIGITAL INPUT ANALOG OUTPUT ( / ) 0000000000 ( / ) 00000000000 0 0 ( / ) 00000000000 ( / ) 000000000000 0V V 7 8 DIGITAL INPUT AD7 A R 0K R 0K R 0K R 90K BIT (LSB) A R 00 NOTE: R and R should be 0.0%, lowtcr resistors. FIGURE. BIPOLAR OPERATION (QUADRANT MULTIPLICATION) FN07 Rev..00 Page of 8
AD7 Test Circuits V 7 8 R FEEDBACK BIT BINARY COUNTER BIT (LSB) AD7 HA00 0K 0.0% M CLOCK BIT (MSB) BIT BIT BIT REFERENCE DAC 0K 0.0% HA00 LINEARITY ERROR X 00 BIT FIGURE. NONLINEARITY TEST CIRCUIT V UNGROUNDED SINE WAVE GENERATION 0Hz.0V PP 00K 0V BIT (LSB) K 0.0% 7 R FEEDBACK K 0.0% 8 I OUT AD7 I HA00 OUT HA00 V ERROR X 00 FIGURE. POWER SUPPLY REJECTION TEST CIRCUIT V (ADJUST FOR = 0V) V K F 7 AD7 0K 00 K 0. F 0K 0ALN 0V f = khz BW = Hz QUAN TECH MODEL D WAVE ANALYZER FIGURE. NOISE TEST CIRCUIT FN07 Rev..00 Page of 8
AD7 Test Circuits (Continued) V NC V = 0V PP 0kHz SINE WAVE V BIT (LSB) 7 8 AD7 7 SCOPE NC K 00mV PP MHz BIT (LSB) 7 8 AD7 HA00 FIGURE 7. OUTPUT CAPACITANCE TEST CIRCUIT FIGURE 8. FEEDTHROUGH ERROR TEST CIRCUIT V 0V DIGITAL INPUT V 0V EXTRAPOLATE BIT (LSB) 7 AD7 00mV 00 t: % SETTLING 9t: 0.0% SETTLING OSCILLOSCOPE FIGURE 9. OUTPUT CURRENT SETTLING TIME TEST CIRCUIT V 0V BIT BIT (LSB) 7 8 AD7 R FEEDBACK I C OUT C A FIGURE 0. GENERAL DAC CIRCUIT WITH COMPENSATION CAPACITOR, C C Dynamic Performance The dynamic performance of the DAC, also depends on the output amplifier selection. For low speed or static applications, AC specifications of the amplifier are not very critical. For highspeed applications slewrate, settlingtime, openloop gain and gain/phasemargin specifications of the amplifier should be selected for the desired performance. The output impedance of the AD7 looking into varies between 0k (R FEEDBACK alone) and k (R FEEDBACK in parallel with the ladder resistance). Similarly the output capacitance varies between the minimum and the maximum values depending on the input code. These variations necessitate the use of compensation capacitors, when high speed amplifiers are used. A capacitor in parallel with the feedback resistor (as shown in Figure 0) provides the necessary phase compensation to critically damp the output. A small capacitor connected to the compensation pin of the amplifier may be required for unstable situations causing oscillations. Careful PC board layout, minimizing parasitic capacitances, is also vital. FN07 Rev..00 Page 7 of 8
AD7 DualInLine Plastic Packages (PDIP) INDEX AREA BASE PLANE SEATING PLANE D B C A N N/ B D e D E NOTES:. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control.. Dimensioning and tolerancing per ANSI Y.M98.. Symbols are defined in the MO Series Symbol List in Section. of Publication No. 9.. Dimensions A, A and L are measured with the package seated in JEDEC seating plane gauge GS.. D, D, and E dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.00 inch (0.mm).. E and e A are measured with the leads constrained to be perpendicular to datum C. 7. e B and e C are measured at the lead tips with the leads unconstrained. e C must be zero or greater. 8. B maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.00 inch (0.mm). 9. N is the maximum number of terminal positions. 0. Corner leads (, N, N/ and N/ ) for E8., E., E8., E8., E. will have a B dimension of 0.00 0.0 inch (0.7.mm). B A 0.00 (0.) M C A A L B S A e C E C L e A C e B E8. (JEDEC MS00BC ISSUE D) 8 LEAD DUALINLINE PLASTIC PACKAGE INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A 0.0. A 0.0 0.9 A 0. 0.9.9.9 B 0.0 0.0 0. 0.8 B 0.0 0.070..77 8, 0 C 0.008 0.0 0.0 0. D 0.8 0.880.7. D 0.00 0. E 0.00 0. 7. 8. E 0.0 0.80.0 7. e 0.00 BSC. BSC e A 0.00 BSC 7. BSC e B 0.0 0.9 7 L 0. 0.0.9.8 N 8 8 9 Rev. 0 /9 Copyright Intersil Americas LLC 00. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO900 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN07 Rev..00 Page 8 of 8