A Compact Digital Pixel Sensor (DPS) Using 2T-DRAM

J. Low Power Elecron. Appl. 2011, 1, 77-96; doi:10.3390/jlpea1010077 Aricle OPEN ACCESS Journal of Low Power Elecronics and Applicaions ISSN 2079-9268 www.mdpi.com/journal/jlpea A Compac Digial Pixel Sensor (DPS) Using 2T-DRAM Xiaoxiao Zhang, Sylvain Leoman, Ka Lai Lau and Amine Bermak Deparmen of Elecronic and Compuer Engineering, Hong Kong Universiy of Science and Technology (HKUST), Clear Waer Bay, Kowloon, Hong Kong, China; E-Mails: zhangxx@us.hk (X.Z.); eesleoma@us.hk (S.L.); kakalau@us.hk (K.L.L.) Auhor o whom correspondence should be addressed; E-Mail: eebermak@us.hk. Received: 7 December 2010; in revised form: 14 March 2011 / Acceped: 21 March 2011 / Published: 28 March 2011 Absrac: In digial pixel sensors (DPS), memory elemens ypically occupy large silicon area of he pixel, which significanly reduces he pixel s fill facor while increases is size, power and cos. In his work, we propose o reduce DPS memory s area and power overhead by reducing he memory requiremens wih a muli-rese inegraion scheme, and meanwhile employing a dynamic memory insead of radiionally exploied large 6T-SRAM cell. The operaion of he DPS akes advanage from he chronological change of he code, which resuls in reduced memory needs wihou affecing he ligh resoluion. In he proposed implemenaion, a 4-bi in-pixel memory is used o reduce he pixel size, and an 8-bi resoluion is achieved wih muli-rese scheme. In addiion, full complemenary meal-oxide-semiconducor (CMOS) 2T DRAM and selecive refresh scheme are adoped o implemen he memory elemens and furher increase he area savings. This paper presens he proposed muli-rese inegraion mehodology and is implemenaion wih dedicaed memory circuis. Proposed archiecure is validaed by a prooype chip fabricaed using AMS 0.35 µm CMOS echnology. Repored experimenal resuls are compared wih relaive works. Keywords: image sensors; digial pixel sensors; pulse widh modulaion pixel; 2T-DRAM

J. Low Power Elecron. Appl. 2011, 1 78 1. Inroducion Complemenary meal-oxide-semiconducor (CMOS) image sensors are now par of our everyday s life covering a wide specrum of applicaions from cell-phone cameras, webcams, digial cameras, video games o securiy and auomoive applicaions [1]. The successful deploymen of CMOS image sensors over he charge coupled devices (CCD) echnology is mainly due o reduced cos and power consumpion, as well as higher inegraion and on-chip processing capabiliies, which are criical for mobile applicaions. Among CMOS image sensors, wo mainsream archiecures are o be disinguished depending on where he analog-o-digial conversion (ADC) is achieved. Firs is acive pixel sensors (APS), which perform he ADC ouside he pixel array using a per-array or per-column readou scheme. Second is digial pixel sensors (DPS), which inegrae he ADC a he pixel level. DPS, while giving flexibiliy of use, perform massive parallel analog o digial conversion a he pixel level and enable he promising pixel-level image processing, which is very aracive for real ime applicaions such as auomoive and surveillance sysems. In addiion, due o a very early analog-o-digial conversion, DPS can offer improved noise figure and dynamic range [2]. Previous DPS implemenaions are based on eiher pulse frequency modulaion (PFM) [3] or pulse widh modulaion (PWM) [4] scheme o digiize he volage of he phoodiode s sensing node wih a volage comparaor. The PWM scheme uses he comparaor oupu signal o wrie a global couner value in he pixel-level memory, while he PFM scheme uses he comparaor oupu o enable an incremen of he pixel-level couner. Boh PFM and PWM schemes are ypically power hungry, due o he high swiching aciviy a he pixel level. In addiion, a major drawback of boh schemes is he requiremen of area-hungry pixel level memory paricularly for high resoluion imaging. As a consequence, he area and power overhead due o he pixel level memory are subsanial and can accoun for up o 50% of he oal overhead. This srongly impacs he pixel s fill facor and hus is ligh sensiiviy as well as he power and pixel area. Several aemps were made o reduce he memory needs a pixel level. Among he oher soluions, he use of an address even represenaion (AER) scheme [5] compleely removes he memory from he pixel a he cos of increased complexiy and he inroducion of iming errors due o collision which occurs when several pixels aemp o access he daa bus simulaneously. Anoher repored soluion consiss of compressing he daa even before sorage as proposed in [6]. This las soluion drasically reduces he pixel area bu a he cos of reduced signal-o-noise raio (SNR) due o he use of lossy compression scheme. In [7], he oupu of he comparaor is sampled and sored using a single bi regiser cell per pixel. All regiser cells are conneced in series o form a scan chain and he whole array is scanned afer each sampling operaion. While only one bi pixel-level memory is required, his archiecure increases power consumpion as he number of samples which is a srong funcion of he resoluion. In his work, a DPS archiecure using 2T DRAM as he sorage elemen and a muli-rese inegraion mehodology are proposed in order o reduce boh he memory needs and he memory size a he pixel-level and reduce he power overhead. The paper is organized as follows: Secion 2 inroduces he PWM ime domain DPS and is conversion ime analysis. Secion 3 is devoed o he muli-rese inegraion mehodology and a discussion abou he rade-offs involved in erms of speed, area and memory size. Secion 4 describes he muli-rese

J. Low Power Elecron. Appl. 2011, 1 79 inegraion DPS archiecure, he pixel circuiry and he 2T DRAM implemenaion and sensing scheme. Secion 5 provides an analysis of power consumpion as well as power reducion echniques. Secion 6 presens he prooype implemenaion and experimenal measuremens. Secion 7 concludes his work. 2. Time-Domain PWM DPS 2.1. Convenional Archiecure The convenional pixel archiecure of a DPS using he PWM echnique is shown in Figure 1. The pixel comprises a phoodiode P d, a rese ransisor AR, a volage comparaor, a memory uni and a feedback circui o perform he auo-rese of he phoodiode. Ouside he pixel array, a iming conrol uni and a global couner are required o perform he conversion of he ligh inensiy ino a digial code. A read-ou circui is also needed o read he conens from he memory and o oupu he daa o he processing uni. Figure 1. Schemaic view of he convenional pixel and corresponding iming diagrams. SI Vdd Frame Cycle Vd Vc Vdd RESET CONTROL Vrs Low Illuminaion(2) EN Vref High Illuminaion(1) AR RESET SI Ou Vdd Vd Vref Pd Vbias Ou Xsel W R 8 bi memory AR Vdd Td1 Ysel Daa Td2 COMPARATOR MEMORY The inegraion phase sars by disabling he precharge o he supply volage of he phoodiode, i.e., when he rese signal ransis from 0 o V dd. Meanwhile, a global couner locaed ouside he pixel array is simulaneously enabled. The volage V d of he phoodiode node loaded wih a capaciance C pd sars decreasing proporionally o ligh inensiy due o he phoo-generaed curren I d hrough he phoodiode P d. When he volage V d reaches a reference volage V ref, he oupu of he comparaor swiches high and he couner value is wrien o he pixel-level memory. The rese of he phoodiode is performed auomaically afer he phoodiode volage has reached he reference level V ref. The wrien code in he

J. Low Power Elecron. Appl. 2011, 1 80 memory is a digiized value of he ime required for V d o reach V ref, which is a funcion of he ligh inensiy. Using firs order approximaion, he inegraion ime is expressed as: T in = C pd(v dd V ref ) I d = α I d (1) From Equaion (1), one mus noice ha he inegraion ime is inversely proporional o he phoo-generaed curren I d. To perform he quanizaion of he inegraion ime, he global couner is used o provide he quanizaion boundaries for he ime o digial conversion. The non-lineariy beween he phoocurren and he inegraion ime can be compensaed by adaping he frequency of he global couner as shown in Figure 2. On one hand, Figure 2(a) represens a uniform ime domain quanizaion leading o a non-linear response from he sensor as he phoocurren boundary quanizaion seps are non-linear. On he oher hand, he non-uniform ime domain quanizaion depiced in Figure 2(b) enables o linearize he conversion of phoocurren ino digial code as he phoocurren boundary quanizaion seps are now linear. Figure 2. Uniform and non-uniform ime-domain quanizaions [4]. (a) Uniform ime domain quanizaion. (b) Non-uniform ime domain quanizaion. 2.2. Conversion Time Analysis PWM coding scheme encodes he illuminaion level informaion of each pixel using a single pulse. This pulse widh represens ime T in o discharge a phoodiode from V dd o V ref. In order o conver he pulse ino digial code, a ime code generaed by he global couner is wrien ino he embedded memory once he pulse is deeced. There are wo quanizaion approaches o conver he PWM pulse signal ino digial code. The firs approach, referred o as uniform ime domain quanizaion (UQ), which provides sampling imes (or boundary quanizaion levels) from T min o T max uniformly. The second approach referred o as non-uniform ime domain quanizaion (NUQ), resolves he sampling ime in order o form a uniformly quanized phoocurrens. A non-linear ime-domain quanizer is herefore required in order o compensae for ime-o-phoocurren non-lineariy.

J. Low Power Elecron. Appl. 2011, 1 81 2.2.1. Uniform Time-Domain Quanizaion Uniform ime domain quanizaion scheme divides he ime wihin he boundaries T min and T max equally ino 2 n quanizaion levels, where n represens he number of bis or resoluion. Therefore, he ime widh of each quanizaion level T can be expressed as: T = T max T min 2 n (2) While he relaionship beween he quanizaion level ξ UQ (n, ) and he ime widh of he PWM pulse is illusraed in he following equaion: ξ UQ (n, ) = T min T = 2n ( T min ) T max T min (3) Using Equaion (3) he conversion beween he quanizaion level ξ UQ (n, I d ) and he discharge phoocurren I d of he phoodiode can be expressed as following: α I dmax ) α I dmin α I dmax ξ UQ (n, I d ) = 2n ( α I d Assuming ha I dmax I dmin, Equaion (4) can be approximaed as: = 2n ( I dmaxi dmin I d I dmin ) I dmax I dmin (4) ξ UQ (n, I d ) 2 n I dmin ( 1 I d 1 I dmax ) (5) Equaion (5) suggess ha, he quanizaion level is inversely proporional o he discharge curren under he UQ scheme, as I dmin I dmax is a consan. Indeed, i also suggess ha he UQ scheme is sensiive o he discharging curren close o I dmin, shown in Figure 3(b). This suggess ha he UQ scheme focuses on quanizing he low illuminaion levels, while he high illuminaion levels are no properly covered. 2.2.2. Non-Uniform Time-Domain Quanizaion Non-uniform ime domain quanizaion scheme resolves he quanizaion levels in order o form linearly disribued phoocurrens I wihin he boundaries I dmin and I dmax. I = I dmax I dmin 2 n (6) The phoocurren I d can be convered o is dedicaed quanizaion level ξ NUQ (n, I d ) as follows: ξ NUQ (n, I d ) = I d I dmin I = 2n (I d I dmin ) I dmax I dmin (7)

J. Low Power Elecron. Appl. 2011, 1 82 Figure 3. (a) 3 bis UQ and NUQ in erms of ime; (b) 3 bis UQ and NUQ in erms of discharging curren. (a) (b) From Equaion (7), we can noe ha he relaionship beween he ime and he quanizaion level ξ NUQ (n, ) can be expressed as: α T max ) α T min α T max ξ NUQ (n, ) = 2n ( α = 2n ( TmaxT min T min ) T max T min (8) In conras o UQ scheme, Equaion (8) suggess ha, he NUQ quanizaion levels are inversely proporional o he sampling ime. Figure 3(b) shows ha he NUQ provides an evenly disribued phoocurren sampling boundaries. 3. The Proposed Muli-Rese Inegraion (MRI) Scheme In order o reduce silicon area of he pixel and o improve he fill facor, a muli-rese inegraion (MRI) scheme is proposed in his work o reduce he memory needs a he pixel level. This secion presens he concep of he MRI and discusses he rade-offs in erms of delay overhead depending on he size of he pixel memory. 3.1. MRI Concep The proposed inegraion scheme akes advanage of he sequenial way how he illuminaion level is digiized. The MRI scheme can be inerpreed as performing he inegraion process several imes in order o resolve each bi of he illuminaion code sequenially, from he mos significan bi (MSB) o he leas significan bi (LSB), as shown in Figure 4. During each new inegraion phase, only a sub-se of he n bis are sored a he pixel reducing he memory requiremens. Then, beween wo inegraion periods, he conen of he pixel memory is scanned ou of he array allowing for he remaining bis of he code o be sored during he successive inegraion phases. The required number of bis for he memory

J. Low Power Elecron. Appl. 2011, 1 83 is herefore reduced by a facor proporional o he number of ieraions. For example, considering a resoluion of 8 bis and a single bi memory, 8 successive reses will be required. In order o reduce he delay overhead caused by he successive inegraion periods, i is possible o define iming boundaries for which he value of he concerned bi of he code is resolved allowing o opimize he corresponding inegraion duraion for each bi. Figure 4. Timing diagram of he muli-rese inegraion scheme. Din V Inegraion phase no. 1 Inegraion phase no. 2 255 254... X... 128... 255 254... X... 64... Inegraion phases no.3 o 7 Inegraion phase no. 8 255 254... X... 0... V Global Rese V Vn V Wrie V Read Enable V Sored Bi 0 X[7] 0 X[6] 0 0 X[0] 0 MSB 2nd MSB LSB Assuming he phoocurren is quanized ino 2 n values, wih n as he resoluion. The quanizaion levels N QT covered by each bi can be expressed as: N QT (i) = 2 n 2 i + 1 i {0, n 1} (9) where bi(0) represens he LSB and bi(n 1) represens he MSB. The quanizaion levels coverage of he MSB is only half of he oal quanizaion levels. Therefore, he opimized inegraion ime for he bis closer o he MSB is much shorer han hose owards he LSB. Indeed, derived from Equaion (1), he opimized duraion of he parial inegraion phase T in required o obain he bi number i of he code is given by: α T in (i) = I max 2n 2 i +1(I 2 n max I min ) = α 1 ( I min 1 + (2 i n 2 n )( Imax I min 1) ) As I max I min 1, 1 T max ( 1 + (2 i n 2 n )( Imax I min ) ) (10)

J. Low Power Elecron. Appl. 2011, 1 84 where T max = α I min is he maximum inegraion ime for n bis resoluion. Under he I max I min condiion, Equaion (10) illusraes ha inegraion ime decreases exponenially when i increases. Assuming 1-bi pixel memory, geing he N bis successively will give a oal inegraion ime T oal ha corresponds o he sum of he duraions of each parial inegraion phase T in. Therefore, he acual inegraion ime of he proposed scheme is expressed by: n 1 T oal = T max i=0 1 1 + (2 i n 2 n )( Imax I min ) (11) From his equaion, he oal ime required o realize he inegraion wih he muli-rese inegraion scheme is much shorer han n T max. I can also be noed ha he ime required o scan he values ou is no accouned for in his equaion. However, his ime can be reduced significanly using parallel and high-speed readou and remains negligible compared o he oal inegraion ime. In addiion, he read-ou phase can be inerleaved wih he inegraion phase. Figure 5 akes 2-bi resoluion as example and assumes I max /I min = 100. Using Equaion (10), T in MSB = 1 26 T max, T in LSB = T max. I is possible o resolve he MSB a a 1/26 fracion of he inegraion period followed by he second bi or he LSB afer one inegraion period. Originally, under he MRI scheme, 2T max are required o obain he MSB and he LSB values. In his scheme, using he opimum iming boundaries, he oal inegraion ime is reduced by 48%. These opimized iming boundaries are used o rese each parial inegraion herefore grealy reduce he iming overhead for high resoluion imagers. In addiion, over inegraion periods are avoided leading o reduced power consumpion. Figure 5. Illusraion of iming boundaries for a 2-bi resoluion. 3.2. Trade-off Analysis Depending on he memory size inegraed a he pixel level, differen area-delay rade-offs can be achieved. Indeed a rade-off can be made beween he required number of bis for he pixel-level memory and he required number of rese of he inegraion phases. MATLAB simulaions were performed o exrac he rends in pixel area versus he size of he memory embedded a he pixel-level and he resuls are shown in Figure 6. In he simulaion, a square pixel wih 30% fill-facor is assumed. The area is esimaed for CMOS 0.35 µm echnology. Area limied by he meal wires and he oal size of he ransisors are also considered. Area of pixel-level embedded memories wih 6T SRAM and 2T DRAM are boh considered. The Figure illusraes ha he area of he pixel wih embedded 6T SRAM is linear

J. Low Power Elecron. Appl. 2011, 1 85 o he number of embedded bis, since i is mainly consrained by he ransisors area. While he area of he pixel wih embedded 2T DRAM is mainly consrained by meal wires. The size of a pixel using 4 bi 2TDRAM is only 72% of he pixel using 4 bi 6T SRAM. Figure 6. Pixel area as funcion of he number of embedded bis. MATLAB simulaions were also performed o exrac he rends in he delay overhead versus he size of he memory embedded a he pixel-level. Figure 7 shows he inerpolaed curve of he delay overhead in erms of inegraion ime versus he memory size n for an 8-bi resoluion by assuming Imax I min = 250. From hese resuls, i appears ha using a 4-bi pixel-level memory requires only one rese and leads o less han 10% overhead on he oal inegraion ime. Considering boh he area and he inegraion ime overheads, using he 4 bis 2T DRAM opimally mainains a small pixel area and keeps a relaively high operaion speed. Figure 7. Inerpolaed curve of he delay as a funcion of memory size.

J. Low Power Elecron. Appl. 2011, 1 86 4. MRI-Based Digial Pixel Sensor 4.1. Overall Archiecure In order o implemen he MRI scheme wih a dynamic memory several changes are required compared o he convenional archiecure. As a resul of he rade-offs analysis presened in he previous secion, he choice o implemen a 4 bi memory elemen has been made. Besides, on op of cuing he memory requiremens by a facor of wo wih he MRI scheme, he use of he full CMOS 2T DRAM insead of he 6T SRAM cell is proposed o furher increase he area savings. The block diagram of he resuling global archiecure is presened in Figure 8. Two scan shif regisers are used o selec each line of he array during he reading operaion and o shif he read values ou of he sensor. The memory sensing and refresh circui is composed of sense amplifiers o boh deec he sae of he pixel: fired or no fired, as well as o read he conen of he pixel-level memories, simulaneously. Based on he sae of he pixel, a condiional refresh circui allows o selecively rewrie he useful informaion. In oher erms, based on an exernal leakage monior or an exernal emperaure sensor giving reenion ime condiions in he memory, he conen will be refreshed wih minimal overhead for power consumpion. A conrol uni allows he pipeline of he read operaion and he scan ou operaion o minimize he ime beween wo parial inegraions. Large wrie buffers are used o sore he informaion from he global couner inside he pixel-level memory during he inegraion. A couner iming uni and a linearizaion circui are also used o provide he daa o he pixel-level memories. Figure 8. Block diagram of he overall archiecure. Replica Circui Shif Regiser Line Selecion Pixel Array Reference Volage Generaion Crl Read Refresh Circui Scan Shif Regiser 4.2. Pixel Circui The proposed pixel circuiry is depiced in Figure 9, which conains a rese ransisor conrolled by a global rese signal, a volage comparaor, a flag circuiry o indicae he firing sae of he pixel, a pass logic circui o bypass he oupu of he comparaor during he refresh operaion and finally he 2T DRAM cells. The operaion of he proposed pixel sars by a rese low signal enabling o se he phoodiode volage o he supply level. A he end of he rese phase, he phoodiode is lef floaing and

J. Low Power Elecron. Appl. 2011, 1 87 he volage of he equivalen capaciance of he phoodiode is discharged by he illuminaion dependan phoocurren. A he same ime, a global down couner ouside he pixel array is enabled and is daa is fed o he inernal sorage elemens of he pixel. The memory is se in he wrie mode during he inegraion phase, as shown in Figure 10 and he conen of one bi DRAM will rack he corresponding daa line. When he phoodiode volage crosses he reference volage, he oupu of he comparaor swiches disabling he wrie signal. When a row is accessed he memory is se in he read mode and he flag signal allows he wrie driver of he column o refresh he daa if he pixel has fired. A he same ime, all he pixels of he same column belonging o differen rows are se in a hold mode in order o preven a wrong daa o be wrien o he memory. Figure 9. Pixel schemaic and layou. (a) Schemaic diagram. (b) Layou view. Figure 10. Simulaed iming diagram illusraing he pixel s operaion.

J. Low Power Elecron. Appl. 2011, 1 88 4.3. 2T DRAM Implemenaion In he proposed archiecure, a 4-bi 2T DRAM is used as he pixel level memory elemen. The use of 2T-DRAM reduces he area compared o he convenional 6T SRAM. The use of a dynamic memory fis very well he requiremens of a DPS as a frequen use of he memory is required wih muli-rese inegraion scheme. However, he use of dynamic memories adds some complexiy compared o saic ones mainly due o he loss of charges on he sorage node caused by leakage currens. A refresh circui is herefore required o solve his problem, depending on exernal condiions, emperaure, supply volage and process variaions. In his par, he implemenaion of he pixel dedicaed memory is described. Some echniques employed in memory design will be reviewed and adaped o he need of he DPS archiecure. The 2T DRAM cell shown in Figure 11(a) is derived from he well known 3T-DRAM and was proposed recenly as a poenial memory cell for microprocessor s cache [9]. The main advanage of his memory cell is ha i uses a full CMOS echnology and i improves densiy compared o he 3T-DRAM, by removing he access ransisor. The operaing principle illusraed in Figure 11(b) can be summarized as follows: during a wrie operaion, he wrie word-line is se high or low in order o charge or discharge he sorage node loaded by he gae capaciance of ransisor M2 and he diffusion capaciance of ransisor M1. Noe ha for a convenional NMOS bi-cell, he gae volage for soring he sae 1 will be limied o he supply volage minus one hreshold volage. In he hold mode, he wrie word-line is kep low and he leakage currens discharge progressively he inernal node and herefore deermine he daa reenion ime and correspondingly he required refresh period. During he read operaion, he read word-line is se low enabling or disabling he discharge of he pre-charged read bi-line, depending on he sored sae on he gae of ransisor M2. Figure 11. 2T DRAM cell operaion. WWl RWl WBl WWl RBl WBl M1 Vsore M2 Vsore Vdd Vn RWl RBl WRITE HOLD READ (a) 2T-DRAM cell (b) Operaing principle 4.4. Differenial Sensing Scheme and Volage Generaion The choice of differenial sensing was made as i reduces he volage swing on he bi-lines hus he power consumpion incurred by he read operaion. Besides, differenial sensing improves he robusness o common mode noise on he bi-line such as supply volage variaions. This scheme has however a cos

J. Low Power Elecron. Appl. 2011, 1 89 as i requires boh a bi-line and a reference bi-line for a single cell and a reference volage generaion circui. In order o reduce coupling noise beween bi-lines, ransposed bi-line archiecure is adoped using regular inerleave of bi-lines wihin he pixel array. As shown in Figure 12, each column is divided ino sub-blocks indexed eiher odd or even. During a read operaion, he conrol uni oupus he sae of he block being accessed eiher odd or even. This signal allows o deermine he bi-line and he reference bi-line for correc reference volage generaion and also o configure he lach inpu, using a muliplexer. The reference volage is generaed using a row of dummy cells eiher suck a value 0 or 1, giving an inermediae volage for he sensing operaion. Figure 12. Diagram of he ransposed bi-line archiecure and he laching sage. REF REF BLOCK<1> BLOCK<0> ODD EVEN pxl pxl pxl pxl pxl pxl pxl pxl Reference volage generaion on eiher Bi line or Bi line b Blb Bl SA+PRECHARGE Din SAE EVEN ODD Daa ODD BLOCK EVEN BLOCK SAE EVEN 4.5. Read and Refresh Circui In order o acivae he sense amplifier a he righ ime for correc sensing of he memory cell, a replica circui (Figure 13) based on a dummy column and a dummy memory cell is used [10]. Noe ha for correc sensing of he memory, he differenial volage, i.e., he volage beween he reference bi-line and he bi-line o be read, mus be higher han he offse value of he sense amplifier. Figure 14 depics he reading sage designed o access he pixel level memory. As all memory cells of a same pixel mus be read simulaneously, a simple sense amplifier srucure was chosen. A basic lach-based sense amplifier is used o fi wihin he pixel pich. Each pixel conains 4 bis, all are read simulaneously. Therefore, four sense amplifiers have o fi wih one column pich. The reading operaion is a large conribuor o he oal power consumpion of he chip, indeed he charge required during pre-charge operaion of he large bi-line capaciances and he large saic curren flowing hrough he sense amplifier mus be reduced as much as possible. As a consequence, a close conrol of he sense amplifier iming is criical and can reduce large amoun of power. As he sensing operaion is differenial, he generaion of a reference volage is required. The reference volage is generaed as in [9]. The ransposed bi-line archiecure allows o reduce he coupling effecs beween wo adjacen lines bu adds some complexiy. In order o keep power under conrol, he refresh operaion is performed only on he fired pixel (Figure 15). This prevens unnecessary swiching ransiions on he daa buses, hus saves power. In order o achieve his, a flag signal is used o deec he sae of he pixel and only if he pixel has fired he conen of he memory is read and refreshed. To conrol he refresh operaion a signal is fed o he DPS saring he refresh operaion.

J. Low Power Elecron. Appl. 2011, 1 90 Figure 13. Schemaic view of he replica scheme. Dummy Column Accessed Column SHIFT REGISTER SIPO Buffer Chain Buffer Chain Buffer Chain Buffer Chain pxl pxl pxl pxl Seleced Line Bi line pxl pxl pxl pxl Bi line Inernal Clk Dummy Bi line Replica on Dummy 2T DRAM Cell Delay Chain Sense Enable Sense Amplifier Sense Oupu PrechargeON (Sync w. Replica ON) Feed back replica Figure 14. Diagram of he reference volage generaion. 1 Column of pixels Bi lineb<0> Bi lineb<1> Bi lineb<2> Bi lineb<3> Reference ON Dummy Cell Dummy Cell suck a 1 suck a 0 Bi line<0> Bi line<1> Bi line<2> Bi line<3> SA<0> SA<1> SA<2> SA<3> Reference volage generaed wih average of 64 cells suck a and 64 cells suck a 0

J. Low Power Elecron. Appl. 2011, 1 91 Figure 15. Schemaic of he sensing and wrie sage. Sae SaeFS STATE DETECTION Pchb Wbl Bl Vdd Pchb Refbl PRECHARGE STAGE Sae ISOLATION STAGE Vdd Daa Daa SENSE AMPLIFIER Sae Sae WRITE STAGE SYNCRONIZATION CIRCUIT lach mux2:1 Di(Couner) Dou (a) Schemaic diagram of he refresh scheme. (b) Simulaed curves. 5. Power Analysis and Power Reducion Techniques In his par an analysis of he power consumpion of he proposed archiecure is given. Power consumpion resuls were obained from elecrical simulaions using Specre simulaor from Cadence. The aim of his analysis is o idenify he major conribuors o he oal power consumpion by giving he disribuion of oal power among differen blocks of he archiecure such as he array, he sense amplifier, precharge circui and he wrie buffers. This analysis is hen used o consider power reducion echniques ha are generally cosly in erms of speed and area, only on criical blocks of he archiecure. 5.1. Power Consumpion Analysis In order o perform our power consumpion analysis, a criical pah of he 64 64 DPS has been designed and simulaed using Specre elecrical simulaor o reduce he nelis size and herefore he simulaion ime. From his analysis, i is clear ha main conribuor o power and energy consumpions are he pixels as he volage comparaor of each pixel is drawing large saic curren during he whole inegraion ime. Considering mobile applicaions, energy is he key meric o be considered and excep he energy required by he pixel o capure one frame, one can say ha he remaining energy consumpion is spread on all blocks. The energy consumpion from scan shif regisers can be negleced. Table 1 shows he power consumpion analysis from elecrical simulaion a nominal process and supply volage.

J. Low Power Elecron. Appl. 2011, 1 92 Table 1. Power consumpion analysis from elecrical simulaion a nominal process and supply volage. Average Power a 30 f/s Average Energy per Frame a 30 f/s Array (Pixels) 13.9 mw 13.9 µj (3.4 nj/pixel) Scan shif regiser 800 nw 23 nj Wrie buffers 24 µw 24 nj Scan regiser for line selecion 10 nw 0.3 nj Precharge and sense amplifiers 430 nw 13 nj 5.2. Power Reducion Techniques The power consumed by he volage comparaors conained in each pixel represens he major conribuor of he oal power consumpion. In order o reduce he power consumpion compared o he acual implemenaion, eiher an auo-rese funcion employing a feedback uni or a differen comparaor srucure could be used. The main advanage of a lach-based sense amplifier is he power consumpion reducion compared o he convenional archiecure, where a bias curren is drawn permanenly from he supply. However, his kind of comparaor suffers from large offse resuling in a lower image qualiy. To solve his problem, a pre-amplifier may be used as a firs sage a he cos of increased area overhead. Anoher soluion is he use of swiched op-amp echnique, allowing o enable or disable he comparaor using a clock signal. This circui maches well wih he ime domain DPS archiecure. Indeed, during he analog o digial conversion, he volage of he phoodiode needs o be compared o a reference volage V ref periodically when he global couner oupu is swiching from one sae o anoher. If he global couner frequency is low enough o swich on he comparaor during a shor period before he couner value changes, hen power savings may be achieved. This scheme is even more efficien when using he non-uniform quanizaion scheme, as he frequency is reduced along wih he inegraion period. Therefore he swiching aciviy and he ime during which he comparaor is on is srongly reduced compared wih he sandard implemenaion. Figure 16 depics he schemaic of he proposed implemenaion for he DPS volage comparaor and simulaed curves of key signals. Compared wih he convenional pixel level comparaor, 2 PMOS and 1 NMOS are added o conrol he swiching. These hree gaes only increase he size of he proposed design in Figure 9 by 2.8%. Transisors MN1-MN2-MP1-MP2 consiue he differenial pair, MNB is a bias ransisor wih is gae volage conrolled exernally for improved flexibiliy. MNF is a fooer ransisor o cu he supply pah once he pixel is fired. MP3 and MN3 consiue he oupu sage of he comparaor o have a full swing signal oupu volage os2. MPS is added o se he correc sae on he oupu during inacive mode by conrolling he volage os1. Noe ha we can use his comparaor wih a phoodiode se in phoovolaic mode allowing for energy harvesing capabiliies. The feedback circui used o disable he operaion of he comparaor is no affecing he rese ransisor bu conrolling he supply pah and enabling o maximize he ime during which he phoodiode is in he energy harvesing mode. From he simulaion resuls (Figure 17), one can observe ha while enabling periodically he comparaor, only one pulse is observed on signal os2 corresponding o he crossing of he phoodiode volage wih he volage level V ref. The simulaed power consumpion of he volage comparaor is in he range of nw depending

J. Low Power Elecron. Appl. 2011, 1 93 on he frequency and linearizaion scheme used, which grealy reduces he power consumpion of he original implemenaion by 2 o 3 orders of magniude. Figure 16. Schemaic diagram of he proposed swiched-opamp comparaor for PWM DPS applicaions. Vdd Bias MPB1 MP3 MPH2 MPH1 fired Clock MPS MP4 MP5 os2 fired_b vpd MP1 MP2 Vref fired Grese MN1 MN2 os1 MN3 MNR1 MNS MNR2 MN4 MN5 Figure 17. Simulaion resuls a nominal process and supply. 6. Hardware and Measuremen Resuls In order o validae he proposed archiecure, a prooype of a 64 64 DPS array was designed using he AMS 0.35µm CMOS echnology. Figure 18 shows he microphoograph of he fabricaed chip

J. Low Power Elecron. Appl. 2011, 1 94 illusraing he differen pars of he chip namely, he pixel array, he shif regisers for line selecion and scan-ou of daa as well as he conrol block. Figure 18. Microphoograph of he prooype. The funcionaliy of he DPS using MRI concep was validaed and successfully esed. Elecrical signals from he pixel were successfully capured. Figure 19 illusraes he signals capured wihin he pixel using a Tekronix DS2024 oscilloscope. This Figure shows elecrical signal boh inside and ouside he pixel, o demonsrae is funcionaliy. Top o boom signals illusraed in Figure 19 correspond o he complemen of he rese signal, he phoodiode node volage, he line selecion signal and he complemen of he flag sae signal afer he read-ou phase. I is clearly illusraed ha once he pixel is rese he phoodiode volage sars o decrease due o he phoo-generaed curren. While sampling periodically he oupu of he comparaor, he complemen of he sae signal remains high unil he phoodiode volage crosses he reference volage. Figure 19. Measuremen resuls of key elecrical signals. Rese, Vpd, Wbl and Rbl are he rese signal, he phoodiode volage, he righ bi line signal and he read bi line signal, respecively. Table 2 summarizes he main characerisics of he proposed implemenaion compared o previous 6-T SRAM based DPS implemenaions [7] and [2] using he same echnology node. The area of he

J. Low Power Elecron. Appl. 2011, 1 95 proposed pixel is 22 µm 22 µm and he fill facor is 20%, which could be furher improved wih he use of a single ended sensing scheme compared o he differenial one we used in his work. While he curren consumpion per pixel is improved compared o previous implemenaions, i is expeced ha furher benefis can be obained using power reducion echniques discussed in previous secions. Table 2. Comparison of key merics wih relaed work. This Work [7] [2] (Convenional) [4] Technology 0.35 µm 0.35 µm 0.35 µm 0.35 µm Supply volage 3.3 V 3.3 V 3.3 V 3.3 V Pixel area 22 µm 22 µm 30 µm 26 µm 45 µm 45µm 50 µm 50 µm Fill facor 20% 16% 12% 20% Pixel curren 1 µa N/A 1.6 µa N/A Transisor coun 25 32 91 38 Resoluion 4/8 bis 4/8 bis 8 bis 4/8 bis Frame/second 33 300 33 33 * Esimaed from he corresponding lieraure. 7. Conclusions Digial pixel sensors are promising archiecure for high speed image acquisiion, high dynamic range and high illuminaion image. However, he area occupied by he memory is a major drawback reducing he pixel sensiiviy o ligh. In his paper wo differen approaches were explored o reduce he area of he pixel memory. Firs approach is o reduce he memory requiremens by using he proposed muli-rese inegraion scheme. The second approach is o direcly improve he area of he sorage elemen using a 2T-DRAM cell insead of he area-consuming 6T-SRAM cell. To successfully implemen his concep, a new DPS archiecure was proposed. This DPS relies on a muli-rese inegraion scheme ha akes benefi from he chronological way he bis of he code are changing. Using his scheme, a four bi per pixel memory was employed making he design of 20% fill facor and 22 µm 22 µm digial pixel sensor possible. Considering he DPS archiecure for mobile applicaions, he power consumpion of he sensor is also of major concern. Deailed analysis of he power conribuors presened in his paper helped o idenify he main building blocks conribuing o power. The volage comparaor wihin each pixel is idenified as he boleneck in erms of power due o is large saic curren during he whole inegraion phase. Some power reducion echniques for fuure DPS implemenaions were also proposed and discussed in his paper. Acknowledgmen This work was suppored by a gran from he Research Gran Council (RGC) of Hong Kong SAR, China, CERG gran reference: 610509.

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