Sample and Hold (S/H)

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 8- 郭泰豪, Analog C Design, 07 Sample and Hold (S/H) Sample and Hold (often referred to as Track and hold (T/H)) dentical in both function & circuit implementation in most cases Only distinction: How they are used in the system S/H: Samples the input for a short time and stays in the hold mode for the remainder of the cycle T/H: Spends most of the time tracking the input and is switched into the hold mode for only brief interval n data acquisition systems operating at sampling rates greater than MHz The terms S/H and T/H lose their distinction n general: These two terms are used interchangeably Necessary components in many data-acquisition systems such as A/D converters n many cases, the use of a S/H can greatly minimize errors due to slightly different delay times in the internal operation of the converter

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 8- 郭泰豪, Analog C Design, 07 Performance Parameters in characterization of S/Hs Sampling pedestal or a hold step Error that occurs each time a sample and hold goes from sample mode to hold mode During this change in operation, there is always a small error in the voltage being held that makes it different from the input voltage at the time of sampling. Obviously, this error should be as small as possible. Perhaps more importantly, this error should be signal independent; otherwise it can introduce nonlinear distortion. How isolated the sampled signal is from the input signal during hold mode deally, the output voltage will no longer be affected by changes in the input voltage n reality, there is always some signal feedthrough, usually through parasitic capacitive coupling from the input to the output. n welldesigned sample and holds, this signal feedthrough can be greatly minimized.

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 8-3 郭泰豪, Analog C Design, 07 Performance Parameters in characterization of S/Hs(Cont.) The speed at which a sample and hold can track an input signal, when in sample mode. n this mode, a sample and hold will have both small-signal and large-signal limitations due to its -3dB bandwidth and finite slew rate, respectively. Both the -3dB bandwidth and slew rate should be maximized for high-speed operation. Droop rate in hold mode Somewhat less important in high-speed designs This error is a slow change in output voltage, when in hold mode, caused by effects such as leakage currents due to the finite base currents of bipolar transistors and reverse-biased junctions. n most CMOS designs expect using advanced processes, this droop rate is so small it can often be ignored.

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 8-4 郭泰豪, Analog C Design, 07 Performance Parameters in characterization of S/Hs(Cont.) Aperture jitter or aperture uncertainty Result of the effective sampling time changing from one sampling instance to the next More pronounced for high-speed signals. Specifically, when highspeed signals are being sampled, the input signal changes rapidly, resulting in small amounts of aperture uncertainty causing the held voltage to be significantly different from the ideal held voltage. Other parameters such as Dynamic range Linearity Gain Offset error Etc.

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 8-5 郭泰豪, Analog C Design, 07 Testing S/Hs Beat test, a popular method for testing S/Hs Test setup in A in sin[ (f smpl Beat frequency Output signal with frequency f f )t] S/H Clk f smpl Spectrum analyzer A/D and computer Sampling signal with sampling frequency f smpl Where the S/H is operating at it s maximum sampling frequency Only a relatively low-frequency output signal must be monitored.

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 8-6 郭泰豪, Analog C Design, 07 Testing S/Hs (Cont.) Example waveforms for the above test setup Output signal of sample and hold nput signal Sampling signal The ideal sinusoidal wave at the beat frequency is subtracted from the measured signal. The error signal is then analyzed for RMS content and spectral components using FFT (Fast Fourier Transform).

Two error sources due to switch a. channel charge injection b. clock feedthrough where b is usually smaller than a. Time jitter MOS S/H Basics in Caused by clock waveforms having finite slopes clk CM th ts actual in clk ts ideal tsideal tsactual th Sampling jitter When in is above 0, the true sampling time is earlier than the ideal sampling time. When in is less than 0, the true sampling time is late. Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 8-7 郭泰豪, Analog C Design, 07

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 8-8 郭泰豪, Analog C Design, 07 Methods for Minimizing Signal-Dependent Switch Error Replace n-channel switches by CMOS transmission gates. Transistor turn-off times are signal dependent and this signal dependence causes the n-channel transistor to turn off at different times than the p-channel transistor. PMOS and NMOS have different amount of channel charges, e.g., when in is closer to DD, the charge from the p-channel transistor is greater than that from the n-channel transistor Add a dummy switch (better with fast clock) When clock waveforms are fast, this Q Q in technique usually can minimize the W,L W, L hold pedestal to less than about one-fifth the value it would have without it. The clock of Q changes slightly after that of Q. This guarantees that the cancelling charge of Q can t escape through Q. in clk clk clk clk CM CM

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 8-9 郭泰豪, Analog C Design, 07 Methods for Minimizing Signal-Dependent Switch Error(Cont.) nclude an OPAMP in a feedback loop of a S/H High input impedance The speed of operation can be seriously degraded due to the necessity of guaranteeing that the loop is stable when it is closed. When in hold mode, the OPAMP is open loop, resulting in its output almost certainly saturating at one of the power supply voltages. When the S/H goes back into track mode, it will take some time for the OPAMP output to slew back to its correct closed-loop value. This slewing time can be greatly minimized by adding two additional transistors in in clk Q Q clk clk C hld Q clk C hld CM Q 3 out out CM

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 8-0 郭泰豪, Analog C Design, 07 Methods for Minimizing Signal-Dependent Switch Error(Cont.) A feedback S/H with a Miller capacitor as a holding capacitor. The voltages on both sides of switch Q are very nearly signal independent. Charge injection results in just a dc offset and will be signal independent. The use of Q greatly speeds up the time it takes the S/H to return to track mode. The use of Q also greatly minimizes signal feedthrough when the S/H is in hold mode. There are two OPAMPs in the loop. Speed is degraded. Opamp clk Chld in clk Q Q Opamp out CM CM

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 8- 郭泰豪, Analog C Design, 07 Methods for Minimizing Signal-Dependent Switch Error(Cont.) A feedback S/H with clock-feedthrough cancellation circuitry To match charge injection by introducing C hld (=C hld ) The major limitation is a second-order effect caused by a mismatch in impedance levels at the left of Q and the bottom of Q. in Opamp clk Q 3 Q clk clk Q Chld Opamp C' hld C hld out CM CM CM

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 8- 郭泰豪, Analog C Design, 07 CMOS Multiplier Circuit CMOS differential pair can be employed in a multiplier circuit [][] Assume: Ma, Mb are identical in saturation region, the drain current is given by k( D GS TH ) we have Ma where Mb k( SS 0.5v Ma X i) k( 0.5v Mb X i) X CM S TH CM + 0.5v i CM - 0.5v i v i Ma Ma s Mb Mb SS Ma SS kv i k SS v i, Mb SS kv i k SS v i - - - - - - () Ma Mb kv i k SS v i - - - - - - - - - - - - - - - - - - - - - - ()

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 8-3 郭泰豪, Analog C Design, 07 CMOS Multiplier Circuit (Cont.) This MOS version of Gilbert s six-transistor cell is the basic multiplier. v x and v y can be made positive or negative: Four-quadrant multiplier 7 8 CM - 0.5v x v x M3 M4 M5 M6 CM + 0.5v x CM + 0.5v y M M CM - 0.5v y v y SS

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 8-4 郭泰豪, Analog C Design, 07 CMOS Multiplier Circuit (Cont.) Define: input signal v x and v y, the output current out = 7-8 ( ) ( ) ( ) ( ) out 7 8 M3 M5 M4 M6 M3 M4 M6 M5 Refer to 8-, equation () M SS kv y k SS v y, SS y SS M v y Refer to 8-, equation () and assuming v x is sufficient small kv k SS SS v SS y vy M 3 M4 kvx vy vy vx kvx ( ) k k k SS SS v SS y vy M 6 M5 kvx vy vy vx kvx ( ) out ( M3 M4 k ) ( M6 M5 k ) kv References: []J. N. Babanezhad and G. C. Temes, A 0- four-quadrant CMOS analog multiplier, EEE J. Solid-State Circuits, vol. SC-0, pp.58-68, Dec. 985. []Gunhee Han and Edgar Sanchez-Sinencio, CMOS Transconductance Multipliers: A Tutorial, EEE Trans. Circuit Syst., vol. 45, pp.550-563, Dec. 998. x v y k

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 8-5 郭泰豪, Analog C Design, 07 oltage and Current References Circuits that yield a precise DC voltage or current independent of external influences are called voltage references( ref ) or current references ( ref ) Two major specs on ref and ref Temperature Coefficient Power Supply Sensitivity

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 8-6 郭泰豪, Analog C Design, 07 Power Supply Sensitivity of ref / ref The sensitivity of ref to change in a power supply xx ( DD or GND) is given as: S lim 0 / / Once S is known, we obtain S Besides, S and can be similarly obtained

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 8-7 郭泰豪, Analog C Design, 07 Temperature Coefficient of / TC ST ; T T TC T S T T Examples(resistor divider): oltage Sensitivity R R R S Temperature Coefficient TC T xx T R R R R R xx R R R T R R R R T R T R RR R R R T R R T f TC(R )=TC(R ), then TC( )=0

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 8-8 郭泰豪, Analog C Design, 07 Supply ndependent Current Source Neglecting base current N S cc BE / R Assuming CC >> BE CC BE/ R S cc CC CC CC t R t R t / Rln N / S CC RS BE RS R CC Q N BE Q R

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 8-9 郭泰豪, Analog C Design, 07 Breakdown diodes and pn junction diodes(or transistor connected diodes) have opposite temperature coefficients. R z 3BE BE R R R R R o Z BE BE R R R R R R Let Reducing TC( ) by using the combination of Breakdown diode and pn diode Assuming then T z T T R R BE 0 R R, then z T 3.5 3m and o C and T.4 BE m o C Z D D Q R R

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 8-0 郭泰豪, Analog C Design, 07 Bandgap oltage Reference Model CC BE( on ) T kt q m / o C o 3300 ppm / C 0. 085 m / o C T T BE( on ) Sum ref BE(on) G T T generator T G GT Rough calculation BE has a temperature coefficient of m/ o c at room temperature T has a temperature coefficient of 0.085 m/ o c = BE +G T Assuming BE =0.65, then G=3.5 & =.6 =>TC=0

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 8- 郭泰豪, Analog C Design, 07 Bandgap oltage Reference (Cont.) The most popular approach to realize voltage reference for CMOS and bipolar Cs Cancelling the negative temperature dependence of a pn junction with a positive temperature dependence from a PTAT(proportional-toabsolute-temperature) circuit Accurate calculation A forward-biased base-emitter junction of a bipolar transistor has an - relationship given by qbe C S e kt where s is the transistor scale (reverse saturation) current and, although not shown, has a strong dependence on temperature. Writing the base-emitter voltage as a function of collector current and temperature, it can be shown that [Brugler, 967; Tsividis, 980] BE T T T mkt T0 kt JC G0 BE0 ln ln T0 T0 q T q JC0

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 8- 郭泰豪, Analog C Design, 07 Bandgap oltage Reference(Cont.) Here, G0 is the bandgap voltage of silicon extrapolated to 0 o k (approximately.06), k is Boltzmann s constant, and m is a temperature constant approximately equal to.3. Also, J C and T are the collector current density and temperature, respectively, while the subscript 0 designates an appropriate quantity at a reference temperature, T 0. Specifically, J C0 is the collector current density at the reference temperature, T 0, whereas J C is the collector current density at the true temperature, T. Also, BE0 is the junction voltage at the reference temperature, T 0, whereas BE is the base-emitter junction voltage at the true temperature, T. ref T BE G0 T G T kt q T T 0 m ln if G is properly taken

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 8-3 郭泰豪, Analog C Design, 07 Bandgap oltage Reference(Cont.) ref.90.80 ( a ) To 400 o K.70 ( b ) To 300 o K T ref 0 T ref 0.60.50.40 ( c ) 60 40 0 To 00 0 T ref o 0 K 0 40 60 80 00 0 T o C Temperature coefficient T T ref 0 k q T T m ln

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 8-4 郭泰豪, Analog C Design, 07 Bipolar Bandgap oltage Reference Q Q R DD R Q 4 Q3 BE R Q5 R Q6 E From S S3 BE4 t S4e and Se BE BE4 R BE BE4 R Sexp S t S3 BE4 S4exp t SS4 R tln SS3 S6 BE ER BE R S3 R S6 BE R R S3 R S6 SS4 BE tln R S3 SS3 t S S4 exp R t

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 8-5 郭泰豪, Analog C Design, 07 CMOS Bandgap oltage Reference Operating in Weak nversion A CMOS bandgap voltage reference operating in weak inversion Operational principle: nitial loop gain is greater than loop current increases Equilibrium is achieved when the loop gain is reduced to one by the voltage R across R R SS t ln SS 4 3 BE R R S S 6 3 SS t ln SS 4 3

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 8-6 郭泰豪, Analog C Design, 07 CMOS Bandgap oltage Reference Operating in Weak nversion (Cont.) Weak inversion (- is similar to bipolar) log DS DS GS GS near off weak on strong inversion inversion DS where W L D0 t exp kt q Parasitic bipolar transistor is needed. (Example with N-well process) BS and nt Th is t exp threshold DS voltage t exp GS nt Th p+ n-well p-substrate

CMOS Bandgap oltage Reference Operating in Weak nversion (Cont.) Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 8-7 郭泰豪, Analog C Design, 07 CMOS circuit M M R DD M3 M4 R R BE M6 R Q5 f BS DS t W L W L W L W L DS M M3 M M4 BS4 W L W L D0 D0, D0 D0 exp exp BS if exp n exp n t GB channel effect is BS n t GB n t GB4 0, t Th Th th ignored BS4 length BS t BS t R BS4 t BS t n t GS modulation Th

CMOS Bandgap oltage Reference Operating in Weak nversion (Cont.) M M DD R M3 M4 R Precautions: R BE M6 R Q5 Let M and M 4 must be in weak inversion Leakage currents must be minimized R R Output resistance of the devices must be large to ensure good current mirrors. By using long channel devices or using various mirrors presented before. Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 8-8 郭泰豪, Analog C Design, 07 R W L S S 3 S BS4 S S BE 4 D0 D0 exp exp SS tln SS S S 6 3 4 3 n t n t GB GB4 Th Th SS tln SS 4 3 BS t BS4 t