Iteratioal Joural of Computer ad Electrical Egieerig, Vol. 5, o. 5, October 013 A Heuristic Method: Differetial Evolutio for Harmoic Reductio i Multilevel Iverter System P. Jamua ad C. Christober Asir Raja Abstract I this paper, Differetial Evolutio (DE) optimizatio techique is applied to determie optimum switchig agles for cascaded multilevel iverter topology with o equal dc sources for elimiatig pre specified order of harmoics while maitaiig the required fudametal voltage. This paper discusses briefly a efficiet Differetial Evolutio algorithm (DE) that reduces sigificatly the computatioal burde resultig i fast covergece. A objective fuctio describig a measure of effectiveess of elimiatig selected order of harmoics while cotrollig the fudametal compoet is derived. This techique ca be applied for ay umber of levels; as a example i this paper 7-level iverter with differet modulatio idices ad switchig agles are reported. The, these agles are used i simulatio to validate the results. Idex Terms RF MEMS, shut switch, dc ad rf characteristics, pull-i voltage, isertio loss, isolatio, sprig costat, youg s modulus, poisso s ratio. compoets o a output voltage wave are required for special applicatios. Specific harmoic compoet required for voltage active filter applicatios. This paper presets the performace of ew sigle phase multilevel iverter where its structure is totally differet from some iverter type i literature. The level umber ca be easily icreased [5]-[7]. As a result, voltage stress is reduced ad more siusoidal shaped output voltage waves ca be obtaied. The proposed iverter works perfectly for reductio of harmoic cotet ad also to maitai specific harmoic cotet for some applicatios. I this paper, Differetial Evolutio algorithm (DE) approach will be preseted, which solves the trascedetal equatios with a simpler formulatios ad with ay umber of levels without extesive derivatio of aalytical expressio. A multilevel iverter based o the cascaded coverter topology with o-equal dc sources is studied i Fig. 1. A accurate solutio is guarateed eve for a umber of switchig agles that is higher tha other techiques would be able to calculate for give equatios. I. ITRODUCTIO A multilevel iverter is a power electroic system that sythesis a desired voltage output from several levels of dc voltage as iput. The cascaded multilevel iverter cosists of a series of H-bridge iverter uits [1]-[3]. Multilevel iverters also have several advatages with respect to hard-switched two-level pulse width-modulatio (PWM)[4],adjustable-speed drives (ASDs). Motor damage ad failure have bee reported by idustry as a result of some ASD iverters high-voltage chage rates (dv/dt), which produced a commo-mode voltage across the motor widigs. High-frequecy switchig ca exacerbate the problem because of the umerous times this commo-mode voltage is impressed upo the motor each cycle. The mai problems reported have bee motor bearig failure ad motor widig isulatio breakdow because of circulatig currets, dielectric stresses, Voltage surge, ad coroa discharge. Multilevel iverters geerate a staircase waveform. By icreasig the umber of output levels, the output voltages have more steps ad harmoic cotet o the output voltage ad the THD values are reduced. Therefore, they produce high quality output voltage by icreasig the level umber. However, i some coditios, the harmoic Mauscript received March 14, 013; revised May 0, 013. P. Jamua is with the Electrical Egieerig Departmet, Sri Maakula Viayagar Egieerig College,Podicherry Uiversity, Puducherry.(e-mail: jamua1981@gmail.com) C. Christober Asir Raja is with the Electrical Egieerig Departmet, Podicherry Egieerig College, Podicherry Uiversity, Puducherry. (e-mail: asir_70@pec) Fig 1. Sigle phase structure of a cascaded multilevel iverter II. ASYMMETRICAL MULTILEVEL IVERTER Various multilevel iverters structures are reported i the techical literature, such as diode-clamp multilevel iverters(eutral-clamp), capacitor-clamp multilevel iverter(flyig capacitor), cascaded multi-cell with separate dc sources ad hybrid iverters that are derived from the above metioed topologies with the aim to reduce the amout of semicoductor elemets[3]. I this paper, the cascaded 7-level iverter cofiguratio is implemeted. It is formed by coectig several sigle phase H-bridge coverters i series as show i Fig. 1. A asymmetrical DOI: 10.7763/IJCEE.013.V5.758 48
Iteratioal Joural of Computer ad Electrical Egieerig, Vol. 5, o. 5, October 013 multilevel iverter ca be defied as a multilevel coverter fed by a set of dc-voltage source capacitor where at least oe of them is differet to the other oe. The seve level iverter with differet dc source, the circuit is show i Fig.. where, =1, 3, 5..-1(odd harmoics oly) = umber of switchig agles per quarter cycle, ad M =umber of dc sources. Equatio (3) has switchig agles where solutios for such equatios ca be obtaied by equatig -1 harmoics to zero ad assigig specific value to fudametal compoet. Solutios ca be obtaied through may iterative techiques such as ewto raphso method, Walsh fuctio, ad resultat theory or through miimizatio approach. I order to precede with miimizatio techique objective fuctio this reduces the pre- specified harmoics to zero while maitaiig the fudametal compoet is defied. Objective fuctio is defied as, F( 1,,... ) V1 cos( k ) A0 V cos(3 k )... VM cos(( 1) k ) k1 k1 k1 Fig.. Seve level iverter circuit Each coverter geerates a square wave voltage waveform with differet duty ratios, which together form the output voltage waveform as i Fig 3. A three phase cofiguratio ca be obtaied by coectig three of these coverters i Y or. For harmoic optimizatio, the switchig agles α 1, α ad α 3 show i Fig. 3 have to be selected so that certai order harmoics are elimiated [4], [6], [8]. The multilevel iverter used is Asymmetrical with biary cofiguratio where levels are idetified usig, Level, l = M+1-1 where, M= umber of dc sources or umber of H-bridge coected. Fig. 3. Geeralized stepped output waveform where as for 7-level iverter oly 3 rd ad 5 th harmoics are cosidered. Sice switchig agles are =3, -1 harmoics (3, 5) are equated to zero. Thus the objective fuctio becomes, (4) F( 1,, 3) V1 cos( k ) A0 V cos(3 k ) V3 cos(5 k ) k1 k1 k1 where k is the k th switchig agle, Mmi A 0 4 H 1 mi M V dc m is the modulatio idex which lies betwee (0 1), i ad H is the fudametal compoet. 1 The optimal switchig agles are obtaied by miimizig the equatio (4) by equatig to further costraits of equatio (5) ad this helps to elimiate the certai order of harmoics. (0 1... ) (5) m i III. PROBLEM FORMULATIO The output stepped voltage waveform is aalyzed usig Fourier theory is show below. Vout ( ) a0 a cos( ) b si( ) (1) 1,,.. Cosiderig the output waveform characteristics of odd ad half-wave symmetry, ow the equatio (1) becomes, V ( ) b si( ) () out where b is give by 1,3,5 4V b V cos( ) V cos( )... V cos( ) 1 dc 1 1 M 1,3,5 (3) IV. DIFFERETIAL EVOLUTIO (DE) Differetial Evolutio (DE) algorithm is a ew heuristic approach maily havig three advatages; fidig the true global miimum regardless of the iitial parameter values, fast covergece, ad usig few cotrol parameters. DE algorithm is a populatio based algorithm like geetic algorithms usig similar operators; crossover, mutatio ad selectio [9]. I this work, we have compared the performace of DE algorithm to that of some other well kow versios of geetic algorithms. It was observed that the covergece speed of DE is sigificatly better tha geetic algorithms [10]. Therefore DE algorithm seems to be a promisig approach for egieerig optimizatio problems. Evolutioary algorithm is explaied through block diagram show below (see Fig. 4): 483
Iteratioal Joural of Computer ad Electrical Egieerig, Vol. 5, o. 5, October 013 Fig. 4. Geeral procedure for evolutioary algorithm F (x +1 ) < F (x ), if so replace the origial values with ewly geerated values. 8) From step 4 to step 8 will be repeated util termiatio criteria is met, F (x ) <ε or > max. Flowchart (see Fig. 5): Mutatio is the process which is performed prior with the cotiuatio of recombiatio which is also said to be crossover. Fially best chromosomes are selected through selectio or reproductio process [11]. The steps ivolved i differetial evolutio techique are explaied below: 1) Iitialize the maximum umber of iteratios max, miimum cost value ε. ) Geerate iitial populatio radomly withi the rage. 3) Set iteratio =0. 4) Calculate cost fuctio f (x ) ad store the agles as base vector. 5) Form two duplicate matrices of switchig agles by shufflig the rows (p m1, p m ). 6) Mutate those values ad form a trial vector V +1 by the give formula, V +1 =base value + F. (p m1 p m ) where, F= scalar factor which should be less tha 1. 7) Perform crossover, assume 0<p c <1 where baby Y +1 is formed as per, Y +1 ={V +1, if rad< p c, base values, otherwise.} With the formed values calculate cost fuctio ad compare with previous fuctio values. Fig. 5. Flowchart for differetial evolutio Fig. 6. Output voltage waveform of seve level sigle phase iverter V. SIMULATIO AD RESULTS To implemet the proposed DE, a program was developed usig the software package MATLAB 7.5 [1]. With the ewly proposed iverter system, the algorithm is applied where some specified order of harmoics is reduced. It should be oted that the level of the dc sources are o-equal ad ca be measured. Furthermore, simulatios preseted cocer a sigle phase system. However, this does ot reduce the way the algorithm ca be applied i the three- phase system. The locatio of harmoics to be elimiated vary betwee the sigle ad three phase case sice the triple harmoics ca be elimiated by the coverter structure ad there is o eed to be icluded i the elimiatio process. The algorithm was used to fid the switchig agles for certai modulatio idex rage withi which solutio exists, i.e., 0.75 0.95. Fig. 6 shows the variatio of m i switchig agle vs. the modulatio idex. The covetioal optimizatio techique of ewto-raphso (R) has bee described i much literature. I differetial evolutio algorithm we have set 30 iteratios ad the degree of accuracy or haltig coditios is cosidered to be 0.00001. This differs from the covetioal method for the computatioal times ad as well as i THD values. This exhibits clearly that the proposed techique is more tha two times faster tha the covetioal method ewto-raphso. 484
Iteratioal Joural of Computer ad Electrical Egieerig, Vol. 5, o. 5, October 013 I this paper a quality factor chose as a performace idex to idicate the usefuless ad effectiveess of the method implemeted. The total harmoic distortio (THD) is a useful factor cosidered for the evaluatio of the iverter performace ad therefore THD is cosidered i this paper. After ruig the matlab codig for DE of modulatio idex 0.8, the output switchig agle is give below: 17.3593 9.4584 3 54.4846 Here 3 rd ad 5 th harmoics are 0.03% ad 0.06% with 100% fudametal voltage. The output waveform for 7-level iverter is show i the Fig. 6. Fig. 7 shows the variatio of switchig agle vs. the modulatio idex Fig. 8. shows the spectrum of output waveform where it has bee observed that low frequecy harmoics (3 rd ad 5 th ) has bee reduced. Fig. 9 depicts the variatio of THD with modulatio idex. Table I shows the switchig agles ad THD values for various modulatio idices. TABLE I: SIMULATED OUTPUTS FOR VARIOUS MODULATIO IDICES Fig. 7. Modulatio idex vs. switchig agle VI. COCLUSIO To geerate optimal switchig agles i order to elimiate a certai order of harmoics, a ew techique is itroduced i this paper. The differetial evolutio(de) is proposed to overcome the computatioal burde ad to esure the accuracy of the calculated agles. The algorithm was developed usig MATLAB software ad is ru for a umber of times idepedetly to esure the feasibility ad the quality of the solutio. Oly oe set of solutios is documeted ad plotted i this paper. The compariso of the results i this paper to similar work i the literature shows that the DE approach for the harmoic optimizatio of multilevel iverters work properly. The simulated output of switchig agles for various modulatio idex is show. DE ca be applied to ay problem where optimizatio is required; therefore, it ca be used i may applicatios i power electroics. Fig. 8. Spectrum of output voltage waveform Fig 9. Modulatio idex vs. total harmoic distortio REFERECES [1] J. Rodriguez, J. S. Lai, ad F. Z. Peg, Multilevel iverter: a survey of topologies, cotrol ad applicatio, IEEE trasactio o Idustrial Applicatio, vol. 49, o. 4, pp. 74-738, August 00. [] P. M. Bhagwat ad V. R. Stefaovic, Geeralized structure of a multilevel PWM iverter, IEEE Tras. o Idustry Applicatio, vol. 19, o. 6, pp. 1057-1069, ov./dec. 1983, [3] L. M. Tolbert, J.. Chiasso, D. Zhog, ad K. J. McKezie, Elimiatio of haromics i a multilevel coverter with oequal DC source, IEEE Trasactio o Idustry Applicatio, vol. 4, o. 1, pp. 75-8, Ja.-Feb. 005. [4] P.. Ejeti, P. D. Ziogas, ad J. F. Lidsay, Programmed PWM techiques to elimiate haromics: a critical evaluatio, IEEE Trasactio o Idustrial Applicatio, vol. 6, pp. 30-316, 1990 [5] J. M. Chiasso, L. M. Toblert, K. J. Mckezie, ad Z. Du Cotrol of a multilevel coverter usig resultat theory, IEEE Tras. o Cotrol System Techology, vol. 11, o. 3, pp. 345-354, May 000. [6] Z. Du, L. M. Tolbert, ad J.. Chiasso, Harmoic Elimiatio for Multilevel Coverter with programmed PWM Method, i Proc. Idustry applicatio coferece, 004, vol. 4, pp. 10-15. [7] T. H. Tag, J. G. Ha, ad X. Y. Ta, Selective Harmoic Elimiatio for a cascade Multilevel Iverter, Idustrial Electroics, 006 IEEE Iteratioal Symposium, vol., pp. 977-981. [8] M. E. Meral, L. Saribulut, A. Teke, ad M. Tumay, A ovel Switchig Sigals Geeratio Method For Hybrid Multilevel Iverters, 004. [9] D. Karaboga ad S. Okdum, A simple ad global optimizatio algorithm for egieerig problems: Differetial Evolutio Algorithm, Erciyes Uiversity, Kayseri-Turkey, 004 485
Iteratioal Joural of Computer ad Electrical Egieerig, Vol. 5, o. 5, October 013 [10] K. Fleetwood, A itroductio to Differetial Evolutio. [11] Differetial Evolutio-A simple heuristic for global optimizatio over cotiuous spaces, Joural of Global Optimizatio, vol. 11, pp. 341-359, 1997, kluwer academic publishers, prited i etherlad. [1] MATLAB 7.5 software package. [Olie]. Available: http://www.mathworks.com. P. Jamua was bor i 1981 ad received her B.Tech degree (Electrical ad Electroics) from Podicherry Egieerig College ad M.E. (Distictio.) degree (Power Electroics & Drives) from Govermet College of Egieerig, Salem. She is doig her research i the Podicherry Egieerig College Podicherry, Idia. She is curretly workig as assistat professor i the Electrical & Egieerig Departmet at Sri Maakula Viayagar Egieerig College, Podicherry, Idia. Her area of iterest is Power Electroics & Drives ad Power System C. Christober Asir Raja was bor i 1970 ad received his B.E. (Dist.) degree (Electrical ad Electroics) ad M.E. (Dist.) degree (Power System) from the Madurai Kamaraj Uiversity (1991 & 1996), Madurai, Idia. Ad he received his postgraduate degree i DI.S. (Dist.) from the Aamalai Uiversity, Chidambaram (1994). He received his Ph.D. i Power System from Aa Uiversity (001-004), Cheai, Idia. He published techical papers i Iteratioal & atioal Jourals ad Cofereces. He is curretly workig as Associate Professor i the Electrical Egieerig Departmet at Podicherry Egieerig College, Podicherry, Idia. His area of iterest is power system optimizatio, operatioal plaig ad cotrol. He acquired Member i ISTE ad MIE i Idia. 486