CHAPTER 7 - HIGH-PERFORMANCE CMOS OPERATIONAL AMPLIFIERS SECTION BUFFERED OP AMPS

CMOS Analog Circuit Design Page 7.01 CHAPTER 7 HIGHPERFORMANCE CMOS OPERATIONAL AMPLIFIERS Chapter Outline 7.1 Buffered Op Amps 7.2 HighSpeed/Frequency Op Amps 7.3 Differential Output Op Amps 7.4 Micropower Op Amp 7.5 LowNoise Op Amps 7.6 ILow Voltage Op Amps 7.7 Summary Goal To illustrate the degrees of freedom and choices of different circuit architectures that can enhance the performance of a given op amp. Differential Output Buffered High Frequency TwoStage Op Amp Low Power Low Noise Low Voltage Fig. 7.01 CMOS Analog Circuit Design Page 7.11 SECTION 7.1 BUFFERED OP AMPS What is a Buffered Op Amp? A buffered op amp is an op amp with a low value of output resistance, R o. Typically, 10Ω R o 1000Ω Requirements Generally the same as for the output amplifier: Low output resistance Large output signal swing Low distortion High efficiency Types of Buffered Op Amps Buffered op amps using MOSFETs With and without negative feedback Buffered op amps using BJTs

CMOS Analog Circuit Design Page 7.12 SourceFollower, PushPull Output Op Amp V T 2V OṈ M24 I Bias M5 M4 M23 1 R out = g m21 g 1000Ω, m22 Output bias current? M18M19M21M22 loop M1 M2 v in M8 M3 M11 M12 M13 M14 R 1 C c M15 M9 M10 V SG18 M16 M18 M19 V GS19 M17 I 17 I 20 M20 Buffer M22 V GS22 V SG21 M21 C L Fig. 7.11 Α v (0) = 65dB for I Bias = 50µA, and GB = 60MHz for C L = 1pF V SG18 V GS19 = V SG21 V GS22 which gives 2I 18 K P S 18 2I 19 K N S 19 = 2I 21 K P S 21 2I 22 K N S 22 CMOS Analog Circuit Design Page 7.13 CrossoverInverter, Buffer Stage Op Amp Principle: If the buffer has high output resistance and voltage gain (common source), this is okay if when loaded by a small R L the gain of this stage is approximately unity. 240 14 M3 100µA C 1 =8pF 144 14 M4 C 2 =5pF 240 14 2400 7.5 R L M1 M2 M5 v v in ' in 360 460 7.5 1400 7.5 14 Input stage Cross over stage Output Stage Fig. 7.12 This op amp is capable of delivering 160mW to a 100Ω load while only dissipating 7mW of quiescent power!

CMOS Analog Circuit Design Page 7.14 CrossoverInverter, Buffer Stage Op Amp Continued How does the output buffer work? The two inverters, M1M3 and M2M4 are designed to work over different regions of the buffer input voltage, v in. Consider the idealized voltage transfer characteristic of the crossover inverters: 240 14 100µA v in ' M3 C 1 =8pF M1 144 14 460 7.5 M4 C 2 =5pF M2 240 14 360 7.5 R L VDD M2 Active M1M3 Inverter M2 Saturated M1 Saturated Crossover voltage V C = V B V A 0 V C is designed to be small and positive for worst case variations in processing (Maximum value of V C 110mV) M2M4 Inverter M1 Active 0 V A V B v in' Fig. 7.13 CMOS Analog Circuit Design Page 7.15 CrossoverInverter, Buffer Stage Op Amp Continued Performance Results for the CrossoverInverter, Buffer Stage CMOS Op Amp Specification Supply Voltage Quiescent Power Output Swing (100Ω Load) OpenLoop Gain (100Ω Load) Unity Gainbandwidth Voltage Spectral Noise Density at 1kHz PSRR at 1kHz CMRR at 1kHz Input Offset Voltage (Typical) Performance ± 6 V 7 mw 8.1 Vpp 78.1 db 260kHz 1.7 µv/ Hz 55 db 42 db 10 mv

CMOS Analog Circuit Design Page 7.16 Compensation of Op Amps with Output Amplifiers Compensation of a threestage amplifier: This op amp introduces a third pole, p 3 (what about zeros?) With no compensation, V out (s) V in (s) = A vo s p 1 s 1 p 1 s 2 p 1 3 Illustration of compensation choices: v in Poles p 1 ' and p 2 ' v 2 Unbuffered op amp x1 Output stage Pole p 3 ' C L R L Fig. 7.14 jω jω p 2 Compensated poles Uncompensated poles p 3 ' p 2 ' p 1 ' p 1 σ p 2 p 3 = p 3 ' p 2 ' p 1 ' p 1 σ p 3 Miller compensation applied around both the second and the third stage. Miller compensation applied around the second stage only. Fig. 7.15 CMOS Analog Circuit Design Page 7.17 Low Output Resistance Op Amp To get low output resistance using MOSFETs, negative feedback must be used. Ideal implementation: v iin Gain Amplifier Error Amplifier Error Amplifier M2 i out C L M1 R L vout Fig. 7.15A Comments: The output resistance will be equal to r ds1 r ds2 divided by the loop gain If the error amplifiers are not perfectly matched, the bias current in M1 and M2 is not defined

CMOS Analog Circuit Design Page 7.18 Low Output Resistance Op Amp Continued Offset correction circuitry: vin C c M16 A1 M9 VBias M8 M17 A2 M8A M13 A M12 V OS Unbuffered op amp Error Loop M10 M11 Fig. 7.16 The feedback circuitry of the two error amplifiers tries to insure that the voltages in the loop sum to zero. Without the M9M12 feedback circuit, there is no way to adjust the output for any error in the loop. The circuit works as follows: When V OS is positive, tries to turn off and so does A. I M9 reduces thus reducing I M12. A reduction in I M12 reduces I M8A thus decreasing V GS8A. V GS8A ideally decreases by an amount equal to V OS. A similar result holds for negative offsets and offsets in EA2. CMOS Analog Circuit Design Page 7.19 Low Output Resistance Op Amp Continued Error amplifiers: M3 M4 Cc1 v in M1 M2 MR1 VBias M5 A1 amplifier A Fig. 7.17

CMOS Analog Circuit Design Page 7.110 Low Output Resistance Op Amp Complete Schematic v in VBiasN M16 C c M1 M2 M17 M5 MN3 MN4 M3H M4H MP4 M3 M4 MP5 M8 MP3 Compensation: Uses nulling Miller compensation. MR1 C c1 A M8A C c2 MR2 M9 MP4A MN5A M13 M12 M11 R C C C M10 MN4A MP3A MN3A M4HA M4A M2A M1A M5A VBiasP M3A M3HA Fig. 7.18 Short circuit protection: MP3MN3MN4MP4MP5 MN3AMP3AMP4AMN4AMN5A (max. output ±60mA) g m1 g m6 C 1 R 1 R L C L CMOS Analog Circuit Design Page 7.111 Low Output Resistance Op Amp Continued Table 7.12 Performance Characteristics of the Low Output Resistance Op Amp: Specification Simulated Results Measured Results Power Dissipation 7.0 mw 5.0 mw Open Loop Voltage Gain 82 db 83 db Unity Gainbandwidth 500kHz 420 khz Input Offset Voltage 0.4 mv 1 mv PSRR(0)/PSRR(0) 85 db/104 db 86 db/106 db PSRR(1kHz)/PSRR(1kHz) 81 db/98 db 80 db/98 db THD (Vin = 3.3Vpp) RL = 300Ω 0.03% 0.13%(1 khz) CL = 1000pF 0.08% 0.32%(4 khz) THD (Vin = 4.0Vpp) RL = 15KΩ 0.05% 0.13%(1 khz) CL = 200pF 0.16% 0.20%(4 khz) Settling Time (0.1%) 3 µs <5 µs Slew Rate 0.8 V/µs 0.6 V/µs 1/f Noise at 1kHz 130 nv/ Hz Broadband Noise 49 nv/ Hz R out r ds6 r ds6a Loop Gain 50kΩ 5000 = 10Ω

CMOS Analog Circuit Design Page 7.112 LowOutput Resistance Op Amp Continued Component sizes for the lowresistance op amp: Transistor/Capacitor µm/µm or pf Transistor/Capacitor µm/µm or pf M16 184/9 M8A 481/6 M17 66/12 M13 66/12 M8 184/6 M9 27/6 M1, M2 36/10 M10 6/22 M3, M4 194/6 M11 14/6 M3H, M4H 16/12 M12 140/6 M5 145/12 MP3 8/6 2647/6 MN3 244/6 MRC 48/10 MP4 43/12 CC 11.0 MN4 12/6 M1A, M2A 88/12 MP5 6/6 M3A, M4A 196/6 MN3A 6/6 M3HA, M4HA 10/12 MP3A 337/6 M5A 229/12 MN4A 24/12 A 2420/6 MP4A 20/12 CF 10.0 MN5A 6/6 CMOS Analog Circuit Design Page 7.113 Simpler Implementation of Negative Feedback to Achieve Low Output Resistance M8 M3 M4 200µA 10/1 1/1 1/1 10/1 M1 M2 v in 10/1 10/1 1/1 M5 M10 10/1 1/1 10/1 M9 C L Output Resistance: R o R out = 1LG where 1 R o = g ds6 g ds7 and LG = g m2 2g m4 (g m6 g m7 )R o Fig. 7.19 Therefore, the output resistance is 1 R out = g. m2 (g ds6 g ds7 ) 1 2g (g m4 m6 g m8 )R o

CMOS Analog Circuit Design Page 7.114 Example 7.11 Low Output Resistance Using the Simple Shunt Negative Feedback Buffer Find the output resistance of above op amp using the model parameters of Table 3.12. Solution The current flowing in the output transistors, and, is 1mA which gives R o of 1 R o = (λ N λ P )1mA = 1000 0.09 = 11.11kΩ To calculate the loop gain, we find that and g m2 = 2K N 10 100µA = 469µS g m4 = 2K P 1 100µA = 100µS g m6 = 2K P 10 1000µA = 1mS Therefore, the loop gain is LG = 469 100 2 11.11 = 104.2 Solving for the output resistance, R out, gives R out = 11.11kΩ 1 104.2 = 106Ω (Assumes that R L is large) CMOS Analog Circuit Design Page 7.115 BJTs Available in CMOS Technology Illustration of an NPN substrate BJT available in a pwell CMOS technology: Emitter Base Collector ( ) ;;;; n (Emitter) p ;n p well (Base) n substrate (Collector) Fig. 7.110 Base Collector( ) Emitter Comments: g m of the BJT is larger than the FET so that the output resistance w/o feedback is lower Can use the lateral or substrate BJT but since the collector is on ac ground, the substrate BJT is preferred Current is required to drive the BJT

CMOS Analog Circuit Design Page 7.116 TwoStage Op Amp with a ClassA BJT Output Buffer Stage Purpose of the M8M9 source follower: 1.) Reduce the output resistance (includes whatever is seen from the base to ground divided by 1β F ) 2.) Reduces the output load at the drains of and M12 M13 I Bias Smallsignal output resistance : r π10 (1/g m9 ) 1 1 R out 1ß = F g m10 g m9 (1ß F ) Output Buffer = 51.6Ω 6.7Ω = 58.3Ω where I 10 = 500µA, I 8 = 100µA, W 9 /L 9 =100 and ß F is 100 Maximum output voltage: v OUT (max) = V SD8 (sat) v BE10 = 2K P I 8 (W 8 /L 8 ) V t ln I c10 I s10 Voltage gain: v = g m1 g m6 g m9 g m10 R L in g ds2 g ds4 g ds6 g ds7 g m9 g mbs9 g ds8 g π10 1g m10 R L Compensation will be more complex because of the additional stages. vin M3 M1 M5 M2 M4 C c M9 M8 Q10 M11 C L Fig. 7.111 R L CMOS Analog Circuit Design Page 7.117 Example 7.12 Designing the ClassA, Buffered Op Amp Use the parameters of Table 3.12 along with the BJT parameters of I s = 10 14 A and ß F = 100 to design the classa, buffered op amp to give the following specifications. Assume the channel length is to be 1µm. = 2.5V = 2.5V A vd (0) 5000V/V Slew rate 10V/µs GB = 5MHz ICMR = 1V to 2V R out 100Ω C L = 100pF R L = 500Ω Solution Because the specifications above are similar to the twostage design of Ex. 6.31, we can use these results for the first two stages of our design. However, we must convert the results of Ex. 6.31 to a PMOS input stage. The results of doing this give W 1 /L 1 = W 2 /L 2 = 6µm/1µm, W 3 /L 3 = W 4 /L 4 = 7µm/1µm, W 5 /L 5 = 11µm/1µm, W 6 /L 6 = 43µm/1µm, and W 7 /L 7 = 34µm/1µm The design of the two followers is next. BJT follower: SR = 10V/µs and 100pF capacitor give I 11 = 1mA. If W 13 = 44µm, then W 11 = 44µm(1000µA/30µA) = 1467µm. I 11 = 1mA 1/g m10 = 0.0258V/1mA = 25.8Ω MOS follower: To source 1mA, the BJT must provide 2mA which requires 20µA from the MOS follower stage. Therefore, select a bias current of 100µA for M8. If W 12 = 44µm, then W 8 = 44µm(100µA/30µA) = 146µm.

CMOS Analog Circuit Design Page 7.118 Example 7.12 Continued If 1/g m10 is 25.8Ω, then design g m9 as 1 1 g m9 = 1 = (10025.8)(101) = 133.4µS g m9 and I 9 W/L = 0.809. R out g (1ß m10 F ) Let us select W/L = 10 for M9 in order to make sure that the contribution of M9 to the output resistance is sufficiently small and to increase the gain closer to unity. This gives a transconductance of M9 of 469µS. To calculate the voltage gain of the MOS follower we need to find g mbs9. This value is given as g m9 γ N g mbs9 = = 469 0.4 2 2φ F V BS9 2 0.72 = 57.1µS where we have assumed that the value of V SB9 is approximately 2V. 469µS A MOS = 469µS57.1µS4µS5µS = 0.8765 V/V. The voltage gain of the BJT follower is 500 A BJT = 25.8500 = 0.951 V/V Thus, the gain of the op amp is A vd (0) = (7777)(0.8765)(0.951) = 6483 V/V which meets the specification. The power dissipation of this amplifier is given as P diss. = 5V(30µA30µA95µA100µA1000µA) = 6.27mW CMOS Analog Circuit Design Page 7.119 TwoStage Op Amp with a ClassAB BJT Output Buffer Stage This amplifier can reduce the quiescent power dissipation. M10 vin M1 M5 M2 95µA C c 133µA Q8 Slew Rate: I Bias M3 M4 Output Buffer M9 C L R L Fig. 7.112 SR = I OUT C L = (1 β F)I 7 C L and SR = β 9( 1V V T0 )2 2C L If β F = 100, C L = 1000pF and I 7 = 95µA then SR = 8.59V/µs. Assuming a W 9 /L 9 = 60 (I 9 = 133µA), ±2.5V power supplies and C L = 1000pF gives SR = 35.9V/µs. (The current is not limited by I 7 as it is for the positive slew rate.)

CMOS Analog Circuit Design Page 7.120 TwoStage Op Amp with a ClassAB BJT Output Buffer Stage Smallsignal characteristics: C c C π Nodal equations: gmi V in R1 V 1 g R 2 miiv 2 V π V 2 R V 3 out g m8 V g m9 V 1 π Fig. 7.113 g mi V in = (G I sc c )V 1 sc c V 2 0V out 0 = (g mii sc c )V 1 (G II g π sc c sc π )V 2 (g π sc π )V out 0 g m9 V 1 (g m13 sc π )V 2 (g m13 sc π )V out where g π > G 3 The approximate voltage transfer function is: s V 9 (s) V in (s) A z 1 1 z 1 2 v0 s p 1 1 p 1 2 where A v0 = g mig mii 1 G I G z II 1 = C C c π g mii g 1 g m9 m13 g mii p 1 = G IG II g mii C c 1 g m9 1 β F g C π mii C G I G II c g m13 g mii g m13 z 2 = C g mii π C 1 g m9 c g mii g m13 g mii p 2 (g mii g m9 )C π CMOS Analog Circuit Design Page 7.121 TwoStage Op Amp with a ClassAB BJT Output Buffer Stage Continued Output stage current, I C8 : I C8 = I D9 = S 9 S I 6 D6 = 60 43 95µA = 133µA Smallsignal output resistance: r out = r π R II 1 β F = 19.668kΩ 116.96kΩ 101 =1353Ω if I 6 =I 7 = 95µA, and β F = 100. Loading effect of R L on the voltage transfer curve (increasing W 9 /L 9 will improve the negative part at the cost of power dissipation): 2 1 vout (Volts) 0 1 R L = 1000Ω R L = 100Ω R L =50Ω 2 3 2 1.5 1 0.5 0 0.5 1 1.5 2 v IN (Volts) Fig. 7.114A

CMOS Analog Circuit Design Page 7.122 Example 7.13 Performance of the TwoStage, Class AB Output Buffer Using the transistor currents given above for the output stages (output stage of the twostage op amp and the buffer stage), find the smallsignal output resistance and the maximum output voltage when R L = 50Ω. Use the W/L values of Example 7.12 and assume that the NPN BJT has the parameters of ß F = 100 and I S = 10fA. Solution It was shown on the previous slide that the smallsignal output resistance is r π r ds6 r ds7 19.668kΩ 116.96kΩ r out = 1ß = F 101 = 1353Ω Obviously, the MOS buffer of Fig. 7.111 would decrease this value. The maximum output voltage given previously is only valid if the load current is small. If this is not the case, then a better approach is to assume that all of the current in becomes base current for Q8. This base current is multiplied by 1ß F to give the sourcing current. If M9 is off, then all this current flows through the load resistor to give an output voltage of v OUT (max) (1ß F )I 7 R L If the value of v OUT (max) is close to, then the sourcedrain voltage across may be too small to be in saturation causing I 7 to decrease. Using the above equation, we calculate v OUT (max) as (101) 95µA 50Ω or 0.48V which is close to the simulation results shown using the parameters of Table 3.12. CMOS Analog Circuit Design Page 7.21 SECTION 7.2 HIGHSPEED/FREQUENCY OP AMPS Objective Explore op amps having high frequency response and/or high slew rate Approaches 1.) Extending the GB of conventional op amps 2.) Switched op amps 3.) Current feedback op amps 4.) Parallel path op amps

CMOS Analog Circuit Design Page 7.22 What is the Influence of GB on the Frequency Response? The op amp is primarily designed to be used with negative feedback. When the product of the op amp gain and feedback gain (loss) is not greater than unity, negative feedback does not work satisfactorily. Example of a gain of 10 voltage amplifier: Magnitude Avd(0) db Op amp frequency response Amplifier with a gain of 10 20dB 0dB ω A ω 3dB GB log 10 (ω) Fig. 7.21 What causes the GB? We know that GB = g m C where g m is the transconductance that converts the input voltage to current and C is the capacitor that causes the dominant pole. This relationship assumes that all higherorder poles are greater than GB. CMOS Analog Circuit Design Page 7.23 What is the Limit of GB? The following illustrates what happens when the next higher pole is not greater than GB: Magnitude Avd(0) db Op amp frequency response Amplifier with a gain of 10 20dB 40dB/dec Next higher pole 0dB ω A ω 3dB GB For a twostage op amp, the poles and zeros are: log 10 (ω) Fig. 7.22 1.) Dominant pole p 1 = g m1 A v (0)C c 2.) Output pole p 2 = g m6 C L 3.) Mirror pole p 3 = g m3 C gs3 C gs4 4.) Nulling pole 1 p 4 = R z C I 5.) Nulling zero 1 z 1 = R z C c (C c /g m6 )

CMOS Analog Circuit Design Page 7.24 A Procedure to Increase the GB of a TwoStage Op Amp 1.) Use the nulling zero to cancel the closest pole beyond the dominant pole. 2.) The maximum GB would be equal to the magnitude of the second closest pole beyond the dominant pole. 3.) Adjust the dominant pole so that GB 2.2x(second closest pole beyond the dominant pole) Illustration which assumes that p 2 is the next closest pole beyond the dominant pole: Avd(0) db Magnitude 0dB Fig. 7.23 p 3 p 4 p 2 = z 1 Old GB GB Increase Old New p 1 p p 2 1 40dB/dec 60dB/dec 80dB/dec New GB p 4 p 3 p 1 New jω p 1 Old log 10 (ω) σ Before cancelling p 2 by z1 and increasing p 1 CMOS Analog Circuit Design Page 7.25 Example 7.21 Increasing the GB of the TwoStage Op Amp Designed in Ex. 6.31 Use the twostage op amp designed in Example 6.31 and apply the above approach to increase the gainbandwidth as much as possible. Solution 1.) We must first find the values of p 2, p 3, and p 4. (a.) From Ex. 6.32, we see that p 2 = 94.25x10 6 rads/sec. (b.) p 3 was found in Ex. 6.31 as 2.81x10 9 rads/sec. (c.) To find p 4, we must find C I 30µA 4.5µm 1µm which is the output capacitance of the first stage of the op amp. C I consists of the following capacitors, C I = C bd2 C bd4 C gs6 C gd2 C gd4 v in M8 For C bd2 the width is 3µm L1L2L3 = 3µm AS/AD=9µm 2 and PS/PD = 12µm. For C bd4 the width is 15µm L1L2L3 = 3µm AS/AD=45µm 2 and PS/PD = 36µm. From Table 3.21: C bd2 = (9µm 2 )(770x10 6 F/m 2 ) (12µm)(380x10 12 F/m) = 6.93fF4.56fF = 11.5fF and C bd4 = (45µm 2 )(560x10 6 F/m 2 ) (36µm)(350x10 12 F/m) = 25.2fF12.6F 37.8fF 15µm 1µm M1 M3 3µm 1µm M5 = 2.5V M4 15µm 1µm 3µm 1µm 30µA 4.5µm 1µm M2 = 2.5V R z C c = 3pF 95µA 94µm 1µm 14µm 1µm C L = 10pF Fig. 7.23A

CMOS Analog Circuit Design Page 7.26 Example 7.21 Continued C gs6 is given by Eq. (10b) of Sec. 3.2 and is C gs6 = CGDOxW 6 0.67(C ox W 6 L 6 ) = (220x10 12 )(94x10 6 ) (0.67)(24.7x10 4 )(94x10 12 ) = 20.7fF 154.8fF = 175.5fF C gd2 = 220x10 12 x3µm = 0.66fF and C gd4 = 220x10 12 x15µm = 3.3fF Therefore, C I = 11.5fF 37.8fF 175.5fF 0.66fF 3.3fF = 228.8fF. Although C bd2 and C bd4 will be reduced with a reverse bias, let us use these values to provide a margin. In fact, we probably ought to double the whole capacitance to make sure that other layout parasitics are included. Thus let C I be 300fF. In Ex. 6.32, R z was 4.591kΩ which gives p 4 = 0.726x10 9 rads/sec. 2.) Using the nulling zero, z 1, to cancel p 2, gives p 4 as the next smallest pole. For 60 phase margin GB = p 4 /2.2 if the next smallest pole is more than 10GB (which is approximately true). GB = 0.726x10 9 /2.2 = 0.330x10 9 rads/sec. or 52.5MHz. The compensating capacitor or g m1 (g m2 ) is designed from the relationship that GB = g m1 /C c to give this value of GB. Assuming g m1 is constant, then C c = g m1 /GB = (94.25x10 6 )/(0.330x10 9 ) = 286fF. It might be useful to increase g m1 in order to increase C c above the surrounding parasitic capacitors. However, let us assume that this value of C c is suitable (C gd6 = 20.7fF). Therefore the new GB is 52.5MHz. We have increased the GB from Example 6.31 by a factor of 10.5 times. The success of this method assumes that there are no other roots with a magnitude smaller than 10GB. CMOS Analog Circuit Design Page 7.27 Example 7.22 Increasing the GB of the Folded Cascode Op Amp of Ex. 6.53 Use the foldedcascode op amp designed in V Example 6.53 and apply the above approach to increase DD the gainbandwidth as much as possible. Assume that the drain/source areas are equal to 2µm times the width of the M14 M4 I 4 M5 I 5 transistor and that all voltage dependent capacitors are at A zero voltage. B R A R B Solution I 1 I 2 The poles of the folded cascode op amp are: M13 I 6 I7 1 M1 M2 R 1 p A R A C (the pole at the source of ) A v in 1 R 2 p B R B C (the pole at the source of ) B I 3 M8 M9 1 p 6 (R 2 1/g m10 )C (the pole at the drain of ) 6 M3 M12 VBias M10 M11 1 p 8 C 8 (r ds2 r ds4 r ds10 ) (the pole at the source of M8 ) p 9 g m9 C (the pole at the source of M9) 9 and g m10 p 10 C (the pole at the gates of M10 and M11) 10 Let us evaluate each of these poles. 1,) For p A, the resistance R A is approximately equal to g m6 and C A is given as C A = C gs6 C bd1 C gd1 C bd4 C bs6 C gd4 C L Fig. 6.57

CMOS Analog Circuit Design Page 7.28 Example 7.22 Continued From Ex. 6.53, g m6 = 744.6µS and capacitors giving C A are found using the parameters of Table 3.21 as, C gs6 = (220x10 12 80x106 ) (0.67)(80x10 6 106 24.7x104 ) = 149fF C bd1 = (770x10 6 )(35.9x10 6 2x106 ) (380x10 12 )(2 37.9x10 6 ) = 84fF C gd1 = (220x10 12 35.9x106 ) = 8fF C bd4 = C bs6 = (560x10 6) (80x10 6 2x106 ) (350x10 12 )(2 82x10 6 ) = 147fF and C gd4 = (220x10 12 )(80x10 6 ) = 17.6fF Therefore, C A = 149fF 84fF 8fF 147fF 17.6fF 147fF = 0.553pF Thus, p A = 744.6x106 0.553x10 12 = 1.346x109 rads/sec. 2.) For the pole, p B, the capacitance connected to this node is C B = C gd2 C bd2 C gs7 C gd5 C bd5 The various capacitors above are found as C gd2 = (220x10 12 35.9x106 ) = 8fF C bd2 = (770x10 6 )(35.9x10 6 2x106 ) (380x10 12 )(2 37.9x10 6 ) = 84fF C gs7 = (220x10 12 80x106 ) (0.67)(80x10 6 106 24.7x104 ) = 149fF C gd5 = (220x10 12 )(80x10 6 ) = 17.6fF and C bd5 = (560x10 6) (80x10 6 2x106 ) (350x10 12 )(2 82x10 6 ) = 147fF CMOS Analog Circuit Design Page 7.29 Example 7.22 Continued The value of C B is the same as C A and g m6 is assumed to be the same as g m7 giving p B = p A = 1.346x10 9 rads/sec. 3.) For the pole, p 6, the capacitance connected to this node is C 6 = C bd6 C gd6 C gs8 C gs9 The various capacitors above are found as C bd6 = (560x10 6 )(80x10 6 2x106 ) (350x10 12 )(2 82x10 6 ) = 147fF C gs8 = (220x10 12 36.4x106 ) (0.67)(36.4x10 6 106 24.7x104 ) = 67.9fF and C gs9 = C gs8 = 67.9fF C gd6 = C gd5 = 17.6fF Therefore, C 6 = 147fF 17.6fF 67.9fF 67.9fF= 0.300pF From Ex. 6.53, R 2 = 2kΩ and g m6 = 744.6x10 6. Therefore, p 6, can be expressed as 1 p 6 = 2x10 3 106 = 0.966x10 9 rads/sec. 744.6 0.300x1012 4.) Next, we consider the pole, p 8. The capacitance connected to this node is C 8 = C bd10 C gd10 C gs8 C bs8 These capacitors are given as, C bs8 = C bd10 = (770x10 6 )(36.4x10 6 2x106 ) (380x10 12 )(2 38.4x10 6 ) = 85.2fF C gs8 = (220x10 12 36.4x106 ) (0.67)(36.4x10 6 106 24.7x104 ) = 67.9fF and C gd10 = (220x10 12 )(36.4x10 6 ) = 8fF

CMOS Analog Circuit Design Page 7.210 Example 7.22 Continued The capacitance C 8 is equal to C 8 = 67.9fF 8fF 85.2fF 85.2fF = 0.246pF Using the value of gm8 found in Ex. 6.53 of 774.6µS, the pole p 8 is found as, p 8 = 3.149x10 9 rads/sec. 5.) The capacitance for the pole at p 9 is identical with C 8. Therefore, since g m9 is also 774.6µS, the pole p 9 is equal to p 8 and found to be p 9 = 3.149x109 rads/sec. 6.) Finally, the capacitance associated with p 10 is given as C 10 = C gs10 C gs11 C bd8 These capacitors are given as C gs10 = C gs11 = (220x10 12 36.4x106 ) (0.67)(36.4x10 6 106 24.7x104 ) = 67.9fF and C bd8 = (770x10 6 )(36.4x10 6 2x106 ) (380x10 12 )(2 38.4x10 6 ) = 85.2fF Therefore, C 10 = 67.9fF 67.9fF 85.2fF = 0.221pF which gives the pole p 10 as 744.6x10 6 /0.246x10 12 = 3.505x10 9 rads/sec. The poles are summarized below: p A = 1.346x109 rads/sec p B = 1.346x109 rads/sec p 6 = 0.966x109 rads/sec p 8 = 3.149x109 rads/sec p 9 = 3.149x109 rads/sec p 10 = 3.505x109 rads/sec CMOS Analog Circuit Design Page 7.211 Example 7.22 Continued The smallest of these poles is p 6. Since p A and p B are not much larger than p 6, we will find the new GB by dividing p 6 by 5 (rather than 2.2) to get 200x10 6 rads/sec. Thus the new GB will be 200/2π or 32MHz. The magnitude of the dominant pole is given as p dominant = GB A vd (0) = 200x106 7,464 = 26,795 rads/sec. The value of load capacitor that will give this pole is 1 1 C L = p = dominant R out 26.795x10 1.9pF 3 19.4MΩ Thus, the load capacitor of the folded cascode op amp of Ex. 6.53 can be reduced to 1.9pF without sacrificing the phase margin. This corresponds to a new unitygainbandwidth of 32 MHz compared with the old unitygainbandwidth of 10 MHz..

CMOS Analog Circuit Design Page 7.212 Conclusion for Increasing the GB of Op Amps Maximum GB depends on the input transconductance and the capacitance that causes the dominant pole. Quantity MOSFET Op Amp BJT Op Amp g m dependence W 2K L I I C D kt/q = I C V t Maximum g m 1 ma/v 20 ma/v GB for 10pF 15 MHz 300 MHz GB for 1pF 150 MHz 3 GHz Note that the power dissipation will be large for large GB because current is needed for large g m. Assumption: All higherorder roots are above GB. The larger GB, the more difficult this becomes. Conclusion: The best CMOS op amps have a GB of 1050MHz The best BJT op amps have a GB of 100200MHz CMOS Analog Circuit Design Page 7.213 Switched Amplifiers Switched amplifiers are time varying circuits that yield circuits with smaller parasitic capacitors and therefore higher frequency response. Such circuits are called dynamically biased. Switched amplifiers require a nonoverlapping clock Switched amplifiers only work during a portion of a clock period Bias conditions are setup on one clock phase and then maintained by capacitance on the active phase Switched amplifiers use switches and capacitors resulting in feedthrough problems Simplified circuits on the active phase minimize the parasitics Typical clock: φ 1 φ 2 t T t T 0 0.5 1 1.5 2 Fig. 7.23B

CMOS Analog Circuit Design Page 7.214 Dynamically Biased Inverting Amplifier C B φ 1 φ 1 M2 I D v in φ 2 C OS M1 φ 1 Fig. 7.24 During phase 1 the offset and bias of the inverter is sampled and applied to C OS and C B. During phase 2 C OS is connected in series with the input and provides offset canceling plus bias for M1. C B provides the bias for M2. (This circuit illustrates the concept of switched amplifiers but is too simple to illustrate the reduction of bias parasitics.) CMOS Analog Circuit Design Page 7.215 Dynamically Biased, PushPull, Cascode Op Amp M8 V B2 φ 1 φ 2 M4 I B v in φ 2 C 1 φ 1 v in M3 C 2 M2 M5 V B1 φ 1 φ 2 M1 Fig.7.25 Pushpull, cascode amplifier: M1M2 and M3M4 Bias circuitry: M5C 2 and M8C 1 Parasitics can be further reduced by using a doublepoly process to eliminate bulkdrain and bulksource capacitances at the drain of M1source of M2 and drain of M4source of M3 (see Fig. 6.55).

CMOS Analog Circuit Design Page 7.216 Dynamically Biased, PushPull, Cascode Op Amp Continued Operation: M8 V B2 V B2 (v in v in ) M4 I B C 1 C 2 V B2 v in v in v in V B1 V B2 v in v in vin V B1 C 1 C 2 M3 M2 M5 V B1 Equivalent circuit during the φ 1 clock period V B1 (v in v in ) M1 Equivalent circuit during the φ 2 clock period. Fig. 7.26 CMOS Analog Circuit Design Page 7.217 Dynamically Biased, PushPull, Cascode Op Amp Continued This circuit will operate on both clock phases. V B2 M8 φ 2 φ 1 φ 1 φ 2 M4 Performance (1.5µm CMOS): 1.6mW dissipation GB 130MHz (C L = 2.2pF) Settling time of 10ns (C L = 10pF) φ C 1 2 C 4 φ 2 v in v in I B φ 2 φ 1 M3 M5 V B1 C 1 C 3 φ 2 φ 1 φ 1 φ 2 M2 M1 Fig. 7.27 This amplifier was used with a 28.6MHz clock to realize a 5thorder switched capacitor filter having a cutoff frequency of 3.5MHz. S. Masuda, et. al., CMOS Sampled Differential PushPull Cascode Op Amp, Proc. of 1984 International Symposium on Circuits and Systems, Montreal, Canada, May 1984, pp. 12111214.

CMOS Analog Circuit Design Page 7.218 Current Feedback Op Amps Why current feedback: Higher GB Less voltage swing more dynamic range What is a current amplifier? R i2 i 2 i 1 i o R o Requirements: i o = A i (i 1 i 2 ) R i1 Current Amplifier Fig. 7.28A R i1 = R i2 = 0Ω R o = Ideal source and load requirements: R source = R Load = 0Ω CMOS Analog Circuit Design Page 7.219 Bandwidth Advantage of a Current Feedback Amplifier Consider the inverting voltage amplifier shown using a current amplifier with negative current feedback: v in R 1 i in i 2 R 2 io i 1 Current Voltage Fig. 7.29 Amplifier Buffer The output current, i o, of the current amplifier can be written as i o = A i (s)(i 1 i 2 ) = A i (s)(i in i o ) The closedloop current gain, i o /i in, can be found as i o i = A i(s) in 1A i (s) However, = i o R 2 and v in = i in R 1. Solving for the voltage gain, /v in gives v = i or 2 in i in R = R 2 1 R A i (s) 1 1A i (s) i o If A i (s) = A o s, then ω 1 A v = R 2 in R A o 1 1A ω A (1A o ) o s ω A (1A o ) A v (0) = R 2 A o R 1 (1A o ) and ω 3dB = ω A (1A o )

CMOS Analog Circuit Design Page 7.220 Bandwidth Advantage of a Current Feedback Amplifier Continued The unitygainbandwidth is, R 2 A o GB = A v (0) ω 3dB = R 1 (1A o ) ω A (1A o ) = R 2 R A 1 o ω A = R 2 R GB 1 i where GB i is the unitygainbandwidth of the current amplifier. Note that if GB i is constant, then increasing R 2 /R 1 (the voltage gain) increases GB. Illustration: Magnitude db A o db 0dB Note that GB 2 > GB 1 > GB i Voltage Amplifier Voltage Amplifier Current Amplifier ω A GB i R 2 R 1 >1 R 2 R 1 <1 GB 1 GB 2 log 10 (ω) Fig. 7.210 The above illustration assumes that the GB of the voltage amplifier realizing the voltage buffer is greater than the GB achieved from the above method. CMOS Analog Circuit Design Page 7.221 A Simple Current Mirror Implementation of a High Frequency Amplifier Since the gain of the current amplifier does not need to be large, consider a unitygain current mirror implementation: M4 v in R1 M5 R 2 M3 vout I Bias M1 M2 M8 M9 Fig. 7.211 An inverting amplifier with a gain of 10 is achieved if R 2 = 20R 1 assuming the gain of the current mirror is unity. What is the GB of this amplifier? R 2 A o GB = A v (0) ω 3dB = R 1 (1A o ) 1 A o 1 R 2 C = o (1A o )R 1 C = o 2R 1 C o where C o is the capacitance seen at the output of the current mirror. If R 1 = 10kΩ and C o = 250fF, then GB = 31.83MHz. Limitations: R 2 R 1 >R in = 1/g m1 and R 2 < r ds2 r ds6 R << g 1 m1 (r ds2 r ds6 )

CMOS Analog Circuit Design Page 7.222 A WideSwing, Cascode Current Mirror Implementation of a High Frequency Amplifier The current mirror shown below increases the value of R 2 by increasing the output resistance of the current mirror. M14 M13 M5 M8 M9 R 4 v in R 1 R 2 M12 I Bias M15 M1 M3 M4 M10 M2 M11 New limitations: R 1 > Fig. 7.212 1 g m1 and R 2 < g m4 r ds4 r ds2 g m6 r ds6 r ds8 R 2 R 1 << g m1 (g m4 r ds4 r ds2 g m6 r ds6 r ds8 ) CMOS Analog Circuit Design Page 7.223 Example 7.23 Design of a High GB Voltage Amplifier using Current Feedback Design the wideswing, cascode voltage amplifier to achieve a gain of 10V/V and a GB of 500MHz which corresponds to a 3dB frequency of 50MHz. Solution Since we know what the gain is to be, let us begin by assuming that C o will be 100fF. Thus to get a GB of 500MHz, R 1 must be 3.2kΩ and R 2 = 32kΩ. Therefore, R 3 must be at least 300Ω. R 3 is designed by V ON /I where V ON is the saturation voltage of M1M4. Therefore we can write R 3 = V ON I = 2 IK (W/L) = 300Ω 22.2x106 = K I W L 0.202 = I W L At this point we have a problem because if W/L is small to minimize C o, the current will be too high. If we select W/L = 200µm/1µm we will get a current of 1mA. However, using this W/L for M4 and will give a value of C o that is greater than 100fF. Select W/L = 200 for M1, M3, M5 and and W/L = 20µm/1µm for M2, M4,, and M8. which gives a current in these transistors of 100µA. Since R 2 /R 1 is multiplied by 1/11 let R 2 be 110 times R 1 or 352kΩ. Now select a W/L for M12 of 20µm/1µm which will now permit us to calculate C o. We will assume zerobias on all voltage dependent capacitors. Furthermore, we will assume the diffusion area as 2µm times the W. C o can be written as C o = C gd4 C bd4 C gd6 C bd6 C gs12

CMOS Analog Circuit Design Page 7.224 Example 7.23 Design of a High GB Voltage Amplifier using Current Feedback Cont d The information required to calculate these capacitors is found from Table 3.21. The various capacitors are, C gd4 = C gd6 = CGDOx10µm = (220x10 12 )(20x10 6 ) = 4.4fF C bd4 = CJxAD 4 CJSWxPD 4 = (770x10 6 )(20x10 12 )(380x10 12 )(44x10 6 ) = 15.4fF16.7fF = 32.1fF C bd6 = (560x10 6 )(20x10 12 )(350x10 12 )(44x10 6 ) = 26.6fF C gs12 = (220x10 12 )(20x10 6 ) (0.67)(20x10 6 106 24.7x104 ) = 37.3fF Therefore, C o = 4.4fF32.1fF4.4fF26.6fF37.3fF = 105fF Note that if we had not reduced the W/L of M2, M4,, and M8 that C o would have easily exceeded 100fF. Since 105fF is close to our original guess of 100fF, let us keep the values of R 1 and R 2. If this value was significantly different, then we would adjust the values of R 1 and R 2 so that the GB is 500MHz. One must also check to make sure that the input pole is greater than 500MHz. The design is completed by assuming that I Bias = 100µA and that the current in M9 through M12 be 100µA. Thus W 13 /L 13 = W 14 /L 14 = 20µm,/1µm and W 9 /L 9 through W 12 /L 12 are 20µm/1µm. CMOS Analog Circuit Design Page 7.225 Example 7.23 Design of a High GB Voltage Amplifier using Current Feedback Cont d vout/vin db 30 20 10 0 10 20 R 1 = 3.2kΩ f 3dB R 1 = 1kΩ 20dB/dec GB 40dB/dec 30 10 5 10 6 10 7 10 8 10 9 10 10 Frequency (Hz) Fig. 7.213 Simulation Results: f 3dB 38MHz GB 300MHz Closedloop gain = 18dB (Loss of 2dB is attributed to source follower and R 1 ) Note second pole at about 1GHz. To get these results, it was necessary to bias the input at 1.7VDC using ±3V power supplies. If R 1 is decreased to 1kΩ results in: Gain of 26.4dB, f 3dB = 32MHz, and GB = 630MHz

CMOS Analog Circuit Design Page 7.226 Parallel Path Op Amps This type of op amp combines a highgain, lowfrequency path with a lowgain, highfrequency path. db v in Fig. 7.214 A1 A2 v o1 v o2 Comments: Op amp will be conditionally stable Compensation will be challenging A vd1 (0 ) db A vd2 (0 ) db 0 db A vd1 (s) p 1 p 2 log 10 (f) A vd2 (s) p 3 GB CMOS Analog Circuit Design Page 7.227 Multipath Nested Miller Compensation C m2 C m1 v in g m3 g m2 g m1 g m4 Fig. 7.215 Comments: All Miller capacitances must be around inverting stages Ensure that the RHP zeros generated by the Miller compensation are canceled Avoid polezero doublets which can introduce a slow time constant R.G.H. Eschauzier and J.H.Huijsing, Frequency Compensation Techniques for LowPower Operational Amplifiers, Kluwer Academic publishers, 1995, Chapter 6.

CMOS Analog Circuit Design Page 7.228 Illustration of Hybrid Nested Miller Compensation (Note that this example is not multipath.) C m3 C m2 C m1 v in p 1 p 2 p3 g m1 gm2 g p4 m3 g m4 Fig. 7.216 R 1 R 2 R3 R L C L Compensating Results: 1) Cm1 pushes p4 to higher frequencies and p3 down to lower frequencies 2) Cm2 pushes p2 to higher frequencies and p1 down to lower frequencies 3) Cm3 pushes p3 to higher frequencies (feedback path) & pulls p1 further to lower frequencies Equations: GB gm1/cm3 p2 gm2/cm3 p3 gm3cm3 / (Cm1Cm2) p4 gm4/cl Design: GB < p2, p3, p4 R.G. H. Eschauzier et. al., A Programmable 1.5V CMOS ClassAB Operational Amplifier with Hybrid Nested Miller Compensation for 120dB Gain and 6MHz UGT, IEEE J. of Solid State Circuits, vol. 29, No. 12, pp. 14971504, Dec. 1994. CMOS Analog Circuit Design Page 7.229 Illustration of the Hybrid Nested Miller Compensation Technique p 4 p 3 p 2 p 1 jω σ C m1 p 4 p 3 p 2 p 1 jω σ C m2 p 4 p 2 p 3 p 1 jω σ C m3 p 4 p 3 p 2 p 1 jω σ Fig. 7.217

CMOS Analog Circuit Design Page 7.230 Summary Normal op amps limited by g m /C Typical limit for CMOS op amp is GB 50MHz Other approaches to high frequency CMOS op amps: Current amplifiers (Transimpedance amplifiers) Switched amplifier (simplifies the circuit reduce capacitances) Parallel path op amps (compensation becomes more complex) What does the future hold? Reduction of channel lengths mean: * Reduced capacitances Higher GB s * Higher transconductances (larger values of K ) Higher GB s * Increased channel conductance Lower gains (more stages required) * Reduction of power supply Increased capacitances In otherwords, there should be some improvement in op amp GB s but it won t be inversely proportional to the decrease in channel length. I.e. maybe GB s 100MHz for 0.2µm CMOS. CMOS Analog Circuit Design Page 7.31 SECTION 7.3 DIFFERENTIAL OUTPUT OP AMPS Why Differential Output Op Amps? Cancellation of common mode signals including clock feedthrough Increased signal swing v 1 v 2 A t A A t A v 1 v 2 2A t 2A Fig. 7.31 Cancellation of evenorder harmonics Symbol: v in Fig. 7.31A

CMOS Analog Circuit Design Page 7.32 Common Mode Output Voltage Stabilization If the common mode gain not small, it may cause the common mode output voltage to be poorly defined. Illustration: v od 0 t v od CM output voltage = 0 0 v od 0 CM output voltage =0.5 t t CM output voltage =0.5 Fig. 7.32 CMOS Analog Circuit Design Page 7.33 TwoStage, Miller, DifferentialIn, DifferentialOut Op Amp v o1 M8 C c R z V BP M3 M4 R z C c v o2 v i1 M1 M2 v i2 M9 V BN M5 Fig. 7.33 Output common mode range (OCMR) = V SDP (sat) V DSN (sat) The maximum peaktopeak output voltage 2 OCMR Conversion between differential outputs and singleended outputs: v id v od Fig. 7.34 C L v id v o1 v o2 2C L 2C L

CMOS Analog Circuit Design Page 7.34 DifferentialOutput, FoldedCascode, ClassA Op Amp M15 M14 M4 M5 M13 R 1 v o2 v i1 v i2 vo1 M1 M2 R 2 M16 M3 M8 M10 M17 OCMR = 2V SDP (sat) 2V DSN (sat) V Bias M12 M9 M11 Fig. 7.35 CMOS Analog Circuit Design Page 7.35 TwoStage, Miller, DifferentialIn, DifferentialOut Op Amp with PushPull Output M13 M3 V BP M4 v o1 C c R z M14 R z C c v o2 v i1 M1 M2 v i2 M9 M10 V BN M5 M12 M8 Fig. 7.36 Comments: Able to actively source and sink output current Output quiescent current poorly defined

CMOS Analog Circuit Design Page 7.36 TwoStage, Differential Output, FoldedCascode Op Amp M4 M20 M5 M12 M13 M19 M14 M15 M10 R 1 M11 v i1 v i2 v R o2 z C c M1 M2 Rz C c v o1 M16 M8 M3 M18 V Bias M9 M17 Fig. 7.37A Note that the followers M11M13 and M10M12 are necessary for level translation to the output stage. CMOS Analog Circuit Design Page 7.37 Unfolded Cascode Op Amp with DifferentialOutputs M5 M3 M4 M8 M21 M20 M9 M10 v i1 M1 M2 v i2 M19 v o1 R 2 M22 R 1 v o2 M15 M16 M17 M18 M23 VBias M13 M12 M11 M14 Fig. 7.38

CMOS Analog Circuit Design Page 7.38 CrossCoupled Differential Amplifier Stage One of the problems with some of the previous stages, is that the quiescent output current was not well defined. The following input stage solves this problem. i 1 i 2 v i1 V GS1 V SG3 M1 M2 v GS1 v GS2 v SG3 v SG4 M3 M4 V GS2 V SG4 v i2 i 2 i 1 Fig. 7.39 Operation: Voltage loop v i1 v i2 = V GS1 v GS1 v SG4 V SG4 = V SG3 v SG3 v GS2 V GS2 Using the notation for ac, dc, and total variables gives, v i2 v i1 = v id = (v sg1 v gs4 ) = (v sg3 v gs2 ) If M1=M2=M3=M4, then half of the differential input is applied across each transistor with the correct polarity. i 1 = g m1 v id 2 = g m4 v id 2 and i 2 = g m2 v id 2 = g m3 v id 2 CMOS Analog Circuit Design Page 7.39 Class AB, Differential Output Op Amp using a CrossCoupled Differential Input Stage M9 M8 M10 M25 M26 M13 v o1 M15 M11 v i1 M21 M19 R 2 M27 M17 M28 V Bias M5 M1 M2 M3 M4 v i2 M24 M22 R 1 M14 v o2 M20 M16 M18 M23 M12 Fig. 7.310 Quiescent output currents are defined by the current in the input crosscoupled differential amplifier.

CMOS Analog Circuit Design Page 7.310 CommonMode Output Voltage Stabilization M1 Commonmode feedback circuit M2 v o1 i o1 (source) R o1 R o2 i o2 (source) v o2 i o1 (sink) R o3 R o4 i o2 (sink) Model of output of differential output op amp Fig. 7.311 Operation: M1 and M2 sense the commonmode output voltage. If this voltage rises, the currents in M1 and M2 decrease. This decreased current flowing through R o3 and R o4 cause the commonmode output voltage to decrease with respect to. CMOS Analog Circuit Design Page 7.311 TwoStage, Miller, DifferentialIn, DifferentialOut Op Amp with CommonMode Stabilization M10 V BP M11 v o1 C c R z M3 M4 R z C c v o2 v i1 M1 M2 v i2 Comments: Simple Unreferenced M9 V BN M5 M8 Fig. 7.312

CMOS Analog Circuit Design Page 7.312 A Referenced CommonMode Output Voltage Stabilization Scheme v o1 M1 M2 v o2 M3 M4 V ocm I I ocm 5 I 6 To correction circuitry M5 Fig. 7.313 Operation: 1.) The desired commonmode output voltage, V ocm, creates I ocm. 2.) The actual commonmode output voltage creates the current I 5 which is mirrored to I 6. 3.) If M1 through M4 are matched and the current mirror is ideal, then when I ocm = I 6 the actual commonmode output voltage should be equal to the desired commonmode output voltage. 4.) The above steps assume that a correction circuitry exists that changes the commonmode output voltage in the correct manner. CMOS Analog Circuit Design Page 7.313 Common Model Feedback Circuits Implementation of common mode feedback circuit: I Bias V CM MC3 Commonmode feedback circuit I C3 MC1 MC2A MC4 I C4 MC2B M3 M4 v 3 I 3 I 4 v 1 M1 M2 v 4 Selfresistances of M1M4 v 2 MB MC5 M5 Fig. 7.313A This scheme can be applied to any differential output amplifier. Caution: Be sure to check the stability of commonmode feedback loops, particularly those that are connected to op amps that have a cascode output. The gain of the commonmode feedback loop can easily reach that of a twostage amplifier.

CMOS Analog Circuit Design Page 7.314 External CommonMode Output Voltage Stabilization Scheme φ 1 φ 2 φ 1 v id v o1 CMbias v o2 C cm C cm φ 1 V ocm φ 1 φ 2 φ 1 Fig. 7.314 Operation: 1.) During the φ 1 phase, both C cm are charged to the desired value of V ocm and CMbias = V ocm. 2.) During the φ 2 phase, the C cm capacitors are connected between the differential outputs and the CMbias node. The average value applied to the CMbias node will be V ocm. CMOS Analog Circuit Design Page 7.41 SECTION 7.4 MICROPOWER OP AMPS Objectives Minimize power dissipation Work at low values of power supply Tradeoff speed for less power Subthreshold Operation Most micropower op amps use transistors in the subthreshold region. Subthreshold characteristics: i D i D Square Law Strong Inversion 1µA Transition 100nA;;;; 100nA Exponential Weak Inversion v GS =V T v GS V T 0 0 V T v GS 0 0 v DS 1V 2V Fig. 7.40A i D = W qv GS L I DO exp nkt (1λv DS ) g m = qi D nkt and g ds λi D

CMOS Analog Circuit Design Page 7.42 TwoStage, Miller Op Amp Operating in Weak Inversion M3 M4 C c M1 M2 v in VBias Low frequency response: A vo = g m2 g m6 r o2 r o4 r r o2 r o4 o6 r o7 r 1 o6 r = o7 n 2 n 6 (kt/q)2(λ 2 λ 4 )(λ 6 λ 7 ) GB and SR: M5 C L Fig.7.41 (No longer 1 I D ) I D1 GB = (n 1 kt/q)c and SR = I D5 C = 2 I D1 C = 2GB n kt 1 q = 2GBn 1V t CMOS Analog Circuit Design Page 7.43 Example 7.41 Gain and GB Calculations for Subthreshold Op Amp. Calculate the gain, GB, and SR of the op amp shown above. The currents are I D5 = 200 na and I D7 = 500 na. The device lengths are 1 µm. Values for n are 1.5 and 2.5 for pchannel and nchannel transistors respectively. The compensation capacitor is 5 pf. Use Table 3.12 as required. Assume that the temperature is 27 C. If = 1.5V and = 1.5V, what is the power dissipation of this op amp? Solution The lowfrequency smallsignal gain is, 1 A v = (1.5)(2.5)(0.026)2(0.04 0.05)(0.04 0.05) = 43,701 V/V The gain bandwidth is 100 10 GB = 9 2.5(0.026)(5 1012) = 307,690 rps 49.0 khz The slew rate is SR = (2)(153846)(2.5)(0.026) = 0.02 V/µs The power dissipation is, P diss = 3(0.7µA) =2.1µW

CMOS Analog Circuit Design Page 7.44 PushPull Output Op Amp in Weak Inversion M3 M4 M8 v i2 M1 M2 First stage gain is, M9 V Bias M5 C c Fig. 7.42 A vo = g m2 g = I D2n 4 V t m4 I D4 n 2 V = I D2n 4 t I D4 n 1 2 Total gain is, A vo = g m1(s 6 /S 4 ) (g ds6 g ds7 ) = (S 6 /S 4 ) (λ 6 λ 7 )n 1 V t At room temperature (V t = 0.0259V) and for typical device lengths, gains of 60dB can be obtained. The GB is, GB = g m1 S 6 C S 4 = g m1b C CMOS Analog Circuit Design Page 7.45 Increasing the Gain of the Previous Op Amp 1.) Can reduce the currents in M3 and M4 and introduce gain in the current mirrors. 2.) Use a cascode output stage (can t use selfbiased cascode, currents are too low). M8 M9 A v = g m1 g m2 2 R out = v i2 g ds6 g ds10 g m10 V Bias g m1 M3 M1 M5 M4 M2 I 5 g ds7 g = ds11 g m11 v i1 M13 V T 2V ON M14 M10 M12 M15 M11 V T 2V ON I 5 2n n V t I 7 2 λ 2 n I 7 n n V t I 7 2 λ p 2 I 7 n p V t Fig. 7.43A Can easily achieve gains greater than 80dB with power dissipation of less than 1µW. C c I 5 1 = 2I 7 n n V 2 t (n n λ 2 n n p λ 2 p )

CMOS Analog Circuit Design Page 7.46 Increasing the Output Current for Weak Inversion Operation A significant disadvantage of the weak inversion is that very small currents are available to drive output capacitance so the slew rate becomes very small. Dynamically biased differential amplifier input stage: M20 M18 M3 M4 M19 M21 i 1 i 1 vi2 i 1 i 2 i 2 i 2 vi1 M1 M2 M22 A(i 2 i 1 ) I 5 A(i 1 i 2 ) M24 M5 M28 V M29 Bias M26 M27 M25 Fig. 7.44 M23 Note that the sinking current for M1 and M2 is I sink = I 5 A(i 2 i 1 ) A(i 1 i 2 ) where (i 2 i 1 ) and (i 1 i 2 ) are only positive or zero. If v i1 >v i2, then i 2 >i 1 and the sinking current is increased by A(i 2 i 1 ). If v i2 >v i1, then i 1 >i 2 and the sinking current is increased by A(i 1 i 2 ). CMOS Analog Circuit Design Page 7.47 Dynamically Biased Differential Amplifier Continued How much output current is available from this circuit if there is no current gain from the input to output stage? Assume transistors M18 through M21 are equal to M3 and M4 and that transistors M22 through M27 are all equal. W 28 W 26 W 29 W 27 Let L = A 28 L and 26 L = A 29 L 27 The output current available can be found by assuming that v in = v i1 v i2 > 0. i 1 i 2 = I 5 A(i 2 i 1 ) The ratio of i 2 to i 1 can be expressed as i 2 v in i = exp 1 nv t Defining the output current as i OUT = b(i 2 i 1 ) and combining the above two equations gives, v in bi 5 exp nv 1 t v in i OUT = v i in OUT = when A = 2.16 and nv = 1 t (1A) (A1)exp nv t where b corresponds to any current gain achieved through the current mirrors (M5M4 and M8M3).

CMOS Analog Circuit Design Page 7.48 Overdrive of the Dynamically Biased Differential Amplifier 2 A = 2 A = 1.5 I OUT I 5 1 A = 1 A = 0.3 A = 0 0 0 1 2 v IN nv t Fig. 7.45 The enhanced output current is accomplished by the use of positive feedback (M28M2M19M28). Loop gain is, g m28 g m19 LG = g m4 g = A g m19 m26 g = A m4 Note that as the output current increases, the transistors leave the weak inversion region and the above analysis is no longer valid. CMOS Analog Circuit Design Page 7.49 Increasing the Output Current for Strong Inversion Operation An interesting technique is to bias the output transistor of a current mirror in the active region and then during large overdrive cause the output transistor to become saturated causing a significant current gain. Illustration: 531µA i 1 i 2 M1 M2 V ds2 Current i 2 for W 2 /L 2 = 5.31(W 1 /L 1 ) i 1 100µA Volts 0.1V ds1 (sat) V ds1 (sat) Fig. 7.46

CMOS Analog Circuit Design Page 7.410 Example 7.42 Current Mirror with M2 operating in the Active Region Assume that M2 has a voltage across the drainsource of 0.1V ds (sat). Design the W 2 /L 2 ratio so that I 1 = I 2 = 100µA if W 1 /L 1 = 10. Find the value of I 2 if M2 is saturated. Solution Using the parameters of Table 3.12, we find that the saturation voltage of M2 is 2I 1 V ds1 (sat) = K N (W 2 /L 2 ) = 200 110 10 = 0.4264V Now using the active equation of M2, we set I 2 = 100µA and solve for W 2 /L 2. 100µA = K N (W 2 /L 2 )[V ds1 (sat) V ds2 0.5V ds2 2] = 110µA/V 2 (W 2 /L 2 )[0.426 0.0426 0.5 0.0426 2 ]V 2 = 1.883x10 6 (W 2 /L 2 ) Thus, 100 =1.883(W 2 /L 2 ) W 2 L = 53.12 2 Now if M2 should become saturated, the value of the output current of the mirror with 100µA input would be 531µA or a boosting of 5.31 times I 1. CMOS Analog Circuit Design Page 7.411 Implementation of the Current Mirror Boosting Concept M8 M17 M10 M9 M18 i 1 i M13 M21 2 v i1 M1 M2 v i2 M22 M14 ki 1 M29 M30 ki 2 v o1 i 1 i 2 M27 M3 M4 M28 i 1 i 2 v o2 ki 2 ki 1 M25 M26 i 2 i 1 M15 M23 V M5 Bias M24 M16 M11 M20 M19 M12 Fig.7.47 k = overdrive factor of the current mirror

CMOS Analog Circuit Design Page 7.412 A Better Way to Achieve the Current Mirror Boosting It was found that when the current mirror boosting idea illustrated on the previous slide was used that when the current increased through the cascode device (M16) that V GS16 increased limiting the increase of V DS12. This can be overcome by the following circuit. i in I B i in I B ki in M3 50/1 M5 M4 1/1 1/1 1/1 M1 M2 210/1 Fig. 7.47A CMOS Analog Circuit Design Page 7.413 Summary of Low Power Op Amps Operation of transistors is generally in weak inversion Boosting techniques are needed to get output sourcing and sinking currents that are larger than that available during quiescent operation Be careful about using circuits at weak inversion, i.e. the selfbiased cascode will cause the resistor to be too large

CMOS Analog Circuit Design Page 7.51 SECTION 7.5 LOWNOISE OP AMPS Introduction Why do we need low noise op amps? ;;;; VDD Dynamic Range = 6dBx(Number. of bits) Noise Distortion Fig. 7.50B Dynamic range. Maximum RMS Signal Signaltonoise ratio (SNR) = Noise (SNDR) Consider a 14 bit digitaltoanalog converter with a 1V reference with a bandwidth of 1MHz. Maximum RMS signal is 0.5V 2 = 0.3535 Vrms A 14 bit D/A converter requires 14x6dB dynamic range or 84 db or 16,400. The value of the least significant bit (LSB) = 0.3535 16,400 = 21.6µVrms If the equivalent input noise of the op amp is not less than this value, then the LSB cannot be resolved and the D/A converter will be in error. An op amp with an equivalent inputnoise spectral density of 10nV/ Hz will have an rms noise voltage of approximately 10nV/ Hz 1000 Hz = 10µVrms. CMOS Analog Circuit Design Page 7.52 Transistor Noise Sources (LowFrequency) Drain current model: D D G M1 G M1 i 2 n1 M1 is noisy M1 is noiseless S S Fig. 7.50A i 2 8kTg m n = 3 (KF)I D fc ox L 2 or i 2 8kTg n = m (1η) 3 (KF)I D fc ox L 2 if v BS 0 Recall that η = g m g mbs Gate voltage model assuming common source operation: D G M1 M1 is noisy S G e 2 n1 * M1 M1 is noiseless D S Fig. 7.50C e 2 n = i N 2 g 2 = 8kT KF m 3g m 2fC ox WLK or e 2 n = 8kT(1η) KF 3g m 2fC ox WLK if v BS 0

CMOS Analog Circuit Design Page 7.53 Minimization of Noise in Op Amps 1.) Maximize the signal gain as close to the input as possible. (As a consequence, only the input stage will contribute to the noise of the op amp.) 2.) To minimize the 1/f noise: a.) Use PMOS input transistors with appropriately selected dc currents and W and L values. b.) Use lateral BJTs to eliminate the 1/f noise. c.) Use chopper stabilization to reduce the lowfrequency noise. Noise Analysis 1.) Insert a noise generator for each transistor that contributes to the noise. (Generally ignore the current source transistor of sourcecoupled pairs.) 2.) Find the output noise voltage across an opencircuit or output noise current into a short circuit. 3.) Reflect the total output noise back to the input resulting in the equivalent input noise voltage. CMOS Analog Circuit Design Page 7.54 A LowNoise, TwoStage, Miller Op Amp M10 M11 V Bias v in M5 M1 M8 M3 M2 M9 M4 C c V Bias e 2 n1 * e 2 n8 * M8 M3 M1 I 5 en3 2 en4 2 * * V SG7 en7 2 en2 2 * M2 * M9 en9 2 * en6 2 VBias * M4 e 2 to The total outputnoise voltage spectral density, e to, 2 is found as follows where g m8 (eff) 1/r ds1, e 2 to = g 2 m6 R 2 II e n6 2 e 2 n7 R 2 I g 2 m1 e 2 2 n1g m2 e 2 2 n2g m3 e 2 2 n3g m4 e 2 n4 e 2 n8 r 2 e 2 n9 ds1 r 2 ds2 Dividing by (g m1 R I g m6 R II ) 2 gives the equivalent inputnoise voltage spectral density, e eq, 2 as e eq 2 e to 2 = (g m1 g m6 R I R II ) 2 = 2 e 2 n6 g m1 2R 2 2 e n1 2 1 g m3 I g 2 e n3 2 e n8 2 m1 e n1 2 g m1 2r 2 ds1 e n1 2 2 e 2 n1 1 g m3 where e 2 n6 = e n7, 2 e 2 n3 = e n4, 2 e 2 n1 = e 2 n2 and e 2 n8 = e 2 n9 and g m1 R I is large. g m1 2 Fig. 7.51 e 2 n3 e 2 n1 2