PRELIMINRY PD- 9.336 IRFR/U024N HEXFET Power MOSFET Utra Low On-Resistance Surface Mount (IRFR024N) Straight Lead (IRFU024N) dvanced Process Technoogy Fast Switching Fuy vaanche Rated G D S V DSS = 55V R DS(on) = 0.075Ω I D = 7 Description Fifth Generation HEXFETs from Internationa Rectifier utiize advanced processing techniques to achieve the owest possibe on-resistance per siicon area. This benefit, combined with the fast switching speed and ruggedized device design that HEXFET Power MOSFETs are we known for, provides the designer with an extremey efficient device for use in a wide variety of appications. The D-PK is designed for surface mounting using vapor phase, infrared, or wave sodering techniques. The straight ead version (IRFU series) is for through-hoe mounting appications. Power dissipation eves up to.5 watts are possibe in typica surface mount appications. bsoute Maximum Ratings Therma Resistance D-Pak TO-252 I-Pak TO-25 Parameter Max. Units I D @ T C = 25 C Continuous Drain Current, V GS @ 0V 7 I D @ T C = 00 C Continuous Drain Current, V GS @ 0V 2 I DM Pused Drain Current 68 P D @T C = 25 C Power Dissipation 45 W Linear Derating Factor 0.30 W/ C V GS Gate-to-Source Votage ± 20 V E S Singe Puse vaanche Energy 7 mj I R vaanche Current 0 E R Repetitive vaanche Energy 4.5 mj dv/dt Peak Diode Recovery dv/dt ƒ 5.0 V/ns T J Operating Junction and -55 to 75 T STG Storage Temperature Range Sodering Temperature, for 0 seconds 300 (.6mm from case ) C Parameter Typ. Max. Units R θjc Junction-to-Case 3.3 R θj Case-to-mbient (PCB mount)** 50 C/W R θj Junction-to-mbient 0 ** When mounted on " square PCB (FR-4 or G-0 Materia ). For recommended footprint and sodering techniques refer to appication note #N-994 www.irf.com
Eectrica Characteristics @ T J = 25 C (uness otherwise specified) Parameter Min. Typ. Max. Units Conditions V (BR)DSS Drain-to-Source Breakdown Votage 55 V V GS = 0V, I D = 250µ V (BR)DSS / T J Breakdown Votage Temp. Coefficient 0.052 V/ C Reference to 25 C, I D = m R DS(on) Static Drain-to-Source On-Resistance 0.075 Ω V GS = 0V, I D = 0 V GS(th) Gate Threshod Votage 2.0 4.0 V V DS = V GS, I D = 250µ g fs Forward Transconductance 4.5 S V DS = 25V, I D = 0 I DSS Drain-to-Source Leakage Current 25 V µ DS = 55V, V GS = 0V 250 V DS = 44V, V GS = 0V, T J = 50 C I GSS Gate-to-Source Forward Leakage 00 V GS = 20V n Gate-to-Source Reverse Leakage -00 V GS = -20V Q g Tota Gate Charge 20 I D = 0 Q gs Gate-to-Source Charge 5.3 nc V DS = 44V Q gd Gate-to-Drain ("Mier") Charge 7.6 V GS = 0V, See Fig. 6 and 3 t d(on) Turn-On Deay Time 4.9 V DD = 28V t r Rise Time 34 I D = 0 ns t d(off) Turn-Off Deay Time 9 R G = 24Ω t f Fa Time 27 R D = 2.6Ω, See Fig. 0 Between ead, L D Interna Drain Inductance 4.5 6mm (0.25in.) nh G from package L S Interna Source Inductance 7.5 and center of die contact C iss Input Capacitance 370 V GS = 0V C oss Output Capacitance 40 pf V DS = 25V C rss Reverse Transfer Capacitance 65 ƒ =.0MHz, See Fig. 5 D S Source-Drain Ratings and Characteristics Parameter Min. Typ. Max. Units Conditions D I S Continuous Source Current MOSFET symbo 7 (Body Diode) showing the G I SM Pused Source Current integra reverse 68 (Body Diode) p-n junction diode. S V SD Diode Forward Votage.3 V T J = 25 C, I S = 0, V GS = 0V t rr Reverse Recovery Time 56 83 ns T J = 25 C, I F = 0 Q rr Reverse RecoveryCharge 20 80 nc di/dt = 00/µs t on Forward Turn-On Time Intrinsic turn-on time is negigibe (turn-on is dominated by L S L D ) Notes: Repetitive rating; puse width imited by max. junction temperature. ( See fig. ) V DD = 25V, starting T J = 25 C, L =.0mH R G = 25Ω, I S = 0. (See Figure 2) ƒ I SD 0, di/dt 280/µs, V DD V (BR)DSS, T J 75 C Puse width 300µs; duty cyce 2%. This is appied for I-PK, L S of D-PK is measured between ead and center of die contact. Uses IRFZ24N data and test conditions. 2 www.irf.com
I, Drain-to-Source Current () D 00 0 VGS TOP 5V 0V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V 4.5V I, Drain-to-Source Current () D 00 0 VGS TOP 5V 0V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V 4.5V 20µs PULSE WIDTH T C = 25 C 0. 0 00 V DS, Drain-to-Source Votage (V) 20µs PULSE WIDTH T C = 75 C 0. 0 00 V DS, Drain-to-Source Votage (V) Fig. Typica Output Characteristics Fig 2. Typica Output Characteristics I D, Drain-to-Source Current () 00 0 T = 25 C J V DS= 25V 20µs PULSE W IDTH 4 5 6 7 8 9 0 V GS T = 75 C J, Gate-to-Source Votage (V) R DS(on), Drain-to-Source On Resistance (Normaized) 3.0 2.5 2.0.5.0 0.5 I D = 7 V GS = 0V 0.0-60 -40-20 0 20 40 60 80 00 20 40 60 80 T J, Junction Temperature ( C) Fig 3. Typica Transfer Characteristics Fig 4. Normaized On-Resistance Vs. Temperature www.irf.com 3
C, Capacitance (pf) 700 600 500 400 300 200 00 C iss C oss C rss V GS = 0V, f = MHz C iss = C gs C gd, C ds SHORTED C rss = C gd C oss = C ds C gd 0 0 00 V DS, Drain-to-Source Votage (V) V, Gate-to-Source Votage (V) GS 20 6 2 8 4 I D = 0 V DS = 44V V DS = 28V FOR TEST CIRCUIT 0 SEE FIGURE 3 0 4 8 2 6 20 Q, Tota Gate Charge (nc) G Fig 5. Typica Capacitance Vs. Drain-to-Source Votage Fig 6. Typica Gate Charge Vs. Gate-to-Source Votage I SD, Reverse Drain Current () 00 0 T = 75 C J T = 25 C J I D, Drain Current () 000 00 0 OPERTION IN THIS RE LIMITED BY R DS(on) 0µs 00µs V GS = 0V 0.4 0.6 0.8.0.2.4.6.8 2.0 V SD, Source-to-Drain Votage (V) T ms C = 25 C T J = 75 C Singe Puse 0ms 0 00 V DS, Drain-to-Source Votage (V) Fig 7. Typica Source-Drain Diode Forward Votage Fig 8. Maximum Safe Operating rea 4 www.irf.com
20 V DS R D I D, Drain Current (mps) 6 2 8 R G V GS 4.5V Puse Width µs Duty Factor 0. % D.U.T. Fig 0a. Switching Time Test Circuit - V DD 4 V DS 90% 0 25 50 75 00 25 50 75 T C, Case Temperature ( C) Fig 9. Maximum Drain Current Vs. Case Temperature 0% V GS t d(on) t r t d(off) t f Fig 0b. Switching Time Waveforms 0 Therm a R esponse (Z thjc ) 0. D = 0.50 0.20 0.0 0.05 0.02 0.0 SINGLE PULSE (THERML RESPONSE) 2. Peak T J = P DM x Z thjc T C 0.0 0.0000 0.000 0.00 0.0 0. t, Rectanguar Puse Duration (sec) Notes:. Duty factor D = t / t 2 P DM t t 2 Fig. Maximum Effective Transient Therma Impedance, Junction-to-Case www.irf.com 5
R G V DS 20V tp I S Fig 2a. Uncamped Inductive Test Circuit tp L D.U.T 0.0Ω 5V DRIVER V (BR)DSS - V DD E S, Singe Puse vaanche Energy (mj) 40 20 00 80 60 40 20 I D TOP 4.2 7.2 BOTTOM 0 V DD = 25V 0 25 50 75 00 25 50 75 Starting T J, Junction Temperature ( C) Fig 2c. Maximum vaanche Energy Vs. Drain Current I S Fig 2b. Uncamped Inductive Waveforms Current Reguator Same Type as D.U.T. 50KΩ Q G 2V.2µF.3µF 0 V Q GS Q GD D.U.T. V - DS V G V GS 3m Charge I G I D Current Samping Resistors Fig 3a. Basic Gate Charge Waveform Fig 3b. Gate Charge Test Circuit 6 www.irf.com
Peak Diode Recovery dv/dt Test Circuit D.U.T ƒ - Circuit Layout Considerations Low Stray Inductance Ground Pane Low Leakage Inductance Current Transformer - - R G dv/dt controed by R G Driver same type as D.U.T. I SD controed by Duty Factor "D" D.U.T. - Device Under Test - V DD Driver Gate Drive Period P.W. D = P.W. Period V GS =0V * D.U.T. I SD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. V DS Waveform Diode Recovery dv/dt V DD Re-ppied Votage Inductor Curent Body Diode Forward Drop Rippe 5% I SD * V GS = 5V for Logic Leve Devices Fig 4. For N-Channe HEXFETS www.irf.com 7
Package Outine TO-252 Outine Dimensions are shown in miimeters (inches) 5.46 (.25) 5.2 (.205) 6.73 (.265) 6.35 (.250) - -.27 (.050) 0.88 (.035) 2.38 (.094) 2.9 (.086).4 (.045) 0.89 (.035) 0.58 (.023) 0.46 (.08) 4.02 (.040).64 (.025) 2 3 6.22 (.245) 5.97 (.235) 0.42 (.40) 9.40 (.370) 6.45 (.245) 5.68 (.224) LED SSIGNMENTS - GTE.52 (.060).5 (.045) 2X.4 (.045) 0.76 (.030) 3X - B - 0.89 (.035) 0.64 (.025) 0.25 (.00) M M B 0.5 (.020) MIN. 0.58 (.023) 0.46 (.08) 2 - DRIN 3 - SOURCE 4 - DRIN 2.28 (.090) 4.57 (.80) NOTES: DIMENSIONING & TOLERNCING PER NSI Y4.5M, 982. 2 CONTROLLING DIMENSION : INCH. 3 CONFORMS TO JEDEC OUTLINE TO-252. 4 DIMENSIONS SHOWN RE BEFORE SOLDER DIP, SOLDER DIP MX. 0.6 (.006). Part Marking Information TO-252 (D-PRK) EXMPLE : THIS IS N IRFR20 W ITH SSEMBLY LOT CODE 9UP INTERNTIONL RECTIFIER LOGO IRFR 20 FIRST PORTION OF PRT NUMBER 9U P SSEMBLY SECOND PORTION LOT CODE OF PRT NUMBER 8 www.irf.com
Package Outine TO-25 Outine Dimensions are shown in miimeters (inches) 5.46 (.25) 5.2 (.205).52 (.060).5 (.045) 6.73 (.265) 6.35 (.250) - - 4 6.22 (.245) 5.97 (.235).27 (.050) 0.88 (.035) 2.38 (.094) 2.9 (.086) 0.58 (.023) 0.46 (.08) 6.45 (.245) 5.68 (.224) LED SSIGNMENTS - GTE 2 - DRIN 3 - SOURCE 4 - DRIN 2 3 - B - 2.28 (.090).9 (.075) 9.65 (.380) 8.89 (.350) NOTES: DIMENSIONING & TOLERNCING PER NSI Y4.5M, 982. 2 CONTROLLING DIMENSION : INCH. 3 CONFORMS TO JEDEC OUTLINE TO-252. 4 DIMENSIONS SHOWN RE BEFORE SOLDER DIP, SOLDER DIP MX. 0.6 (.006). 3X.4 (.045) 0.76 (.030) 2.28 (.090) 2X 3X 0.89 (.035) 0.64 (.025) 0.25 (.00) M M B.4 (.045) 0.89 (.035) 0.58 (.023) 0.46 (.08) Part Marking Information TO-25 (I-PRK) EXMPLE : THIS IS N IRFU20 W ITH SSEMBLY LOT CODE 9UP INTERNTIONL RECTIFIER LOGO SSEMBLY LOT CODE IRFU 20 9U P FIRST PORTION OF PRT NUMBER SECOND PORTION OF PRT NUMBER www.irf.com 9
Tape & Ree Information TO-252 Dimensions are shown in miimeters (inches) TR TRR TRL 6.3 (.64 ) 5.7 (.69 ) 6.3 (.64 ) 5.7 (.69 ) 2. (.476 ).9 (.469 ) FEED DIRECTION 8. (.38 ) 7.9 (.32 ) FEED DIRECTION NOTES :. CONTROLLING DIMENSION : MILLIMETER. 2. LL DIMENSIONS RE SHOWN IN MILLIMETERS ( INCHES ). 3. OUTLINE CONFORMS TO EI-48 & EI-54. 3 INCH NOTES :. OUTLINE CONFORMS TO EI-48. 6 mm WORLD HEDQURTERS: 233 Kansas St., E Segundo, Caifornia 90245, Te: (30) 322 333 EUROPEN HEDQURTERS: Hurst Green, Oxted, Surrey RH8 9BB, UK Te: 44 883 732020 IR CND: 732 Victoria Park ve., Suite 20, Markham, Ontario L3R 2Z8, Te: (905) 475 897 IR GERMNY: Saaburgstrasse 57, 6350 Bad Homburg Te: 49 672 96590 IR ITLY: Via Liguria 49, 007 Borgaro, Torino Te: 39 45 0 IR FR EST: K&H Bdg., 2F, 30-4 Nishi-Ikebukuro 3-Chome, Toshima-Ku, Tokyo Japan 7 Te: 8 3 3983 0086 IR SOUTHEST SI: 35 Outram Road, #0-02 Tan Boon Liat Buiding, Singapore 036 Te: 65 22 837 http://www.irf.com/ Data and specifications subject to change without notice. 4/98 0 www.irf.com
Note: For the most current drawings pease refer to the IR website at: http://www.irf.com/package/