Power MOSFET IRFP23N50L, SiHFP23N50L PRODUCT SUMMRY V DS (V) 500 R DS(on) ( ) V GS = V 0.90 Q g (Max.) (nc) 50 Q gs (nc) Q gd (nc) 72 Configuration Single TO-27C S G D ORDERING INFORMTION Package Lead (Pb)-free SnPb G D S N-Channel MOSFET FETURES Superfast Body Diode Eliminates the Need for External Diodes in ZVS pplications Lower Gate Charge Results in Simpler Drive Requirements Enhanced dv/dt Capabilities Offer Improved Ruggedness Higher Gate Voltage Threshold Offers Improved Noise Immunity Compliant to RoHS Directive 2002/95/EC PPLICTIONS Zero Voltage Switching SMPS Telecom and Server Power Supplies Uninterruptible Power Supplies Motor Control pplications TO-27C IRFP23N50LPbF SiHFP23N50L-E3 IRFP23N50L SiHFP23N50L vailable RoHS* COMPLINT BSOLUTE MXIMUM RTINGS (T C = 25 C, unless otherwise noted) PRMETER SYMBOL LIMIT UNIT Drain-Source Voltage V DS 500 V Gate-Source Voltage V GS ± 30 Continuous Drain Current V GS at V T C = 25 C 23 I D T C = 0 C 5 Pulsed Drain Current a I DM 92 Linear Derating Factor 2.9 W/ C Single Pulse valanche Energy b E S mj Repetitive valanche Current a I R 23 Repetitive valanche Energy a E R 37 mj Maximum Power Dissipation T C = 25 C P D 370 W Peak Diode Recovery dv/dt c dv/dt 2 V/ns Operating Junction and Storage Temperature Range T J, T stg - 55 to 50 Soldering Recommendations (Peak Temperature) for s 300 d C Mounting Torque 6-32 or M3 screw Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. ). b. Starting T J = 25 C, L =.5 mh, R g = 25, I S = 23 (see fig. 2). c. I SD 23, di/dt 650 /μs, V DD V DS, T J 50 C. d..6 mm from case. lbf in. N m * Pb containing terminations are not RoHS compliant, exemptions may apply Document Number: 9209 www.vishay.com S-05-Rev. B, 2-Mar- THE PRODUCT DESCRIBED HEREIN ND THIS DTSHEET RE SUBJECT TO SPECIFIC DISCLIMERS, SET FORTH T www.vishay.com/doc?900
IRFP23N50L, SiHFP23N50L THERML RESISTNCE RTINGS PRMETER SYMBOL TYP. MX. UNIT Maximum Junction-to-mbient R thj - 0 Case-to-Sink, Flat, Greased Surface R thcs 0.2 - C/W Maximum Junction-to-Case (Drain) R thjc - 0.3 SPECIFICTIONS (T J = 25 C, unless otherwise noted) PRMETER SYMBOL TEST CONDITIONS MIN. TYP. MX. UNIT Static Drain-Source Breakdown Voltage V DS V GS = 0 V, I D = 250 μ 500 - - V V DS Temperature Coefficient V DS /T J Reference to 25 C, I D = m d - 0.27 - V/ C Gate-Source Threshold Voltage V GS(th) V DS = V GS, I D = 250 μ 3.0-5.0 V Gate-Source Leakage I GSS V GS = ± 30 V - - ± 0 n V DS = 500 V, V GS = 0 V - - 50 μ Zero Gate Voltage Drain Current I DSS V DS = 00 V, V GS = 0 V, T J = 25 C - - 2.0 m Drain-Source On-State Resistance R DS(on) V GS = V I D = b - 0.90 0.235 Forward Transconductance g fs V DS = 50 V, I D = b 2 - - S Dynamic Input Capacitance C iss V GS = 0 V, - 3600 - Output Capacitance C oss V DS = 25 V, - 380 - Reverse Transfer Capacitance C rss f =.0 MHz, see fig. 5-37 - Output Capacitance C oss V DS =.0 V, f =.0 MHz - 800 - V DS = 00 V, f =.0 MHz - 0 - pf Effective Output Capacitance C oss eff. V GS = 0 V V DS = 0 V to 00 V c - 220 - Effective Output Capacitance (Energy Related) C oss eff. (ER) V DS = 0 V to 00 V d - 60 - Internal Gate Resistance R G f = MHz, open drain -.2 - Total Gate Charge Q g I D = 23, V DS = 00 V - - 50 Gate-Source Charge Q gs V GS = V - - nc Gate-Drain Charge Q gd see fig. 6 and 3 b - - 72 Turn-On Delay Time t d(on) V DD = 250 V, I D = 23-26 - Rise Time t r - 9 - R g = 6.0, V GS = V Turn-Off Delay Time t d(off) - 53 - ns Fall Time t f see fig. b - 5 - Drain-Source Body Diode Characteristics MOSFET symbol D Continuous Source-Drain Diode Current I S - - 23 showing the G integral reverse Pulsed Diode Forward Current a I SM S - - 92 p - n junction diode Body Diode Voltage V SD T J = 25 C, I S =, V GS = 0 V b - -.5 V T J = 25 C - 70 250 Body Diode Reverse Recovery Time t rr T J = 25 C I F = 23, - 220 330 ns Body Diode Reverse Recovery Charge Q rr T J = 25 C di/dt = 0 /μs b - 560 80 T J = 25 C - 980 500 μc Reverse Recovery Current I RRM T J = 25 C - 7.6 Forward Turn-On Time t on Intrinsic turn-on time is negligible (turn-on is dominated by L S and L D ) Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. ). b. Pulse width 300 μs; duty cycle 2 %. c. C oss eff. is a fixed capacitance that gives the same charging time as C oss while V DS is rising fom 0 % to 80 % V DS. d. C oss eff. (ER) is a fixed capacitance that stores the same energy time as C oss while V DS is rising fom 0 % to 80 % V DS. www.vishay.com Document Number: 9209 2 S-05-Rev. B, 2-Mar- THE PRODUCT DESCRIBED HEREIN ND THIS DTSHEET RE SUBJECT TO SPECIFIC DISCLIMERS, SET FORTH T www.vishay.com/doc?900
I D, Drain-to-Source Current () IRFP23N50L, SiHFP23N50L TYPICL CHRCTERISTICS (25 C, unless otherwise noted) 0 0. 0.0 0.00 VGS TOP 5V V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM.5V.5 V 20µs PULSE WIDTH Tj = 25 C 0. 0 I D, Drain-to Source Current () 00.00 T J = 25 C 0.00 T J = 50 C.00 20 µs PULSE WIDTH T J = 50 C.00.0 6.0.0 6.0 V DS, Drain-to-Source Voltage (V) V GS, Gate-to-Source Voltage (V) Fig. - Typical Output Characteristics Fig. 3 - Typical Transfer Characteristics I D, Drain-to-Source Current () 0 0. VGS TOP 5V V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM.5V,5 V 20µs PULSE WIDTH Tj = 50 C 0 VDS, Drain-to-Source Voltage (V) R DS(ON), Drain-to-Source On Resistance (Normalized) 3.0 2.5 2.0.5.0 0.5 I D = 23 V GS = V 0.0-60 -0-20 0 20 0 60 80 0 20 0 60 T J, Junction Temperature ( C) Fig. 2 - Typical Output Characteristics Fig. - Normalized On-Resistance vs. Temperature Document Number: 9209 www.vishay.com S-05-Rev. B, 2-Mar- 3 THE PRODUCT DESCRIBED HEREIN ND THIS DTSHEET RE SUBJECT TO SPECIFIC DISCLIMERS, SET FORTH T www.vishay.com/doc?900
Energy (µj) IRFP23N50L, SiHFP23N50L C, Capacitance (pf) 0000 000 00 0 V GS = 0 V, f = MHZ C iss = C gs C gd, C ds SHORTED C rss = C gd C oss = C ds C gd Ciss Coss I D, Drain Current () 00 0 OPERTION IN THIS RE LIMITED BY R DS(ON) us 0us ms Crss 0 00 V DS, Drain-to-Source Voltage (V) Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage T C = 25 C ms T J = 50 C Single Pulse 0 00 000 V DS, Drain-to-Source Voltage (V) Fig. 7 - Maximum Safe Operating rea 25 2 I D = 23 20 5 5 V GS, Gate-to-Source Voltage (V) 7 5 2 V DS = 00 V V DS = 250 V V DS = 0 V 0 0 0 200 300 00 500 600 V DS, Drain-to-Source Voltage (V) Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage 0 0 2 8 72 96 20 Q G, Total Gate Charge (nc) Fig. 8 - Typical Gate Charge vs. Gate-to-Source Voltage www.vishay.com Document Number: 9209 S-05-Rev. B, 2-Mar- THE PRODUCT DESCRIBED HEREIN ND THIS DTSHEET RE SUBJECT TO SPECIFIC DISCLIMERS, SET FORTH T www.vishay.com/doc?900
IRFP23N50L, SiHFP23N50L 0.00 R D V DS I SD, Reverse Drain Current ().00.00 T J = 50 C T J = 25 C R G V GS V Pulse width µs Duty factor 0. % D.U.T. - V DD Fig. a - Switching Time Test Circuit 0. 0.0 V GS = 0 V 0.5.0.5 2.0 V SD, Source-to-Drain Voltage (V) Fig. 9 - Typical Source-Drain Diode Forward Voltage 25 V DS 90 % % V GS t d(on) t r t d(off) t f I D, Drain Current () 20 5 Fig. b - Switching Time Waveforms 5 0 25 50 75 0 25 50 T C, Case Temperature ( C) Fig. - Maximum Drain Current vs. Case Temperature Thermal Response (Z thjc ) 0. 0.0 D = 0.50 0.20 0. 0.05 0.02 0.0 SINGLE PULSE (THERML RESPONSE) P DM t t 2 Notes:. Duty factor D = t / t 2 2. PeakT J = P DM x Z thjc T C 0.00 0.0000 0.000 0.00 0.0 0. t, Rectangular Pulse Duration (sec) Fig. 2 - Maximum Effective Transient Thermal Impedance, Junction-to-Case Document Number: 9209 www.vishay.com S-05-Rev. B, 2-Mar- 5 THE PRODUCT DESCRIBED HEREIN ND THIS DTSHEET RE SUBJECT TO SPECIFIC DISCLIMERS, SET FORTH T www.vishay.com/doc?900
IRFP23N50L, SiHFP23N50L E S, Single Pulse valanche Energy (mj) V GS(th) Gate Threshold Voltage (V) 5.0.5.0 3.5 3.0 2.5 2.0.5.0 I D = 250 µ - 75-50 - 25 0 25 50 75 0 25 T J, Temperature ( C) Fig. 3 - Threshold Voltage vs. Temperature 750 600 50 300 50 0 25 50 75 0 25 50 Starting T, Junction Temperature I D TOP 5 BOTTOM 23 ( C) 50 Fig. - Maximum valanche Energy s. Drain Current V DS t p I S Fig. 5b - Unclamped Inductive Waveforms Current regulator Same type as D.U.T. 2 V 50 kω 0.2 µf 0.3 µf D.U.T. V GS 3 m I G I D Current sampling resistors V - DS Fig. 6a - Gate Charge Test Circuit Q G V Q GS Q GD V G 5 V Charge V DS L Driver Fig. 6b - Basic Gate Charge Waveform R G 20 V tp D.U.T I S 0.0Ω - V DD Fig. 5a - Unclamped Inductive Test Circuit www.vishay.com Document Number: 9209 6 S-05-Rev. B, 2-Mar- THE PRODUCT DESCRIBED HEREIN ND THIS DTSHEET RE SUBJECT TO SPECIFIC DISCLIMERS, SET FORTH T www.vishay.com/doc?900
IRFP23N50L, SiHFP23N50L Peak Diode Recovery dv/dt Test Circuit D.U.T. - Circuit layout considerations Low stray inductance Ground plane Low leakage inductance current transformer - - R g dv/dt controlled by R g Driver same type as D.U.T. I SD controlled by duty factor D D.U.T. - device under test - V DD Driver gate drive P.W. Period D = P.W. Period V GS = V a D.U.T. l SD waveform Reverse recovery current Body diode forward current di/dt D.U.T. V DS waveform Diode recovery dv/dt V DD Re-applied voltage Inductor current Body diode forward drop Ripple 5 % I SD Note a. V GS = 5 V for logic level devices Fig. 7 - For N-Channel maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?9209. Document Number: 9209 www.vishay.com S-05-Rev. B, 2-Mar- 7 THE PRODUCT DESCRIBED HEREIN ND THIS DTSHEET RE SUBJECT TO SPECIFIC DISCLIMERS, SET FORTH T www.vishay.com/doc?900
www.vishay.com TO-27C (High Voltage) Package Information 3 B R/2 Q E E/2 S 2 7 ØP (Datum B) Ø k M D B M ØP D2 2 x R (2) D D 2 3 D Thermal pad 5 L C 2 x b2 3 x b 0. M C M b Lead ssignments. Gate 2. Drain 3. Source. Drain 2 x e L See view B C DDE (b, b2, b) () Section C - C, D - D, E - E MILLIMETERS INCHES MILLIMETERS INCHES DIM. MIN. MX. MIN. MX. DIM. MIN. MX. MIN. MX..58 5.3 0.80 0.209 D2 0.5.30 0.020 0.05 2.2 2.59 0.087 0.2 E 5.29 5.87 0.602 0.625 2.7 2.9 0.06 0.098 E 3.72-0.50 - b 0.99.0 0.039 0.055 e 5.6 BSC 0.25 BSC b 0.99.35 0.039 0.053 Ø k 0.25 0.0 b2.53 2.39 0.060 0.09 L.20 6.25 0.559 0.60 b3.65 2.37 0.065 0.093 L 3.7.29 0.6 0.69 b 2.2 3.3 0.095 0.35 N 7.62 BSC 0.300 BSC b5 2.59 3.38 0.2 0.33 Ø P 3.5 3.66 0.38 0. c 0.38 0.86 0.05 0.03 Ø P - 7.39-0.29 c 0.38 0.76 0.05 0.030 Q 5.3 5.69 0.209 0.22 D 9.7 20.82 0.776 0.820 R.52 5.9 0.78 0.26 D 3.08-0.55 - S 5.5 BSC 0.27 BSC ECN: X3-03-Rev. D, 0-Jul-3 DWG: 597 Notes. Dimensioning and tolerancing per SME Y.5M-99. 2. Contour of slot optional. 3. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.27 mm (0.005") per side. These dimensions are measured at the outermost extremes of the plastic body.. Thermal pad contour optional with dimensions D and E. 5. Lead finish uncontrolled in L. 6. Ø P to have a maximum draft angle of.5 to the top of the part with a maximum hole diameter of 3.9 mm (0.5"). 7. Outline conforms to JEDEC outline TO-27 with exception of dimension c. 8. Xian and Mingxin actually photo. E View B C C Planting (c) E 0.0 M D B M View - (b, b3, b5) Base metal c Revision: 0-Jul-3 Document Number: 9360 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHNGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN ND THIS DOCUMENT RE SUBJECT TO SPECIFIC DISCLIMERS, SET FORTH T www.vishay.com/doc?900
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