PROTETION PRODUTS - EMIlamp TM Description The Elamp TM 0 is a low pass filter array with integrated TVS diodes. It is designed to suppress unwanted EMI/RFI signals and provide electrostatic discharge (ESD) protection in portable electronic equipment. This state-of-the-art device utilizes solidstate silicon-avalanche technology for superior clamping performance and D electrical characteristics. They have been optimized for protection of color LD panels in cellular phones and other portable electronics. The device consists of ten identical circuits comprised of TVS diodes for ESD protection, and a resistor - capacitor network for EMI/RFI filtering. A series resistor value of 00Ω and a capacitance value of pf is used to achieve 0dB minimum attenuation from 00 to GHz. Each line features two stages of TVS diode protection. The TVS diodes provide effective suppression of ESD voltages in excess of kv (air discharge) and kv (contact discharge) per IE 000--, level. The device is a -bump, 0.mm pitch flip chip array with a x bump grid. It measures. x. x 0.mm. The solder bumps have a nominal diameter of 0.mm. ircuit Diagram Features Elamp0 EMI Filter and ESD Protection for olor LD Interface PIN onfiguration Flip hip bidirectional EMI/RFI filter with integrated ESD protection ESD protection to IE 000-- (ESD) Level, +/-kv (air), +/-kv (contact) Filter performance: 0dB minimum attenuation 00 to GHz TVS working voltage: V Resistor: 00 Ohms Input apacitance: pf (VR =.V D ) Protection and filtering for ten lines Solid-state technology Mechanical haracteristics JEDE MO-, 0.0 mm pitch flip chip Nominal Dimensions:. x. x 0. mm Bump Diameter: +/-0 µm Non-conductive top side coating Marking : Mark code, lot code, orientation mark Packaging : Tape and Reel per EIA Applications olor LD Panel Protection ell Phone D amera Lines Personal Digital Assistants (PDA s) LOW PASS FILTER IN = pf R = 00 Ohms ircuit 0x x Grid Flip hip (Ball Side View) Revision 0/0/00
Elamp0 PROTETION PRODUTS - EMIlamp TM Absolute Maximum Rating Rating Symbol Value Units ESD per IE 000-- (Air) ESD per IE 000-- (ontact) +/- V ESD +/- kv Junction Temperature T J o Operating Storage Temperature Temperature T op 0 to + T STG to +0 - o - o Electrical haracteristics (T= o ) P arameter r S ymbo l ondition s M inimu m T ypica l M aximu m Unit s TVS Reverse Stand-Off Voltage V RWM V TVS Reverse Breakdown Voltage V R B I t = ma 0 V TVS Reverse Leakage urrent I R V RWM =.0V 0. µ A Total Series Resistance R Each Line 00 Ohms Total Total apacitance apacitance i n Input to Ground, V R Each Line = 0V, f = i n Input to Ground, V R Each Line =.V, f = pf pf 00 Semtech orp.
Elamp0 PROTETION PRODUTS - EMIlamp TM Typical haracteristics Typical Insertion Loss S (Each Line) Analog rosstalk (Each Line) H S LOG db / REF 0 db : -. db 0.000 H S LOG 0 db / REF 0 db 0 db : -. db 00 - db : -. db. GHz - db - db : -.0 db. GHz - db -0 db - db - db - db 0 00 GHz GHz START. 00 STOP 000. 000 000 START. 00 STOP 000. 000 000 ESD lamping (+kv ontact) ESD lamping (-kv ontact) apacitance vs. Reverse Voltage (Normalized to. volts) Series Resistance vs. Temperature. 0.0. Normalized apacitance. 0. 0. 0. Series Resistance (Ohm) 00.0.0 0. 0 0 0..... 0.0-0 -0-0 -0 0 0 0 0 0 0 0 0 0 Reverse Voltage - VR (V) Temperature ( o ) 00 Semtech orp.
Elamp0 PROTETION PRODUTS - EMIlamp TM Applications Information Device onnection Options The Elamp0 has solder bumps located in a x matrix layout on the active side of the device. The bumps are designated by the numbers - along the horizontal axis and letters A - E along the vertical axis. The input of the lines to be protected are connected at bumps A - A and B - B. The line outputs are connected at bumps D - D and E - E. Bumps - are connected to ground. All path lengths should be kept as short as possible to minimize the effects of parasitic inductance in the board traces. Flip hip TVS Flip chip TVS devices are wafer level chip scale packages. They eliminate external plastic packages and leads and thus result in a significant board space savings. Manufacturing costs are minimized since they do not require an intermediate level interconnect or interposer layer for reliable operation. They are compatible with current pick and place equipment further reducing manufacturing costs. ertain precautions and design considerations have to be observed however for maximum solder joint reliability. These include solder pad definition, board finish, and assembly parameters. Printed ircuit Board Mounting Non-solder mask defined (NSMD) land patterns are recommended for mounting flip chip devices. Solder mask defined (SMD) pads produce stress points at the solder mask to solder ball interface that can result in solder joint cracking when exposed to extreme fatigue conditions. The recommended pad size is 0. ± 0.00 mm with a minimum solder mask opening of 0. mm. Pin Identification and onfiguration (Ball Side View) Pin Identification A - A Input, Lines,,,, B - B Input, Lines,,,, 0 - Ground D - D Output, Lines,,,, 0 E - E Output, Lines,,,, Layout Example (Ball Side View) Output 0 Grid ourtyard The recommended grid placement courtyard is. x. mm. The grid courtyard is intended to encompass the land pattern and the component body that is centered in the land pattern. When placing parts on a PB, the highest recommended density is when one courtyard touches another. 0 Input 00 Semtech orp.
Elamp0 PROTETION PRODUTS - EMIlamp TM Applications Information Printed ircuit Board Finish A uniform board finish is critical for good assembly yield. Two finishes that provide uniform surface coatings are immersion nickel gold and organic surface protectant (OSP). A non-uniform finish such as hot air solder leveling (HASL) can lead to mounting problems and should be avoided. Recommended NSMD Pad and Stencil Aperture Stencil Design A properly designed stencil is key to achieving adequate solder volume without compromising assembly yields. A 0.00mm thick, laser cut, electro-polished stencil with 0.0mm apertures corners with rounded corners is recommended. Reflow Profile The flip chip TVS can be assembled using the reflow requirements for IP/JEDE standard J-STD-00 for assembly of small body components. During reflow, the component will self-align itself on the pad. ircuit Board Layout Recommendations for Suppression of ESD Good circuit board layout is critical for the suppression of ESD induced transients. The following guidelines are recommended: Place the TVS near the input terminals or connectors to restrict transient coupling. Minimize the path length between the TVS and the protected line. Minimize all conductive loops including power and ground loops. The ESD transient return path to ground should be kept as short as possible. Never run critical signals near board edges. Use ground planes whenever possible. Assembly Guideline for Pb-Free Soldering The following are recommendations for the assembly of this device: Assembly Solder Solder Parameter Ball omposition Stencil Design Recommendation.Sn/.Ag/0. u Same as the SnPb design S older Stencil Thickness 0.00 mm (0.00") S older Paste omposition Sn Ag (-) u (0.-0.) Solder Paste Type Type size sphere or smaller Solder Reflow Profile per JEDE J-STD-00 PB PB Solder Pad Design Pad Finish Same as the SnPb Design OSP or AuNi 00 Semtech orp.
00 Semtech orp. PROTETION PRODUTS - EMIlamp TM Elamp0 Applications Information Implementation Example 0 0 Baseband ontroller LD Display 0 0 Elamp0 Elamp0 0 0 0 0 0 0 Baseband ontroller LD Display 0 0 0 0 0 0 Elamp0 Elamp0
Elamp0 PROTETION PRODUTS - EMIlamp TM Applications Information Insertion Loss The insertion loss of the device is the ratio of the power delivered to the load with and without the filter in the circuit. This parameter is dependent upon the impedance of the source and the load. The standard impedance of test equipment that is used to measure filter frequency response is 0Ω. In order to obtain an accurate measurement of the filter performance, an evaluation board with 0Ω transmission lines are used. The test conditions for the Elamp0 are shown below. The evaluation board contains SMA connectors at each of the circuits inputs and outputs. The connections are made with 0Ω traces. An HP E network analyzer with an internal spectrum analyzer and tracking generator is used. This equipment has the capability to sweep the device from khz to GHz. The analyzer s source (R S ) impedance is equal to the load (R L ) impedance which is equal to 0Ω. 0 db - db - db - db - db -0 db - db - db - db H S LOG db / REF 0 db 0 00 Insertion Loss S START. 00 STOP 000. 000 000 GHz GHz : -. db 0.000 : -. db 00 : -. db. GHz : -.0 db. GHz 0 Ohms To onnector (Output) To onnector (Input) 0 Ohms Vg Insertion Loss Measurement onditions 00 Semtech orp.
Elamp0 PROTETION PRODUTS - EMIlamp TM Outline Drawing A.0±0.0 B INDEX AREA A ORNER.0±0.0 0.0 0.0-0.0 0.0-0. 0.0 0.0 0.0 L L. E D B A 0.0±0.0 X Ø0.±0.00 0.0 A B NOTES:. ONTROLLING DIMENSIONS ARE IN MILLIMETERS. REFERENE JEDE REGISTRATION MO-.. Sn/Pb FOR STANDARD DEVIES OR Sn./Ag./u0. FOR Pb-FREE DEVIES. Land Pattern X Ø0. 0.0 0.0 THIS LAND PATTERN IS FOR REFERENE PURPOSES ONLY. ONSULT YOUR MANUFATURING GROUP TO ENSURE YOUR NOTES:. OMPANY'S MANUFATURING GUIDELINES ARE MET. 00 Semtech orp.
Elamp0 PROTETION PRODUTS - EMIlamp TM Marking Ordering Information Part Number Solder Ball ompostion Qty per Reel Reel Size 0 Elamp0.W Elamp0.WT SnPb 000 Inch SnAgu 000 Inch EMIlamp and Elamp are marks of Semtech orporation Top View Showing Laser Mark Note: = Wafer Lot ode Top oating: The top (non-bump side) of the device is a white non-conductive coating. The coating is laser markable and helps prevent die chipping during the PB assembly process. This material is compliant with UL V-0 flammability requirements. Tape and Reel Specification Pin A 0 0 0 0 0 Tape Specifications Device Orientation in Tape 00 Semtech orp.
Elamp0 PROTETION PRODUTS - EMIlamp TM ontact Information Semtech orporation Protection Products Division 00 Flynn Rd., amarillo, A 0 Phone: (0)- FAX (0)-0 00 Semtech orp. 0