Alternative Channel Materials for MOSFET Scaling Below 10nm Doug Barlage Electrical Requirements of Channel Mark Johnson Challenges With Material Synthesis
Introduction Outline Challenges with scaling below 10nm What will the MOS device look like at 10nm Opportunities in alternative channels
2015 10nm Gate Length Devices 1995* 2005** 2015** Gate Length (nm) 300 32 10 EOT (Å) 5.0 1.1 0.6 EOT from Channel and Gate Electrode 1.1 0.7 0.4 Gate Capacitance (µf/cm 2 ) 0.64 1.9 3.5 Gate Oxide Leakage (A/cm 2 ) 600 10000 Power Supply (V) 2.5 1.1 0.8 FAST Free Charge Density (µc/cm 2 ) 1.4 1.7 1.75 Saturation Threshold Voltage (V) 0.35 0.2 0.12 Ioff (µa/µm) NA 0.3 Ion (ma/µm) 0.75 1.09 2.11 Relative Mobility Enhancement 1.3 2 Full Depletion Enhancement 1 1 0.5 Saturation Velocity Enhancement 1 1 1.3 Parasitic Source/Drain (Ω*µm) 180 88 Gate Delay (ps) 7.5 0.86 0.18 Cutoff Frequency (GHz) 21 185 884 Power Delay Product (aj/µm) 1.27 0.29 Static Power Dissipation (µw/µm) NA 0.77 2.6 * Technology for Advanced High-Performance Microprocessors M.T. Bohr, Y.A. El-Mansy, pp. 620-628 1998 IEEE Transactions on Electron Devices ** ITRS Road Map 2004 Updates
Assumptions In this study of electrical performance of the channel we make the following assumptions Material synthesis challenges can be overcome given sufficient experimental resources Effective source-drain doping can be achieved Barrier dielectric can be achieved with unpinned interfaces Metal gates can be formed with work function from -3.5eV to -5.5eV Room Temperature to Room Temperature +150C preferred Evaluation channel properties to determine suitability for sub 10nm gate scaling
Fully Depleted FET Generic fully depleted architecture Source/Drain Carrier Supply Spacer Needs sufficient carriers with sufficient velocity Metal Gate --Tunable to -3.5-5.5eV Gate Dielectric -- 0.5-1.0 nm Channel Spacer Substrate needs to be insulating Source/Drain Carrier Collector Can this be metal?
Fully Depleted FET Generic fully depleted architecture Metal Gate --Tunable to -3.5-5.5eV Source Gate Dielectric -- 0.5-1.0 nm Channel needs to be intrinsic homogenous for V th control Drain Substrate needs to be insulating
Fully Depleted FET Source Metal Gate --Tunable to -3.5-5.5eV Gate Dielectric -- 0.5-1.0 nm Channel Drain Substrate needs to be insulating Source G Drain Channel Depleted material must be able to hold off current in off state Must be able to maintain a large charge density at high velocities in on state V =1.0V V =0.0V Source and Drain resistance is dominant under these conditions
Key Considerations Figure of merit: Off Current On Current Non-ideal sub-threshold effects For relevance must be able to: Form unpinned gate dielectric barrier Tunable gate work function Source/drain doping
Off-On Potential Carrier will see the same on-off potential difference regardless of material On/off potential ratio is improved via subthreshold enhancement Improving the ratio means bringing subthreshold slope closer to ideal
Carrier Velocity Si @ 10nm Source Drain El ect r on Vel oci t yl ( V) 45000000 40000000 35000000 30000000 25000000 20000000 15000000 10000000 5000000 On Sour ce Of f On Channel Lsp Spacer Lg Gat e 0-70 -65-60 -55-50 -45-40 -35-30 -25-20 -15-10 -5 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 X ( nm) Off Spacer v sat Dr ai n Ballistic Transport Mobility Ballistic transport achieved in off state Saturation velocity achieved in contact area
<v> vs. E Length Scale (nm) @1V Switching 1µm 100nm 10nm Carbon Nanotube (Calculated Range for Small Diameter CNT) Electron Drift Velocity( 10 7 cm/s) 10-1 10 0 10 1 0.01 0.1 InSb III-N offer the most significant advantage at relative gate lengths.
Scale Comparison Silicon GaN InSb
Collective Figure of Merit F t vs. Gate Length 10000 1000 GaN InN InGaAs F t (GHz) 100 Si MOSFET InSb 10 AlGaN MOSFET 1 0.001 0.01 0.1 1 10 Gate Length (microns)
Off Current High mobility is actually detrimental to off state performance. Ballistic transport is also not favored for off current performance Tunneling can limit performance if band gap is too small Intrinsic Carrier Concentration limits minimum I off
Conclusions Silicon is tough to beat Wider band gap can be better Smaller gate lengths achievable Mobility, saturation velocity and overshoot velocity can be misleading Larger density of states Maximize current density