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Advanced Design System for Wireline and High Speed Analog Design Tuesday, May 21, 2002Title of Page 1
TRENDS AND CHALLENGES ADS VALUE ADS DESIGN FLOW SOLUTIONS PRODUCT OFFERINGS CONCLUSIONS Page 2
The need for ADS in Wireline Most optical systems contain 80% electronics. Waguih Ishak Technology director Agilent Communications and Optics Networks Lab Page 3
High-speed Lightwave Transmission Switching and Routing Semiconductors (SRS) 10 Gbit/s Transmitter Clock Optical Transport Semiconductors (OTS) Laser Driver 1310-1550 nm (long haul) 850 nm (short haul, board level) Optical Components (OC) Laser CMOS Data Source 16:1 Mux 16 @ 622 MB/s 10 GB/s Re-timing circuit Modulator Driver Modulator Fiber Optic Channel CPU 16 @ 622 MB/s 1:16 DMux 10 GB/s Limiting Amp TIA Photo Detector Receiver Det Page 4
TRENDS AND CHALLENGES FEC = Forward Error Correction Multi-Rate Support (FEC) Power Dissipation Block Diagram Integration CMOS Data Source FEC Coding Gain improves BER CPU Clock 16:1 16 @ 622 MB/s Mux 10 GB/s 16 @ 622 MB/s Jitter (VCO Phase Noise) Multi-Rate Support (FEC) 6-7Vpp drive level at high freq Power Dissipation Waveform distortion / dispersion Active Device Model 1:16 DMux High-Speed Integration Power Dissipation 10 GB/s Det Laser Driver TIA Laser BiCMOS GaAs HBT SiGe - infrastructure InP - instrumentation Power Control Eye Quality RZ Modulation for Long Haul Modulator Photo Detector Tunable Laser Optical Signal Separation Dynamic range of modulator Electrical / Optical interface Fiber Attenuation Chromatic Dispersion (CD) Polarization Mode Dispersion Optical Non-linearities Sensitivity, Dynamic Range Signal Detect Accuracy Optical-Electrical Integration Page 5
TRENDS AND CHALLENGES ADS VALUE Applications Simulations ADS DESIGN FLOW SOLUTIONS PRODUCT OFFERINGS CONCLUSIONS Page 6
Benefits of ADS / IC-CAP for Wireline Leading edge simulation technologies Time Domain / Frequency Domain / EM / Optimization under one environment IC package analysis Board analysis Foundry partners for latest models Design Flow - Cadence Dynamic Link Active Device Model capability (IC-CAP) Page 7
Application Examples Reference design examples Page 8
Multiplexer 16:1 MUX 2:1 MUX 2:1 MUX 2:1 MUX 2:1 MUX 2:1 MUX 2:1 MUX 2:1 MUX 2:1 Data Selector Data Selector Data Selector Data Selector Data Selector Data Selector ADS can be used to design complete MUX/DEMUX Data Selector Amplifier Design Challenges: Signal Timing Jitter Eye diagram Good Impedance match Page 9
Laser Modulator ADS can be used to design electrical portions of the Laser Modulator Design Challenges: CPW Bond Wire model Optical Measured Data Good Impedance match Page 10
Modulator Driver Laser Driver Laser Mod. Driver Optical Modulator ADS can be used to design complete MUX/DEMUX Design Challenge: High Speed Signal and Large Output Signal Requirements Short rise time and Fall time requirements for good eye Opening Minimal Jitter ( Phase Noise) Good impedance match Wide Bandwidth design Page 11
Limiting Amplifier Limiting Amplifier ADS can be used to design Limiting Amplifier for 10 GB/s and 40 GB/s system Limiting Amplifier is the main amplifier in OC-192 & OC768 Limiting Amplifier is used to reshape NRZ data Design Challenges: Ultra wide bandwidth with High gain Minimum Phase shift deviation to achieve small timing jitter Output Power must be constant over a wide dynamic range Page 12
Amplifier with Gain Control Variable Amplifier ADS can be used to design Variable Gain Amplifier Design Challenges: Linear channel flat response over very wide bandwidth Constant group delay throughout band Good input and output return loss Wide gain control dynamic range Low noise figure design Page 13
Trans-Impedance Amplifier Trans-Imp. Amplifier ADS can be used to design Trans-Impedance Amplifier Design Challenges: High Gain over wide Bandwidth High Speed with wide Dynamic Range To achieve lowest possible noise while retaining Bandwidth performance Good Input/Output Return Loss Low Power Consumption Effects of distributed models Include measured S-Parameters from Network analysers or EM simulators Include E/O measurements of laser, detector from Agilent Lightwave analysers. Create and use a behavioral model from simulation or from Data Sheet Create and use an Encoded Model of the TIA Page 14
OEIC Package Design Uses ADS Capability On chip signal distribution, Vias, Coplanar waveguide, Multilayer structures, Spiral Inductors, Bond Wires BGA and other packages Page 15
TRENDS AND CHALLENGES ADS VALUE Applications Simulations ADS DESIGN FLOW SOLUTIONS PRODUCT OFFERINGS CONCLUSIONS Page 16
High Frequency Spice with Convolution Analysis In standard Spice all the frequency-dependent components are approximated with lumped element equivalents High frequency effects such as dispersion and loss at higher frequencies are not taken into account The Convolution engine in ADS High Frequency Spice models accurately all frequency-dependent components (microstrip, S-parameter blocks etc.) Impulse response for all distributed components is calculated, then convolved with input signal to yield output Y ( s) X ( s) H ( s) y( t) x( t) h( t ) d t 0 Unique in ADS Page 17
ADS Simulation of Transimpedance Amplifier (TIA) or Laser Driver Time Domain (using High Frequency Spice and Convolution Simulator) Jitter, Gain, Skew, delay, Eye diagram, Eye Closure Rise time, overshoot, ringing etc. Effects of distributed models of on chip transmission lines and Packages such as BGA Page 18
ADS Simulation of Transimpedance Amplifier (TIA), or Laser Driver Time Domain (using High Frequency Spice and Convolution Simulator) Differential circuits and LVDS Include measured S-Parameters from Network analysers or other sources such as EM simulators Include E/O measurements of laser, detector from Agilent Lightwave analysers. Use a behavioral model of TIA from simulation or from Data Sheet Create and use an Encoded Model of the TIA Page 19
ADS Simulation of Oscillator and Clock Recovery circuits Time Domain (using High Frequency Spice and Convolution Simulator) Jitter, Oscillator start up time, Waveform, Rise time, overshoot, ringing etc. Effects of distributed models of on chip transmission lines and Package such as BGA Include measured S-Parameters from Network analysers or other sources such as EM simulators Create and use an Encoded Model of the Oscillator Page 20
ADS Simulation of Oscillator and Clock Recovery circuits Frequency Domain (Linear and Non-Linear Harmonic Balance, and Circuit Envelope Simulator) Loop gain and phase in Oscillator circuit, Oscillating frequency, level, waveform and spectrum. Ring Oscillators. Phase Noise VS frequency offset Jitter Calculated from Phase Noise PLL circuits, Lock time, Frequency vs Time Effects of distributed models (transmission lines, vias etc) of on chip transmission lines and Package such as BGA Include measured S-Parameters from Network analysers or other sources such as EM simulators Create and use a behavioral model of Oscillator from simulation or from Data Sheet Create and use an Encoded Model of the Oscillator Page 21
Harmonic Balance Operation V V j CV 0 R V V, V... V ) ( 1 2 k The circuit is described by deriving Kirchoff s current law in the frequency domain at each node The system of nonlinear equations so obtained is solved using the Newton-Raphson method Since most nonlinear devices are described by time domain (Spice) models, the simulator has to transform (inverse FFT) the voltage spectrum into the time domain, evaluate the response of the device then transform it back to the frequency domain (FFT) Page 22
HB Oscillator Analysis Phase Noise Simulation FM Flicker noise 1/f 3 Pts/decade FM white noise 1/f 2 PM Flicker noise 1/f PM White noise Start Stop Page 23
Transient-Assisted Harmonic Balance How it works: Runs transient to generate an initial guess Initial guess is transformed from time to frequency domain Use the initial guess with harmonic balance Applications: Highly nonlinear analog/rf circuits Digital circuits (i.e. dividers, phase detectors) Available in ADS Unique in ADS Page 24
TAHB Example Divide by 8 chain of three flip-flops CMOS, 76 MOSFETs examine phase noise after division Run times, P3-500 transient: 96 sec HB signal: 21 sec HB noise: 122 sec for 4 phase noise analyses Page 25
ADS Simulation of IC and PC Board structures Distributed Models and EM simulation In Time or Frequency Domain. PC Board transmission lines and traces, multilayer vias and routing LVDS traces and signals Creating lumped element equivalent models of all of the above. TAPERED LINES MULTI- COUPLED LINES COUPLED CROSSOVER COUPLE D CORNER S Page 26
Agilent Ptolemy Unique in ADS Based on the Ptolemy code from UC Berkeley Simulation environment that supports multiple domains ADS Ptolemy uses the Synchronous Dataflow (SDF) domain for Digital Signal Processing analysis We have added: Timed Synchronous Dataflow (TSDF) domain for co-simulation Large library of behavioral and timedomain models I/O Interfaces Page 27
TRENDS AND CHALLENGES ADS VALUE ADS DESIGN FLOW SOLUTIONS PRODUCT OFFERINGS CONCLUSIONS Page 28
Electronic Design Tools ADS, IC-CAP db(s(2,1)) db(s(1,2)) 20 0-20 -40-60 -80-100 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 freq, GHz frequency domain view (S 11, S 22 etc.), Non-linear response modelled interconnect. LVDS laser driver with transmission lines time domain view of data and crosstalk Simulation of Clock Phase noise and Jitter Page 29
A World Class Integrated Simulation Tools Linear Harmonic Balance Krylov Solver Transient Assisted HB Circuit Envelope Convolution High Frequency SPICE RF System Simulator Ptolemy Ptolemy Fixed Point Digital Filter E-Syn Domain Physical Numeric Time Frequency AC / S-Parameters HF SPICE High Speed Interconnect Library New Harmonic Balance Convolution Momentum Circuit Envelope Ptolemy Synchronous Dataflow Model Composer Ptolemy Timed Synchronous Dataflow (TSDF) Planar EM Advancing Capabilities Page 30
ADS Foundry Support SiGe GaAs HBT GaAs HBT Maxim GST2 & MBIC-1 Clock Optical Transport Semiconductors (OTS) BiCMOS SiGe HBT GaAs HBT Laser Driver SiGe - infrastructure InP - instrumentation TQTRx 0.18um & 0.25um CMOS 16:1 Mux 10 GB/s Re-timing circuit 0.18um & 0.25um CMOS 5AM, 5HP, 6HP & 7HP SiGe BiCMOS SiGe HBT GaAs HBT SiGe - infrastructure InP - instrumentation HCMOS7 0.25um & HCMOS8 0.13um BICMOS 6M & SiGe 6G 0.35um 1:16 DMux 10 GB/s TIA 0.8u BYX SiGe QBIC3 & QBIC4 Det Page 31
ADS Design Flow with Cadence Dynamic Link Cadence Dynamic Link ADS schematic layout Simulations Design Kit DRC / LVS Harmonic Balance Design Kit Parasitic extraction Transient Convolution DesignGuides Interconnect Models Planar EM Post Processing Ptolemy Page 32
xxx xx xxx xxx xxx x xx xxx x xxx x xxx xxx xx xxx xxx xxxx xxx x xxx xxxx IC-CAP Parameter Extraction Methodology for Accurate Device Models Support extraction of industry standard and customized simulation models Open environment customizable to each process Characterize process variations with statistical modeling Modeling System Test Setups Measured Data IC-CAP Integrated Circuit Characterization and Analysis Program Model Parameters XXXXXXX Model Libraries Circuit Design Device Design Process Control Page 33
TRENDS AND CHALLENGES ADS VALUE ADS DESIGN FLOW SOLUTIONS PRODUCT OFFERINGS CONCLUSIONS Page 34
PRODUCT SOLUTIONS HIGH SPEED ANALOG DESIGNER PRODUCT BUNDLES HSAD HSAD Pro HSAD Premier Design Environment X X X Data Display X X X Linear Simulator X X X High Frequency Spice X X X Spice Netlist Translator X X X Passive Circuit DesignGuide X X X Convolution Simulator X X Multi-Layer interonnect Models X X Statistical Design X X RF Passive Circuit Models X X Layout X X Layout Translators X X Momentum X X Momentum Visualization X X Momentum Optimization X Harmonic Balance X RF System Models X Ptolemy X Ptolemy Matrix Models X Analog Model Development X E-Syn X Page 35
E9008A - Agilent High Speed Analog Design Simulation Technology Accurate devices and distributed transmission line models for 40 GB/s design. Linear Simulators to evaluate small signal Performance. Harmonic Balance Simulator for accurate output power characterization and Optimization. Spice and Convolution time domain simulators for accurate time domain simulation for 10 GB/s and 40 GB/s designs. EM simulation capability in integrated environment for package characterization and interconnect modeling. Interconnect Model library. Ptolemy Simulator and Matrix Models Design Flow Design kits supportfrom many commercial foundry. Powerful data processing capabilities for circuit performance characterization. Integrated environment for system and circuit design. Page 36
TRENDS AND CHALLENGES ADS VALUE ADS DESIGN FLOW SOLUTIONS PRODUCT OFFERINGS CONCLUSIONS Page 37
Accurate and Efficient High Speed Analog Design Model 10 & 40 Gb/s with ADS Trans-Impedance Amplifier Distributed Travelling Wave Amplifier Limiting Amplifier Multiplexer/Demultiplexer Design Laser Driver Modulator Driver (large voltage swings) Variable gain Amplifier Variable Attenuators Ring Oscillator (jitter) Clock Recovery Circuit (jitter) Error correction encoders & decoders Interconnect & Package Design Semiconductor Parameters and More.. Page 38
ADS Simulation Capabilites for Optical Wireline Summary Frequency and time domain simulators: Pick the right tool for the job at hand Can do much more than Spice Distributed models and EM simulation Account for high frequency effects that can no longer be ignored Do System, on board, and IC all in one tool Combine everything for end to end simulation with all physical effects Complete Simulation of Transmit and Receive sections Eye Diagram/Eye Closure Jitter Measurements/Transfer Functions Page 39
ADS Capabilities Additional Slides
DC Analysis Operation Capacitors, inductors eliminated Topology checked for circuits with no unique DC solution Iteratively find solution such that sum of all DC currents into each circuit node is zero Uses Newton-Raphson convergence algorithm to find solution for nonlinear devices (BJTs, FETs, diodes) Sum of DC currents must be zero Page 41
AC/S-Parameter Analysis DC analysis is performed to find the bias point Nonlinear devices linearized at the bias point Assumes signal does not perturb the bias Components characterized by their small-signal [S] or [Y] Finds solution such that sum of all AC currents into each circuit node is zero (not iterative) Computes [S] and [Y] of the overall circuit at external ports Calculates response to small sinusoidal signals Page 42
Transient Analysis (SPICE) - Simple RC Circuit Kirchoff s current equations are derived at each node in differential form v(t) v( t) R C dv( t) dt 0 (1) The time derivatives are replaced with discrete-time approximations (integration) The solution in the case of a complex circuit will consist of a system of nonlinear equations which is solved using the Newton-Raphson method Page 43
HB Nonlinear Noise Analysis Large signals at harmonics Small signals on either side harmonics large signals and non-linearities causes mixing Noise from nf translates to IF LO f IF Noise from all components translates to output 0 IF LO RF 2LO 3LO Page 44
Phase Noise as Frequency Modulation All oscillators exhibit sensitivity of oscillation frequency to voltage (VCO) Noise acts to randomly modulate the oscillator frequency -80-20 db/dec -120-160 100 Hz 10 khz 1 MHz Page 45
Phase Noise Mixing Noise mixes with oscillator harmonics -80-120 -160 0 fosc 2fosc 3fosc 100 Hz 10 khz 1 MHz Page 46
TAHB example (2) Transceiver-on-chip: includes RF, analog and digital circuitry Total # of Devices = 14,000+ 13,000+ linear devices including interconnect and substrate parasitics 1200+ non-linear devices 400 BJT s, 60 MOSFET s, 800 diodes Single-tone analysis with 56 harmonics 4.5 hours on an HP J210 workstation with 1GB of RAM Page 47
Spice Vs Harmonic Balance: ADS has them BOTH Standard Spice Solves KCL by Newton Raphson Time Steps determine rise time resolution Error Residuals determine Accuracy Frequencies determined by Fourrier transform-needs long sim. period Standard Spice Models Used Used for decades by Analog and Digital designers Can t simulate non-linear noise such as phase noise ADS HFSPICE CAN SIMULATE JITTER! Harmonic Balance Solves KCL by Newton Raphson # of Harmonics determine rise time resolution Error Residuals Determine Accuracy Frequencies solved for explicitly. Standard Spice Models used Used for decades by RF and Microwave designer. Excellent for non-linear noise and phase noise. Page 48
What ADS can Simulate in Transimpedance Amplifier (TIA) or Laser Driver Frequency Domain (Linear and Non-Linear Harmonic Balance Simulator) Effects of distributed models (transmission lines, vias etc) of on chip transmission lines and Package such as BGA, Crosstalk, Bounce Include measured S-Parameters from Network analysers or other sources such as EM simulators Include E/O measurements of laser, detector from Agilent Lightwave analysers. Create and use a behavioral model of TIA from simulation or from Data Sheet Create and use an Encoded Model of the TIA Page 49
What ADS can Simulate in Mux/Demux and SerDes circuits Time Domain (using High Frequency Spice and Convolution Simulator) Jitter, Rise time, overshoot, ringing etc. Skew, delay Effects of distributed models of on chip transmission lines and Package such as BGA Include measured S-Parameters from Network analysers or other sources such as EM simulators Create and use an Encoded Model of the circuit Create and use behavioral digital model using Ptolemy (instead of transistor level circuit) Page 50
What ADS can Simulate in Mux/Demux and SerDes circuits Frequency Domain Using Harmonic balance (TAHB) Additive Phase noise Additive Jitter calculated from Phase noise Page 51
What ADS can Simulate in Data Source, Encoding and Error Correction circuits Ptolemy Data flow Simulator Develop and create algorithms Implement as high level functional circuits and gates Generate and output HDL Use in end to end simulation of physical layer by cosimulating with analog circuits Page 52
What ADS can Simulate in IC and PC Board structures: EVAL, DUT, and Demo boards Simulate IC on Board Isolate IC and Board effects Correlate simulation with measurements On Evaluation Boards in R&D On DUT boards in Manufacturing Test On customer DEMO boards Page 53
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