Low Phase Noise, LVPECL VCXO (for 150MHz to 160MHz Fundamental Crystals) FEATURES. * Internal 60KΩ pull-up resistor

Similar documents
PL XIN CLK XOUT VCON. Xtal Osc. Varicap. Low Phase Noise VCXO (17MHz to 36MHz) PIN CONFIGURATION FEATURES DESCRIPTION BLOCK DIAGRAM

19MHz to 250MHz Low Phase-Noise XO PAD CONFIGURATION

19MHz to 800MHz Low Phase-Noise XO PIN CONFIGURATION

PL600-27T CLK0 XIN/FIN 1. Xtal Osc CLK1 XOUT CLK2. Low Power 3 Output XO PIN ASSIGNMENT FEATURES DESCRIPTION CLK2 GND VDD FIN CLK0 SOT23-6L

OE CLKC CLKT PL PL PL PL602-39

Low-Power, 1.62V to 3.63V, 1MHz To 150MHz, 1:2 Fanout Buffer IC OE CLK1. DFN-6L (2.0 x 1.3 x 0.6mm) FIN CLK1

Phase Detector. Charge Pump. F out = F VCO / (4*P)

Low-Power, 1.62V to 3.63V, 1MHz to 150MHz, 1:3 Fanout Buffer IC CLK2 VDD CLK0 SOT23-6L

(Prelim inary ) Analog Frequency Multiplier. Oscillator Amplifier

PL565-37/38 VCXO Family

PL560/ VCXO Family

CLK1 GND. Phase Detector F VCO = F REF * (2 * M/R) VCO. P-Counter (14-bit) F OUT = F VCO / (2 * P) Programming Logic

Low-Power 2.25V to 3.63V DC to 150MHz 1:6 Fanout Buffer IC DESCRIPTION

Note: ^ Deno tes 60K Ω Pull-up resisto r. Phase Detector F VCO = F REF * (M/R) F OUT = F VCO / P

PL High Speed Translator Buffer to LVDS FEATURES PIN CONFIGURATION

Phase Detector. Selectable / 1,/ 2,/4,/8. Selectable / 1,/2

Analog Frequency Multiplier

The PL is an advanced Spread Spectrum clock generator (SSCG), and a member of PicoPLL Programmable Clock family.

[S3,S0] REF_SEL. PLL (Phase Locked Loop)

Features. Applications. Micrel Inc Fortune Drive San Jose, CA USA tel +1 (408) fax + 1 (408)

SM General Description. ClockWorks. Features. Applications. Block Diagram

DESCRIPTION CLK1 CLK2 GND CLK1 CLK2 VDD CLK3 CLK4 VDD

SM Features. General Description. Applications. Block Diagram

DESCRIPTION CLKA1 CLKA2 CLKA3 CLKA4 CLKB1 CLKB2 CLKB3 CLKB4

SM Features. General Description. Applications. Block Diagram. ClockWorks GbE (125MHz) Ultra-Low Jitter, LVPECL Frequency Synthesizer

Features. Micrel Inc Fortune Drive San Jose, CA USA tel +1 (408) fax + 1 (408)

ICS HIGH PERFORMANCE VCXO. Features. Description. Block Diagram DATASHEET

Features. Applications

ICS511 LOCO PLL CLOCK MULTIPLIER. Description. Features. Block Diagram DATASHEET

DESCRIPTION CLKOUT CLK2 CLK4 CLK1 VDD GND SOP-8L

LOCO PLL CLOCK MULTIPLIER. Features

ICS502 LOCO PLL CLOCK MULTIPLIER. Description. Features. Block Diagram DATASHEET

SM Features. General Description. Applications. Block Diagram. ClockWorks PCI-e Quad 100MHz Ultra-Low Jitter, HCSL Frequency Synthesizer

SM ClockWorks 10-Gigabit Ethernet, MHz, Ultra-Low Jitter LVPECL Clock Frequency Synthesizer. General Description.

Features. Applications

DSC2022. Low-Jitter Configurable Dual LVPECL Oscillator. Features. General Description. Block Diagram. Applications

Features. Applications

PCI-EXPRESS CLOCK SOURCE. Features

ICS LOW PHASE NOISE CLOCK MULTIPLIER. Features. Description. Block Diagram DATASHEET

Programmable Low-Jitter Precision HCSL Oscillator

Features. Applications

ICS722 LOW COST 27 MHZ 3.3 VOLT VCXO. Description. Features. Block Diagram DATASHEET

DSC2042. Low-Jitter Configurable HCSL-LVPECL Oscillator. General Description. Features. Block Diagram. Applications

ICS LOW PHASE NOISE ZERO DELAY BUFFER AND MULTIPLIER. Description. Features. Block Diagram DATASHEET

ICS OSCILLATOR, MULTIPLIER, AND BUFFER WITH 8 OUTPUTS. Description. Features (all) Features (specific) DATASHEET

ICS LOW EMI CLOCK GENERATOR. Description. Features. Block Diagram DATASHEET

MK2703 PLL AUDIO CLOCK SYNTHESIZER. Description. Features. Block Diagram DATASHEET

LOCO PLL CLOCK MULTIPLIER. Features

MK3727D LOW COST 24 TO 36 MHZ 3.3 VOLT VCXO. Description. Features. Block Diagram DATASHEET

ICS PCI-EXPRESS CLOCK SOURCE. Description. Features. Block Diagram DATASHEET

Features. Applications. Markets

MK3722 VCXO PLUS AUDIO CLOCK FOR STB. Description. Features. Block Diagram DATASHEET

The FS6128 is a monolithic CMOS clock generator IC designed to minimize cost and component count in digital video/audio systems.

LOW PHASE NOISE CLOCK MULTIPLIER. Features

DSC2011. Low-Jitter Configurable Dual CMOS Oscillator. General Description. Features. Block Diagram. Applications

Low-Jitter Precision LVPECL Oscillator

PI6CX201A. 25MHz Jitter Attenuator. Features

PT7C4502 PLL Clock Multiplier

ICS LOW PHASE NOISE ZERO DELAY BUFFER AND MULTIPLIER. Description. Features. Block Diagram DATASHEET

ICS LOW EMI CLOCK GENERATOR. Features. Description. Block Diagram DATASHEET

Low-Jitter, Precision Clock Generator with Two Outputs

Programmable Low-Jitter Precision LVDS Oscillator

ICS276 TRIPLE PLL FIELD PROGRAMMABLE VCXO CLOCK SYNTHESIZER. Description. Features. Block Diagram DATASHEET

PI6C :4 24MHz Clock Buffer. Description. Features. Applications. Block Diagram. Pin Configuration (16-Pin TSSOP) 16-pin (173 mil) TSSOP

ICS507-01/02 PECL Clock Synthesizer

PI6C49X0208. High Performance 1:8 Multi-Voltage CMOS Buffer

MK3721 LOW COST 16.2 TO 28 MHZ 3.3 VOLT VCXO. Description. Features. Block Diagram DATASHEET. MK3721D is recommended for new designs.

ICS LOW EMI CLOCK GENERATOR. Description. Features. Block Diagram DATASHEET

12-27 MHz XO IC with 1 Pair of LVDS and 1 CMOS Outputs

SY58608U. General Description. Features. Functional Block Diagram

Low-Jitter, 8kHz Reference Clock Synthesizer Outputs MHz

ICS QUAD PLL CLOCK SYNTHESIZER. Description. Features. Block Diagram PRELIMINARY DATASHEET

MK2705 AUDIO CLOCK SOURCE. Description. Features. Block Diagram DATASHEET

Preliminary Rev. M Accusilicon AS318-B Series Professional Audiophile Crystal Oscillator

ULTRA PRECISION 4 4 CML SWITCH WITH INTERNAL I/O TERMINATION

PL V-3.3V Low-Skew 1-4 Differential PECL Fanout Buffer

Features VDD 2. 2 Clock Synthesis and Control Circuitry. Clock Buffer/ Crystal Oscillator GND

Features. EXTERNAL PULLABLE CRYSTAL (external loop filter) FREQUENCY MULTIPLYING PLL 2

Features. 1 CE Input Pullup

ICS CLOCK SYNTHESIZER FOR PORTABLE SYSTEMS. Description. Features. Block Diagram PRELIMINARY DATASHEET

High-Frequency Programmable PECL Clock Generator

DSC400. Configurable Four Output, Low Jitter Crystal-less Clock Generator. General Description. Block Diagram. Applications.

PI6LC48S25A Next Generation HiFlex TM Ethernet Network Clock Generator

MK VCXO AND SET-TOP CLOCK SOURCE. Description. Features. Block Diagram DATASHEET

PT7C4511. PLL Clock Multiplier. Features. Description. Pin Configuration. Pin Description

VX-805 Voltage Controlled Crystal Oscillator

NOT RECOMMENDED FOR NEW DESIGNS. Features. Applications. Markets

SY89847U. General Description. Functional Block Diagram. Applications. Markets

ICS512 LOCO PLL CLOCK MULTIPLIER. Description. Features. Block Diagram DATASHEET

3.3V/5V 2.5GHz PECL/ECL 1:4 FANOUT BUFFER WITH 2:1 INPUT MUX

ICS501 LOCO PLL CLOCK MULTIPLIER. Description. Features. Block Diagram DATASHEET

VVC1 VVC2 Voltage Controlled Crystal Oscillator

PI6C557-03AQ. PCIe 2.0 Clock Generator with 2 HCSL Outputs for Automotive Applications. Description. Features. Pin Configuration (16-Pin TSSOP)

TRIPLE PLL FIELD PROG. SPREAD SPECTRUM CLOCK SYNTHESIZER. Features

MK SPREAD SPECTRUM MULTIPLIER CLOCK. Description. Features. Block Diagram DATASHEET

MK SPREAD SPECTRUM MULTIPLIER CLOCK. Description. Features. Block Diagram DATASHEET

VVC4 Voltage Controlled Crystal Oscillator

FailSafe PacketClock Global Communications Clock Generator

Features. Applications. Markets

Features VDD. PLL Clock Synthesis and Spread Spectrum Circuitry GND

Transcription:

0.952mm VDD QB PL586-55/-58 FEATURES DIE CONFIGURATION Advanced non multiplier VCXO Design for High Performance Crystal Oscillators Input/Output Range: 150MHz to 160MHz Phase Noise Optimized for 155.52MHz: -68dBc @10Hz, -152dBc @100kHz Very low Phase Jitter: <100fs RMS High Pull Range: ±100ppm Linearity: <5% Integrated Variable Capacitors Complementary LVPECL Outputs Power Supply: 3.3V ±10% Available in Die or Wafer Form XIN X 7 8 Die ID 0.952mm 6 5 4 3 Q VSS DESCRIPTION The PL586-55/-58 is a non-multiplier VCXO IC specifically designed to pull fundamental mode crystals from 150MHz to 160MHz. This IC achieves a typical pull range of ±100ppm with <5% linearity. The phase noise performance is optimized for close-in performance and with <100fs phase jitter, makes this an ideal solution for all high end clocking applications such as SONET, WiMax, CPRI, OBSAI, Fiber Channel, and any application where performance and quality are required. DIE SPECIFICATIONS Name Size Reverse side Pad dimensions Thickness Value 952 micron x 952 micron GND 80 micron x 80 micron 8 mil VCON (0,0) 1 2 OE PUT ENABLE LOGIC PL586-55 OE State (Pad 4) Output Buffers State 0 Outputs Tri-Stated 1 (Default) Outputs Enabled * Internal 60KΩ pull-up resistor PUT ENABLE LOGIC PL586-58 OE State (Pad 4) Output Buffers State 0 (Default) Outputs Enabled 1 Outputs Tri-Stated * Internal 60KΩ pull-down resistor BLOCK DIAGRAM OE XIN X VCON Xtal Osc Varicap Q QB Micrel Inc. 2180 Fortune Drive San Jose, CA 95131 USA tel +1(408) 944-0800 fax +1(408) 474-1000 www.micrel.com Rev 3/6/13 Page 1

PAD ASSIGNMENT Pad # Name X ( m)* Y ( m)* Description 1 VCON -194-365 Voltage Control input 2 X -372-190 Crystal output connection 3 XIN -372 158 Crystal input connection 4 VDD -117 329 V DD connection 5 QB 140 315 Complementary LVPECL output 6 Q 315 75 LVPECL output 7 VSS 373-127 GND connection 8 OE 373-373 Output enable pin. Internal pull up (-55) or pull down (-58). * Note: Referenced to center of the die. ELECTRICAL SPECIFICATIONS 1. Absolute Maximum Ratings PARAMETERS SYMBOL MIN. MAX. UNITS Supply Voltage V DD 4.6 V Input Voltage, DC V I V SS-0.5 V DD+0.5 V Output Voltage, DC V O V SS-0.5 V DD+0.5 V Storage Temperature T S -65 150 C Ambient Operating Temperature T A -40 85 C HBM ESD Protection 2,000 V Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permane nt damage to the device and affect product reliability. These condition s represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. *Operating temperature is guaranteed by design. Parts are tested to commercial grade only. Micrel Inc. 2180 Fortune Drive San Jose, CA 95131 USA tel +1(408) 944-0800 fax +1(408) 474-1000 www.micrel.com Rev 3/6/13 Page 2

2. Voltage Control Crystal Oscillator VCXO Stabilization Time * T VCXOSTB From power valid 10 ms XTAL C 1 = 6.8, C 0/C 1 = 270 120 ppm 0V VCON V VCXO Pullability * DD (at 25 C) XTAL C 1 = 3.7, C 0/C 1 = 480 70 ppm 0V VCON V DD (at 25 C) Varicap Control Range * VCON = 0 to V DD 0 3.3 V Linearity * 0.0V VCON 3.3V 7 % 0.3V VCON 3.0V 2.5 % VCON Input Impedance * DC Input resistance 10 MΩ VCON Modulation BW * 0V VCON V DD, -3dB 30 khz Note: Parameters denoted with an asterisk (*) represent nominal characterization data and are not production tested to any specific limits. 3. Crystal Specifications Crystal Resonator Frequency F XIN Fundamental Mode, AT cut 150 160 MHz Crystal Loading Rating C L (xtal) VCON = 1.65V 5 pf Shunt Capacitance C 0 2.0 pf Motional Capacitance C 1 Recommended for at least ±100ppm Frequency Pulling 5.5 ff Recommended ESR R E C 0 2.0pF 10 Ω 4. General Electrical Specifications C 0 1.5pF 12 Ω Supply Current I DD Standard LVPECL Loading (See LVPECL Levels Test Circuit, page 4) 50 ma Operating Voltage V DD 2.97 3.3 3.63 V Output Clock Duty Cycle @ V DD 1.3V (See LVPECL Transition Time Waveform, page 4) 45 50 55 % Short Circuit Current 50 ma Micrel Inc. 2180 Fortune Drive San Jose, CA 95131 USA tel +1(408) 944-0800 fax +1(408) 474-1000 www.micrel.com Rev 3/6/13 Page 3

5. Jitter Specifications PARAMETERS CONDITIONS MIN. TYP. MAX. UNITS Period Jitter RMS At 155.52MHz, with capacitive 2.5 decoupling between V DD and ps Period Jitter pk-to-pk GND. Over 10,000 cycles 20 Integrated Jitter RMS at 155.52MHz Integrated 12 khz to 20 MHz 90 fs 6. Phase Noise Specifications PARAMETERS FREQUENCY @10Hz @100Hz @1kHz @10kHz @100kHz @1MHz @10MHz UNITS Phase Noise, 155.52MHz -68 98 124 144 152 156 158 dbc/hz relative to carrier Note: Phase Noise measured at VCON = 0.3V to 3.0V. 7. LVPECL Electrical Characteristics Output High Voltage V OH R L = 50 Ω to V DD 1.025 V DD 0.950 V DD 0.880 V Output Low Voltage V OL (V DD 2V) (see figure) V DD 1.810 V DD 1.700 V DD 1.620 V 8. LVPECL Switching Characteristics Clock Rise Time t r @20/80% of output waveform 400 600 ps Clock Fall Time t f @80/20% of output waveform 400 600 ps LVPECL Levels Test Circuit LVPECL Transistion Time Waveform DUTY CYCLE VDD 45-55% 55-45% 50? 2.0V 80% 50% 50? 20% t R t F Micrel Inc. 2180 Fortune Drive San Jose, CA 95131 USA tel +1(408) 944-0800 fax +1(408) 474-1000 www.micrel.com Rev 3/6/13 Page 4

ORDERING INFORMATION For part ordering, please contact our Sales Department: 2180 Fortune Drive, San Jose, CA 95131, USA Tel: (408) 944-0800 Fax: (408) 474-1000 PART NUMBER The order number for this device is a combination of the following: Part number, Package type and Operating temperature range Part Number PL586-5X XX Packaging Option D = Die W = Wafer Temperature Range C=Commercial (0 C to 70 C) Order Number PL586-55DC PL586-58DC PL586-55WC PL586-58WC Packaging Die Waffle Pack Wafer Micrel Inc., reserves the right to make changes in its products or specifications, or both at any time without notice. The in formation furnished by Micrel is believed to be accurate and reliable. However, Micrel makes no guarantee or warranty concerning the accuracy of said info rmation and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this pr oduct. LIFE SUPPORT POLICY: Micrel s products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of Micrel Inc. Micrel Inc. 2180 Fortune Drive San Jose, CA 95131 USA tel +1(408) 944-0800 fax +1(408) 474-1000 www.micrel.com Rev 3/6/13 Page 5