A 6.0 GHZ ICCO (INDUCTOR-LESS CURRENT CONTROLLED OSCILLATOR) WITH LOW PHASE NOISE

International Journal of Electrical Engineering & Technology (IJEET) Volume 7, Issue 5, September October, 2016, pp.01 07, Article ID: IJEET_07_05_001 Available online at http://www.iaeme.com/ijeet/issues.asp?jtype=ijeet&vtype=7&itype=5 ISSN Print: 0976-6545 and ISSN Online: 0976-6553 Journal Impact Factor (2016): 8.1891 (Calculated by GISI) www.jifactor.com IAEME Publication A 6.0 GHZ ICCO (INDUCTOR-LESS CURRENT CONTROLLED OSCILLATOR) WITH LOW PHASE NOISE Chakaravarty D Rajagopal Universiti Sains Malaysia, 14300 Nibong Tebal, Penang. Malaysia. Dr. Othman Sidek Universiti Sains Malaysia, 14300 Nibong Tebal, Penang. Malaysia. ABSTRACT This article presents a novel design of 5-stage ICCO (Inductor-less Current Controlled Ring Oscillator). Simulation was carried out using 180nm CMOS Technology from Silterra. The results of the simulation are quite remarkable where a peak frequency of 6.0 GHz along with a low phase noise of -115.67 dbc/hz at 1MHz offset was achieved. The tuning range of this design was at 2.89 GHz, with lowest frequency of 2.11 GHz. This design employs CMOS cross coupled delay cells. The key ingredient in this design was the usage of active inductor (thus inductor-less) and current source circuit to help in improving the switching speed and the noise parameters. Key words: VLSI, CMOS, Differential Delay, Negative Skew, Phase Noise, LC Oscillators, Current Source, Active Inductor Cite this Article: Chakaravarty D Rajagopal and Dr.Othman Sidek, A 6.0 GHz ICCO (Inductor- Less Current Controlled Oscillator) with Low Phase Noise. International Journal of Electrical Engineering & Technology, 7(5), 2016, pp. 01 07. http://www.iaeme.com/ijeet/issues.asp?jtype=ijeet&vtype=7&itype=5 1. INTRODUCTION PLL (Phase-locked Loop) has become a very critical component in any high-speed wireless communication systems. This is due to the fact that the PLL controls the functions of data recovery, clock control, and synchronization by providing the timing basis. Within the heart of the PLL resides the voltage or current controlled oscillators (VCO/CCO). Since these oscillators directly provide the output clock of the PLL, it is widely considered the most critical and crucial circuit piece in PLL. CMOS oscillators can be easily built in the form of ring structures or of relaxation circuits or of even an LC resonant circuit. LC oscillator, by far, has been dominant in many high-speed wireless communication systems. This is simply because of the presence of inductance-capacitance (LC) in the oscillator makes the circuit a resonant network [1]. The resonance creates a large Q factor and helps tremendously in providing the best noise and frequency performance. However, LC circuit in CMOS process does come with some drawbacks. First of all, it increases the cost and the complexity of the chip due to layout of the inductor. Along with this, LC circuits often time has problems in controlling the eddy http://www.iaeme.com/ijeet/index.asp 1 editor@iaeme.com

Chakaravarty D Rajagopal and Dr.Othman Sidek current. Thus it has become a necessity to find alternate solution to replace these LC oscillators which is less complex, less costly but with equal performance. Speaking of finding an alternative, ring oscillators seem to be the first choice due to its simplicity. Ring oscillators are less costly and less complex and as said above are easily built on any CMOS process. The design is extremely straight forward where a string of inverters are connected in a ring as shown in Figure 1. This simple architecture is very capable of wide frequency tuning range along with multiphase outputs. Five-stage ring oscillator is shown in Figure 1. Figure 1 Conventional Five-Stage Ring Oscillator However, phase noise on this ring oscillator is a disaster. The main reason is due to the missing of passive LC network. In an effort to introduce the resonant network into the conventional ring oscillator which can improve the phase noise, this paper presents the idea of deploying active inductor as compared to the passive inductor for the LC network. This novel idea is carefully designed such that it doesn t compromise the overall characteristics of CMOS ring oscillators. Moreover, this design also replaces the voltage source with the current source to help increase the switching speed thus increasing the peak frequency. 2. ACTIVE INDUCTOR CROSS COUPLED DELAY CELL In attempting to replace the passive inductor network with active inductor network, it is very important that we choose a design that produces a very similar output without much compromise. Figure 2 below is one such design. Figure 2(A) is the typical LC cross coupled delay cell which has a great phase noise performance. However passive inductors have relatively small inductance, heavy interaction with substrate and larger die area since they are realized using an on-chip spiral layout. Thus passive inductors are generally costly. To overcome this issue, the passive inductor is replaced with active inductors in the same delay cell. One can synthesize an inductor in many ways such as using self-biased MESFET [2] technology or the robust CMOS [3, 4] technology. The proposal to use active inductor is shown in Figure 2(B). Figure 2 VCO delay cell. (A) Delay cell with passive inductor. (B) Delay cell with active inductor. http://www.iaeme.com/ijeet/index.asp 2 editor@iaeme.com

A 6.0 GHz ICCO (Inductor-Less Current Controlled Oscillator) with Low Phase Noise The RLC network in the Figure 2(B) is formed by M res and M ind transistors. To measure the performance of the active inductor, both circuits in Fig. 2(A-B) were simulated by inputting square wave at V in+ and V in-. The output response at V out+ and V out- is shown in Fig 3. It is quite remarkable to note that the output response of the active inductor delay cell (B) is very much similar to the one with the passive inductor (A). This is a huge achievement and proves that replacing the passive inductor with the active inductor can be done without much loss of performance. Figure 3 Output voltage of VCO delay cell. (A) Delay cell with passive inductor. (B) Delay cell with active inductor. 3. CURRENT MODE TECHNIQUES In powering up circuits, voltage supply, V DD has been common for many applications. Alternatively these circuits can be operated in current mode I DD. Figure 4 below shows the connection of supply voltage V DD and its core supply current I DD for a CMOS inverter ring oscillator. The advantage of using a current mode switching is twofold. First of all, the switching speed is improved, meaning the oscillator tends to have higher operating frequency. Secondly, the current mode aids in the improvement of phase noise of the oscillator. Figure 4 Conventional Ring Oscillator: Voltage mode supply (top) Current mode supply (bottom). To prove the above statement, phase noise response and the operating frequency for the five-stage conventional ring oscillator (shown as Figure 4 above) simulated using Silterra 180nm CMOS technology parameters with Cadence s HSPICE. Table 1 below shows the results. http://www.iaeme.com/ijeet/index.asp 3 editor@iaeme.com

Chakaravarty D Rajagopal and Dr.Othman Sidek Table 1 Simulation results of Phase Noise at 1MHz offsetand Operating Frequency in Voltage Mode and Current Mode. The results in Table 1 clearly tells that the phase noise and the operating frequency of the five-stage oscillator which is controlled by current, sees an improvement of about 4dBc/Hz to its voltage controlled counterpart. PMOS current mirror technique using 3.3V I/O transistors is adopted to supply the desired I DD to the oscillator as depicted by Figure 5. Figure 5 Conventional ring oscillator implementing PMOS current Mirror and the connections for voltage mode and current mode supply. 4. INDUCTOR-LESS CURRENT CONTROLLED OSCILLATOR (ICCO) Techniques explained in Section 2 and Section 3 has become the fundamental application in designing the novel current controlled inductor-less oscillator (ICCO). This novel design is aided with the negative delay skew techniques [5,6]. The architecture of the ICCO is shown in Figure 6. The proposed oscillator comprises of active inductor dual delay cell (Section 2) and operated in current mode using PMOS current mirror technique (Section 3). Figure 6 Inductor-less Current Controlled Oscillator (ICCO) and Active Inductor Differential Delay Cell http://www.iaeme.com/ijeet/index.asp 4 editor@iaeme.com

A 6.0 GHz ICCO (Inductor-Less Current Controlled Oscillator) with Low Phase Noise Figure 7 shows the ICCO layout which is drawn on Silterra 180nm CMOS technology. The layout was further used to extract the device parameters for the simulation purposes. Figure 7 Layout of Five-Stage ICCO. The simulation result of the ICCO using the 180nm extracted device parameters reveals a peak operating frequency of 5.99GHz. The simulated phase noise was -115.67dBc/Hz at the peak frequency and at 1MHz offset. Figure 8 below shows the results. Each delay stage of the ICCO was set with 0.5pF driving capacitance while the current mirror voltage was set to 3.3V. Figure 8 Simulated ICCO Oscillation of 6.0 GHz and Phase Noise of -115.67dBc/Hz at 1 MHz offset. The ICCO went through rigorous simulation by varying the I DD settings. Table 2 below shows the simulation setup and the simulated output frequency and the phase noise of the ICCO for various setting of the I DD. The table clearly shows that the ICCO attains a tuning frequency range of 2.88 GHz. Such a wide tuning range is made possible by the use of current mode circuit and the active inductor. http://www.iaeme.com/ijeet/index.asp 5 editor@iaeme.com

Chakaravarty D Rajagopal and Dr.Othman Sidek Table 2 Simulation Setup and Simulated Oscillation Frequency and Phase Noise (at 1MHz offset) of the ICCO for various I DD This work was compared against many other well-known works [7-11] as shown in Table 3 below. It is clearly noted that this work is superior in both the phase noise performance and the operating frequency performance. On top of that, this work is also much smaller in the layout size (hence cheaper) due to the use of the active inductor. This indicator is important for this work when compared specifically against [11]. Work [11] achieves almost same operating frequency as this work but uses passive inductor, thus more costly than this work. Overall, current mode sourcing and active inductor implementation has undeniably proved that they play a major role in oscillators key performance features. Table 3 Comparison of this work against others 5. CONCLUSIONS This paper proposes a ring oscillator with active inductor load and controlled by current source for an improved frequency oscillation and an improved phase noise. The proposed oscillator achieves a peak oscillation at 5.99 GHz and a phase noise of -115.67 dbc/hz at 1MHz frequency offset. This is quite a significant performance and clearly capable of being used in high speed communications applications. REFERENCES [1] B. Razavi, "A study of phase noise in CMOS oscillators", IEEE J. Solid-State Circuits, vol. 31, pp.331-343 1996 [2] S. Hara, T. Tokumitsu, T. Tanaka and M. Aikawa, "Broadband monolithic microwave active inductor and its application to miniaturized wide-band amplifiers." IEEE Trans. Microwave Theory and Appl., vol. 36, no. 12, pp. 1920-1924, 1988. [3] E. Sackinger and W. Fischer, "A 3-GHz 32-dB CMOS limiting amplifier for SONET OC-48 receivers." IEEE J. Solid-State Circuits, vol. 35, no. 12, pp. 1884-1888, 2000. [4] S. Song, S.Park and H.Yoo, "A4-Gb/s CMOS clock and data recovery circuit using 1/8-rate clock technique." IEEE J. Solid-State Circuits, vol. 38, no. 7, pp. 1213-1219, 2003. http://www.iaeme.com/ijeet/index.asp 6 editor@iaeme.com

A 6.0 GHz ICCO (Inductor-Less Current Controlled Oscillator) with Low Phase Noise [5] S.-J. Lee, B. Kim, and K. Lee, "A novel high-speed ring oscillator for multiphase clock generation using negative skewed-delay scheme", IEEE J. Solid-State Circuits, vol. 32, pp.289-291 1997 [6] [6] C. H. Park and B. Kim, "A low-noise, 900-MHz VCO in 0.6-µm CMOS", IEEE J. Solid-State Circuits, vol. 34, pp.586-591 1999 [7] L. Lu, H. Hsieh, Y. Liao, A wide tuning-range CMOS VCO with a differential tunable active inductor, IEEE Transactions on Microwave Theory and Techniques, Vol. 54, No. 9, pp. 3462 3468, 2006 [8] Ms. Rashmi K Patil and Prof (Ms).Vrushali G Nasre, Wide-Frequency-Range CMOS Voltage Controlled Oscillator for Phase Lock Loop A Review. International Journal of Electronics and Communication Engineering & Technology (IJECET), 3(1), 2012, pp.10-16. [9] A. Tang, F. Yuan, E. Law, A new CMOS active transformer QPSK modulator with optimal bandwidth control, IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 55, No. 1, pp. 11 15, 2008 [10] A. Tang, F. Yuan, E. Law, Class AB CMOS active transformers Voltage-Controlled Oscillators, ISSSE '07, International Symposium on Signals, Systems and Electronics, pp. 501 504, Montreal, 2007 [11] A. Tang, F. Yuan, E. Law, Low-noise CMOS active transformer voltage-controlled oscillators, MWSCAS 50th Midwest Symposium on Circuits and Systems, pp. 1441 1444, Montreal, 2007 [12] S. S. Khot, P. W. Wani, M. S. Sutaone and S.K.Bhise, A 555/690 MSPS 4-Bit CMOS Flash ADC Using TIQ Comparator. International Journal of Electrical Engineering & Technology (IJEET), 3(2), 2012, pp. 373 882. [13] N. Yangqing, C. Baoyong, W. Zhihua, A CMOS LC VCO with 3.2-6.1GHz tuning range, Chinese Journal of Semiconductors, vol. 28, no. 4, pp. 526-529, 2007. http://www.iaeme.com/ijeet/index.asp 7 editor@iaeme.com