Prof. Paolo Colantonio a.a. 20 2
Field effect transistors (FETs) are probably the simplest form of transistor, widely used in both analogue and digital applications They are characterised by a very high input resistance and small physical size, and they can be used to form circuits with a low power consumption They are widely used in ery Large Scale Integration (LSI) There are two basic forms: insulated gate FETs junction gate FETs Many forms, but basic operation is the same a voltage on a control input produces an electric field that affects the current between two other terminals when considering amplifiers we looked at a circuit using a control device a FET is a suitable control device o IR The current I is controlled by the input signal i Thus the output signal o is controlled by the input signal i If an appropriate gain is given by the control device, it behaves like a voltage amplifier Prof. Paolo Colantonio 2 24
FETs are 3 terminal devices drain (d) source (s) gate (g) The gate is the control input oltages are given symbols of the form XX, where X and Y correspond to the symbols of two of the device s terminals (example GS ) Currents are given symbols of the form I Z, where Z correspond to the device associated terminal (example I D ) Upper case letters used for steady quantities GS or I D Lower case letters for varying quantities v gs or i d Special notation for power supply voltage or current, by doubling the subscript associated to the device terminal DD, SS, I DD, I SS Prof. Paolo Colantonio 3 24
Such devices are sometimes called IGFETs (insulated gate field effect transistors) or sometimes MOSFETs (metal oxide semiconductor field effect transistors) Digital circuits constructed using these devices are usually described as using MOS technology Here we will describe them as MOSFETs These devices are realized in either n channel or p channel semiconductor material Prof. Paolo Colantonio 4 24
An n channel device is formed by taking a p type semiconductor (the substrate, namely bulk, b) and forming n type regions within it to represent the drain and source pads Electrical connections are made to these regions to form the drain and source electrodes A thin n type channel is then formed to join these two regions (the channel) This channel is covered by an insulating oxide layer and then by a metal gate electrode Electrical connections are made to the gate an substrate Usually the substrate is internally connected to the source to form a three terminal device (i.e. with only three external connections) Prof. Paolo Colantonio 5 24
Gate voltage controls the thickness of the channel Consider an n channel device making the gate more positive attracts electrons to the gate and makes the channel thicker reducing the resistance of the channel. The channel is said to be enhanced making the gate more negative repels electrons from the gate and makes the channel thinner increasing the resistance of the channel. The channel is said to be depleted Prof. Paolo Colantonio 6 24
Devices as described above are termed depletion enhancement MOSFETs or simply DE MOSFETs Some MOSFETs are constructed so that in the absence of any gate voltage there is no channel Such devices can be operated in an enhancement mode, but not in a depletion mode (since there is no channel to deplete) These are called Enhancement MOSFETs Both forms of MOSFET are available as either n channel or p channel devices Prof. Paolo Colantonio 7 24
Sometimes known as a JUGFET, most often with the common name JFET As in a MOSFET, conduction takes place through a channel formed in a semiconductor material Here the insulated gate of a MOSFET is replaced with a reverse biased pn junction Since the gate junction is always reverse biased no current flows into the gate and it acts as if it were insulated Prof. Paolo Colantonio 8 24
The reverse biased gate junction produces a depletion layer in the region of the channel The gate volt controls the thickness of the depletion layer and hence the thickness of the channel Consider an n channel device the gate will always be negative with respect to the source to keep the junction between the gate and the channel reverse biased making the gate more negative increases the thickness of the depletion layer, reducing the width of the channel increasing the resistance of the channel Prof. Paolo Colantonio 9 24
The arrow shows the polarity of the device It points towards and n type channel or away from in a p type channel Prof. Paolo Colantonio 0 24
While MOSFETs and JFETs operate in different ways, their characteristics are quite similar Input characteristics in both MOSFETs and JFETs the gate is effectively insulated from the remainder of the device Output characteristics consider n channel devices usually the drain is more positive than the source the drain voltage affects the thickness of the channel Prof. Paolo Colantonio 24
The applied voltage DS produces a drain current I D through the channel between the drain and the source Such a current produces a potential drop due to the channel resistance The potential gradually falls along the channel The thickness of the channel is mainly controlled by the voltage applied to the gate but it is also influenced by the drain to source voltage Prof. Paolo Colantonio 2 24
For small values of DS, the behavior of the channel resembles that of a resistor, with the drain current I D being proportional to the drain voltage DS The value of this effective resistance is controlled by the gate voltage GS It decreases as GS is made more positive This is referred as the ohmic region of the device s operation As DS is increased the channel becomes more tapered and it thickness is reduced to approximately zero at the end near the channel The channel in this situation is said to be pinched off and the value of DS is called pinch off voltage This does not stop the flow of current, while preventing its any further increase This is referred to as the saturation region of the device s operation Prof. Paolo Colantonio 3 24
If GS is kept constant, while increasing DS the current I D initially rises (almost) linearly with the applied voltage (ohmic region) then above the pinch off voltage becomes essentially constant (saturation region) arying GS, the effective resistance of the channel in the ohmic region and also the value of the steady current is changed Prof. Paolo Colantonio 4 24
The DE MOSFETs are used with both positive and negative gate voltages, while MOSFETs use only one polarity (positive GS for n channel type, NMOS, negative for p type, PMOS) The gate voltage at which the device starts to conduct is called threshold voltage T For n type DE MOSFET it will have a negative value of a few volts For enhancement MOS a positive value of a few volts at pinch off DS GS T I D [ma] 0 9 8 7 Locus of pinch-off = - DS GS T GS =+2 GS =+ Enhancement I D [ma] 0 9 8 7 Locus of pinch-off = - DS GS T GS =+9 GS =+8 I DSS 6 5 4 3 2 0 5 0 5 20 25 GS =0 GS =- GS =-2 GS =-3 GS =-4 GS =-5 = [] DS T Depletion 6 5 4 3 2 0 5 0 5 20 25 GS =+7 GS =+6 GS =+5 GS =+4 GS =+3 GS [] DS =+2 = T Prof. Paolo Colantonio 5 24
The output characteristic of a JFET are similar to those of MOSFETs, except that the useful range of GS is different The drain current produced for GS=0 is termed the drain to source saturation current IDSS The gate voltage at which the channel stops conducting is now called pinch off voltage P at pinch off DS GS P I DSS I D [ma] 0 9 8 7 6 5 4 3 2 0 Locus of pinch-off = - DS GS P 5 0 5 20 25 GS =0 GS =- GS =-2 GS =-3 GS =-4 GS =-5 GS =-6 [] DS GS P Prof. Paolo Colantonio 6 24 =-7 =
It represents the relationship between the input voltage GS and the output current I D Obviously there is no linear relationship between GS and I D However, if the device remains within the saturation region, it is possible to plot such relationship Similar shape for all forms of FET but with a different offset I D I D I D DE NMOS NMOS JFET I DSS I DSS T GS T GS P GS 2 I K D GS T I D IDSS Which can be rearranged into the form GS P 2 2 I K' D GS P Prof. Paolo Colantonio 7 24
The relationship between the input voltage GS and the output current I D does not show a linear response, but over a small region might be considered to approximate a linear response DE N MOS N MOS N JFET When operating about its operating point the transfer characteristic can be described by its slope This quantity has units of current/voltage, which is the reciprocal of resistance (that is conductance) It is called the transconductance, g m ID did i I d D gm d v GS GS gs GS Prof. Paolo Colantonio 8 24
In a real FET, in the saturation region the current I D slightly increase with DS I D [ma] Locus of pinch-off = - DS GS T GS -/ [] DS The slope of the I curve in the saturation region represents a resistance r d Prolonging the characteristic in the saturation region towards left, all of them cross in the same point at DS = /, usually referred as Early s voltage Typical values of are between 0.0 and 0.03 2 I K D GS T DS Prof. Paolo Colantonio 9 24
The transconductance g m is proportional to the square root of the drain current MOSFET JFET di D gm 2KGS T d GS I D 2K 2 K I K D g m di 2 D GS IDSS dgs P P 2 I I D DSS I DSS 2 P I DSS P The small signal equivalent circuit models the behaviour of the device for small variations of the input about the operating point I D r d is given by the slope of the output characteristic and, for this reason, is also known as the output slope resistance Prof. Paolo Colantonio 20 24
At high frequencies more sophisticated models are used The gate and the channel in a MOSFET are separated by an insulator, resembling a capacitor In a JFET, the insulator is replaced by a depletion layer, which has the same effect In both case capacitances are present between the gate and the channel As the channel is joined to the drain at one end and to the source at the other, capacitance is present between the gate and each of the other terminals The reverse biased junction between drain and substrate also acts as a capacitor Since the substrate is normally joined to the source, it results in a capacitance between drain and source Prof. Paolo Colantonio 2 24
Consider the case A, where an impedance Z is connected between two points of a network characterised by a voltage gain K It is possible to make the electrical transformation as case B The two networks must have the same voltages at the external nodes A I Z I 2 B A= / 2 2 Z I A = / 2 I 2 Z 2 2 I 2 A Z Z I Z Z Z A I A Z Z 2 2 2 I 2 Z 2 2 Z A A Z2 Z A Prof. Paolo Colantonio 22 24
It is possible to consider a dual effect The two networks must have the same mesh currents A A=-I/ I 2 I 2 B Z Z 2 A=-I/ I 2 I 2 N 2N 2 N 2N 2 I N I 2 I N I 2 Z Z I I Z I A N 2 N I Z I N Z Z A I 2 2N ZI I22N ZI2 A I Z I 2 2N 2 2 AI Z2 Z Z AI AI Prof. Paolo Colantonio 23 24
Considering the Miller effect Z Z A A Z2 Z A A C C A gd gd A C C C A gd gd gd C gd C A gd C C A gd gd C C C A T gs gd C C C out ds gd Prof. Paolo Colantonio 24 24