A Self-Aligned Process for High-Voltage, Short- Channel Vertical DMOSFETs in 4H-SiC

Purdue University Purdue e-pubs Birck and NCN Publications Birck Nanotechnology Center October 2004 A Self-Aligned Process for High-Voltage, Short- Channel Vertical DMOSFETs in 4H-SiC Maherin Martin School of Electrical and Computer Engineering, Birck Nanotechnology Center, Purdue University Asmita Saha School of Electrical and Computer Engineering, Birck Nanotechnology Center, Purdue University James A. Cooper Jr. School of Electrical and Computer Engineering, Birck Nanotechnology Center, Purdue University, james.a.cooper.1@purdue.edu Follow this and additional works at: http://docs.lib.purdue.edu/nanopub Martin, Maherin; Saha, Asmita; and Cooper, James A. Jr., "A Self-Aligned Process for High-Voltage, Short-Channel Vertical DMOSFETs in 4H-SiC" (2004). Birck and NCN Publications. Paper 253. http://docs.lib.purdue.edu/nanopub/253 This document has been made available through Purdue e-pubs, a service of the Purdue University Libraries. Please contact epubs@purdue.edu for additional information.

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 51, NO. 10, OCTOBER 2004 1721 A Self-Aligned Process for High-Voltage, Short-Channel Vertical DMOSFETs in 4H-SiC Maherin Matin, Asmita Saha, and James A. Cooper, Jr., Fellow, IEEE Abstract In this paper, we describe a self-aligned process to produce short-channel vertical power DMOSFETs in 4H-SiC. By reducing the channel length to 0 5 m, the specific on-resistance of the MOSFET channel is proportionally reduced, significantly enhancing performance. Index Terms Counter-doping, DMOS, high-voltage MOSFET, nitric oxide (NO) anneal, self-aligned, short-channel, SiC. I. INTRODUCTION REDUCING specific on-resistance is of great importance for power MOSFETs in all SiC polytypes, but it is particularly desirable for 4H-SiC devices. 4H-SiC is the material of choice for high voltage power MOSFETs because of its high critical electric field ( MV/cm), wide bandgap ( ev), high bulk electron mobility ( cm /Vs), and minimal mobility anisotropy. However, 4H-SiC MOSFETs fabricated to date suffer from low inversion channel mobility, typically in the range of 5 10 cm /Vs using standard oxidation procedures [1], and 20 50 cm /Vs with a post-oxidation anneal in nitric oxide (NO) [1], [2]. In most 4H-SiC power MOSFETs reported to date, the resistance of the inversion channel is the dominant component of the total device on-resistance. The inversion channel resistance in MOSFETs is inversely proportional to channel mobility, but directly proportional to channel length. The channel length in SiC DMOSFETs is lithographically determined by the alignment tolerance between the base and source implant masks, and is typically in the range of 2 3 m using conventional optical lithography. If the channel length could be reduced to the order of 0.5 m, the channel resistance would be reduced by a factor of four to six. Moreover, this improvement would be obtained in addition to any improvements achieved by increasing the inversion channel mobility. Fig. 1 summarizes the performance of a number of SiC power MOSFETs reported to date, along with projected performance for DMOSFETs having 3 and 0.5 m channel lengths [3]. The specific on-resistance is the sum of resistances due to the source, channel, accumulation layer, JFET region, and drift region [4]. In these calculations, we assume an inversion channel mobility of 20 cm /Vs, a maximum oxide field of 4 MV/cm, and a cell pitch of 11 m (JFET region width m). Manuscript received January 27, 2004. This work was supported in part by the Office of Naval Research (ONR) under Grant N00014-01-1-0072 and in part by the Defense Advanced Research Projects Agency (DARPA) under Grant N00014-02-1-0628. The review of this paper was arranged by Editor M. A. Shibib. The authors are with the School of Electrical and Computer Engineering and also with the Birck Nanotechnology Center, Purdue University, West Lafayette, IN. Digital Object Identifier 10.1109/TED.2004.835622 Fig. 1. Overview of SiC MOSFET performance. Curved dashed lines are calculations for DMOSFETs with channel lengths of 3.0 and 0.5 m. Fig. 2. Schematic cross section of the short-channel DMOS cell. The right side contains JTE edge termination features. The calculated on-resistance is plotted at 70% of the ideal plane-junction blocking voltage, assuming that the breakdown voltage in a real device will be reduced by two-dimensional field crowding. A significant reduction in on-resistance is predicted for short-channel (0.5 m) DMOSFETs, especially for blocking voltages in the 600 1800 V range. In this paper, we describe a robust self-aligned process for producing short-channel DMOSFETs in 4H-SiC, and report the first short-channel (0.5 m) 4H-SiC power DMOSFETs. These devices exhibit record low specific on-resistances for blocking voltages in the range of 900 to 1000 V. II. DEVICE DESIGN A schematic cross section of the self-aligned DMOSFET is shown in Fig. 2. The fabrication of SiC DMOS (double 0018-9383/04$20.00 2004 IEEE

1722 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 51, NO. 10, OCTOBER 2004 Fig. 3. Simulated reverse currents for self-aligned DMOSFETs with channel lengths of 0.5 m and four different counter-doped doses. Note that all currents in this plot are well below those which would be expected under punch-through conditions. Fig. 4. Simulated reverse currents for self-aligned DMOSFETs with channel lengths of 0.3 m and three different counter-doped doses. Solid curves are for V =0and dashed curves are for V = 06 V. implanted) transistors requires a p-type base implantation and an n source implantation. The p-type base region usually has a retrograde profile [5], with lower doping near the surface to provide a low threshold voltage, and higher doping near the bottom junction to prevent punchthrough in the OFF-state. In the blocking mode, a punchthrough condition exists if the depletion region of the n-type drift layer reaches the n source, either from the side or from the bottom. To investigate punchthrough, MEDICI simulations are performed on a 20- m-thick, cm drift layer with channel lengths of 0.5 and 0.3 m. We assume a retrograde p-base doping profile with cm in the channel region and cm near the bottom junction. To reduce the threshold voltage, the surface of the p-base is also assumed to be counter-doped with nitrogen at a dose between and cm. Fig. 3 shows that the DMOSFET with a 0.5- m channel length does not punch through up to 70% of the theoretical plane-junction blocking voltage ( kv). Fig. 4 shows that a device with a channel length as short as 0.3 m will not punch through if the counter-doped dose is kept cm. For doses cm, the blocking capability can be increased with the application of a negative gate voltage (Fig. 4). A self-aligned source technique [3], [6] is used to obtain channel lengths m, as described in the next section. Recent studies of 4H-SiC MOSFETs on ion-implanted p-base regions show that significant improvements to inversion channel mobility are achieved by: 1) activating the p-type implants in a silane ambient to minimize surface roughness [7]; 2) performing a post-oxidation anneal in nitric oxide (NO) to reduce interface state density in the upper half of the bandgap [8]; and 3) counter-doping the channel with nitrogen [9]. All these features are incorporated in the fabrication process. Unlike previous devices [9], we exclude the counter-doped nitrogen implant from the JFET region to avoid increasing the oxide field in the blocking state. Single-zone junction termination extension (JTE) [10] is employed for edge termination. To Fig. 5. SEM image of one of the polysilicon fingers after RIE. The polysilicon mask is 6 m wide. reduce the cell pitch, we utilize a self-aligned source/base ohmic contact process with zero spacing between n and p contacts, as illustrated in Fig. 2. III. DEVICE FABRICATION Two 4H-SiC wafers are processed to fabricate the self-aligned short-channel DMOS transistors. The first wafer includes a 20- m n-type epilayer doped cm. The second wafer includes a 6- m n-type epilayer doped cm. The self-aligned process begins with the growth of a 40 nm sacrificial oxide, followed by low-pressure chemical vapor deposition (LPCVD) deposition of 1.5 m of polysilicon, which is further oxidized to produce 35 nm of sacrificial oxide. A 200-nm Ti Ni mask is formed by liftoff lithography and used to mask the reactive ion etching (RIE) of the polysilicon layer, which subsequently serves as the p-base implant mask. Fig. 5 shows an SEM image of one of the polysilicon fingers used to mask the p-base implant. The p-base regions are formed by implanting Al with a retrograde profile [5] having a surface concentration of cm. Next, a threshold adjust implant of N is performed at a dose of cm and energy of 30 kev. By introducing the counter-doped implant at the same time as the p-well implant, we exclude the n-type dopants from

MATIN et al.: SELF-ALIGNED PROCESS FOR HIGH-VOLTAGE, SHORT-CHANNEL VERTICAL DMOSFETs 1723 Fig. 6. SEM image of the oxidized polysilicon finger used as a self-aligned mask for the source implant. Fig. 8. Completed self-aligned short-channel DMOSFET. Fig. 7. DMOSFET after the n+ source implant. The light feature is a Ti Au mask to block n+ implants in areas where p+ contacts will subsequently be formed. the JFET region under the gate, where their presence would increase the oxide field in the blocking state. The resulting MOSFETs are normally off, with threshold voltages varying from 2 to 6 V. After the p-well and counter-doped implants, the polysilicon mask is oxidized to increase its width by 0.5 m per side, and this oxidized polysilicon mask defines the n source implant. The channel length is precisely determined by the thickness of the polysilicon oxidation. Fig. 6 shows an SEM image of the oxidized mask. A separate Ti Au ( nm) mask is used to block the source implant in areas outside the channel region where a p base contact implant will later be performed. The n source region is then implanted with a concentration of cm and a depth of 0.25 m. Fig. 7 shows a DMOSFET at this point. The metal mask, SiO layer, and polysilicon mask are removed, and p contacts and JTE terminations are implanted with Al. All implants are activated simultaneously at 1600 C for 40 min in an EPIGRESS VP-508 CVD reactor in a silane and argon atmosphere. The wafers are then RCA cleaned, and a 50-nm gate oxide is formed by pyrogenic oxidation at 1150 C. Following oxidation, the samples receive a post-oxidation anneal in NO at 1175 Cto reduce the interface state density [8]. A 0.5- m polysilicon layer is deposited by LPCVD and doped with phosphorus to form the gate electrode. P-type and n-type ohmic contacts are formed by 50-nm Al, -nm Ni, and 50-nm Ni, respectively. To minimize cell pitch, source and base contacts are abutted using a Ni-over-Al process, as shown in Fig. 2. The contacts are annealed at 850 C 900 C for 2 min in a vacuum. Fig. 8 shows a completed DMOSFET. Fig. 9. ON-state characteristics of a DMOSFET on a 20-m epilayer with L =8mand an area of 1:248 2 10 cm. R =27m1cm. Fig. 10. ON-state characteristics of a DMOSFET on a 20-m epilayer with L =6mand an area of 1:56 2 10 cm. R = of 33 m1cm. IV. EXPERIMENTAL RESULTS Figs. 9 and 10 show current voltage (I V) characteristics of two self-aligned DMOSFETs on the 20- m epilayer, fabricated

1724 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 51, NO. 10, OCTOBER 2004 Fig. 13. ON-state characteristics of a DMOSFET on a 6-m epilayer with L =6mand an area of 1:56 2 10 cm. R =16:9m1cm. Fig. 11. Blocking characteristics of the 1:248 2 10 cm and 1:56 2 10 cm DMOSFETs on the 20-m epilayer. Both measurements are performed with the devices immersed in Fluorinert. Fig. 14. OFF-state characteristics of the DMOSFET of Fig. 13, showing blocking voltage >900 V. Fig. 12. ON-state characteristics of a DMOSFET on a 6-m epilayer with L =4mand an area of 1:04 2 10 cm. R =9:95 m1cm. with 3 and 5- m feature sizes, respectively. The specific on-resistances are 27 m cm ( m, cell pitch m) and 33 m cm ( m, cell pitch m), respectively. The devices block up to 2000 V, as shown in Fig. 11. Figs. 12 and 13 show ON-state characteristics of self-aligned DMOSFETs on a 6- m epilayer, fabricated with 2 and 3 m minimum feature sizes and JFET widths of 4 and 6 m, respectively. For the device in Fig. 12, the specific on-resistance is 9.95 m cm. The MOSFET of Fig. 13 has an area of cm and a specific on-resistance of 16.9 m cm. The blocking voltage is around 900 V, as shown in Fig. 14. In all devices, the blocking voltage is determined by avalanche breakdown, and not by oxide breakdown. Fig. 15 shows a plot of measured specific on-resistance as a function of the JFET width for DMOSFETs on the 6- m epilayer, fabricated with 2- m feature sizes. The on-resistance decreases as the JFET width decreases, even though with smaller the JFET resistance increases. The decrease in on-resistance occurs mainly because the cell pitch is being reduced. However, there is an optimum value of below which the on-resistance dramatically increases due to increased JFET resistance. Fig. 15. Specific on-resistance of DMOSFETs on a 6-m epilayer as a function of JFET width. Fig. 16 shows measured on-resistance of DMOSFETs on the 6- m epilayer as a function of the gate voltage. As the gate voltage is decreased and approaches the threshold voltage, the channel resistance increases rapidly. The specific on-resistance becomes almost independent of gate voltage for V. Since the inversion channel resistance is inversely proportional to gate voltage minus threshold voltage, and therefore continues to decrease as gate voltage is increased, this is evidence that in the full-on condition the inversion channel resistance is no longer the dominant component of total device resistance. This is in marked contrast to conventional 4H-SiC DMOSFETs,

MATIN et al.: SELF-ALIGNED PROCESS FOR HIGH-VOLTAGE, SHORT-CHANNEL VERTICAL DMOSFETs 1725 [7] M. A. Capano, S. Ryu, J. A. Cooper Jr., M. R. Melloch, K. Rottner, S. Karlsson, N. Nordell, A. Powell, and D. E. Walker Jr., Surface roughening in ion implanted 4H-silicon carbide, J. Electron. Mater., vol. 28, pp. 214 218, 1999. [8] G. Y. Chung et al., Effect of nitric oxide annealing on the interface trap densitiies near the band edges in the 4H polytype of silicon carbide, Appl. Phys. Lett., vol. 76, p. 1713, 2000. [9] S.-H. Ryu et al., Large area (3.3 mm 2 3.3 mm) power MOSFETs in 4H-SiC, in Mater. Sci. Forum, vol. 389 393, 2002, pp. 1195 1198. [10] V. A. K. Temple, Junction termination extension (JTE), a new technique for increasing avalanche breakdown voltage and controlling surface electric fields in p-n junctions, IEDM Tech. Dig., pp. 423 426, 1977. Fig. 16. Specific on-resistance of DMOSFETs on a 6-m epilayer as a function of applied gate voltage. where the channel resistance typically dominates the on-resistance of the device, even at the highest allowable gate voltages. In the DMOSFETs on the 6- m epilayer, the source resistance is found to be the dominant component of the on-resistance. The source resistance is larger than expected in these devices due to misalignments in the minimum-size abutting source/base contacts shown in Fig. 2. This effect can be eliminated by minor changes to the source/base ohmic contact layout. V. CONCLUSION A novel self-aligned process was developed that allowed reliable fabrication of short-channel high voltage DMOSFETs in 4H-SiC. By reducing the channel length to m, we significantly reduced the resistance of the inversion channel so that it is no longer the dominant component of the specific on-resistance of the device. Fabricated DMOSFETs show low specific-on resistance of 9.95 m cm. Maherin Matin received the B.S.E.E. and M.S.E.E. degrees from Bangladesh University of Engineering and Technology, Dhaka, Bangladesh, in 1994 and 1995, respectively. Her thesis focused on the study of quantum mechanical effects on MOS capacitors. She received the M.S.E.E. and Ph.D. degrees from the School of Electrical and Computer Engineering, West Lafayette, IN, in 1997 and 2002, respectively, both focusing on the design, fabrication, characterization, and development of DMOS devices on the 4H-SiC material. She is currently with the Birck Nanotechnology Center, Purdue University. She has three patents pending on the fabrication of short-channel self-aligned counter-doped DMOS transistors. Asmita Saha received the B.E. degree in electronics and telecommunication engineering from Jadavpur University, Jadavpur, India, in 1997, and the M.Tech. degree in electronics and electrical communication engineering from Indian Institute of Technology, Kharagpur, India. She is currently pursuing the Ph.D. degree in the School of Electrical and Computer Engineering, Birck Nanotechnology Center, Purdue University, West Lafayette, IN. She was a Lecturer in the Electronics Department, Jadavpur University, from 1999 to 2001. Currently, she is with the Birck Nanotechnology Center, Purdue University, working on short-channel SiC power DMOSFETs. ACKNOWLEDGMENT The authors would like to thank Prof. J. R. Williams, Auburn University, for the NO post-oxidation annealing, and Prof. M. A. Capano, Purdue University, for the Silane ambient implant annealing. REFERENCES [1] C.-Y. Lu, J. A. Cooper Jr., T. Tsuji, G. Y. Chung, J. R. Williams, K. McDonald, and L. C. Feldman, Effect of process variations and ambient temperature on electron mobility at the SiO /4H-SiC interface, IEEE Trans. Electron Devices, vol. 50, pp. 1582 1588, July 2003. [2] G. Y. Chung et al., Improved inversion channel mobility for 4H-SiC MOSFETs following high temperature anneals in nitric oxide, IEEE Electron Device Lett., vol. 22, pp. 176 178, Feb. 2001. [3] M. Matin, A. Saha, and J. A. Cooper Jr., Self-aligned short-channel vertical power DMOSFETs in 4H-SiC, in Mater. Sci. Forum, vol. 457 460, 2004, pp. 1393 1396. [4] S. C. Sun and J. D. Plummer, Modeling of the on-resistance of LDMOS, VDMOS, and VMOS power transistors, IEEE Trans. Electron Devices, vol. 27, p. 356, 1980. [5] J. N. Shenoy, J. A. Cooper Jr., and M. R. Melloch, High-voltage double implanted power MOSFETs in 6H-SiC, IEEE Electron Device Lett., vol. 18, pp. 93 95, Jan. 1997. [6] K. Ueno, Method for manufacturing silicon carbide MDS semiconductor device including utilizing difference in mask edges in implanting, U.S. Patent 6 238 980, May 29, 2001. James A. Cooper, Jr. (F 93) received the B.S.E.E. degree from Mississippi State University, Mississippi State, Miss., in 1968, the M.S.E.E. degree from Stanford University, Stanford, CA, in 1969, and the Ph.D.degree from Purdue University, West Lafayette, IN, in 1973. From 1973 to 1983, he was Member of Technical Staff, Bell Laboratories, Murray Hill, NJ. While at Bell Labs, he served as principal designer of AT&T s first microprocessor, and developed a time-of-flight technique for measuring the high-field drift velocity of electrons in inversion layers on silicon. In 1983 he became a Professor of electrical engineering at Purdue, where he was the founding Director of the Purdue Optoelectronics Research Center. He is currently the Charles William Harrison Professor of Electrical and Computer Engineering at Purdue University. He has coauthored more than 250 technical papers and conference presentations (18 invited), five book chapters, and holds 13 U.S. patents. Since joining Purdue, he has been principal investigator of over $25 million in sponsored research contracts, and he was recently named Co-Director of the Birck Nanotechnology Center, a $58 million research facility being constructed in Purdue s Discovery Park. During the 1980s, he focused on GaAs devices, but since 1990 he has worked almost exclusively on SiC. His Purdue group is responsible for a number of advances in SiC devices, including the first SiC nonvolatile memories, the first monolithic digital integrated circuits, the first charge-coupled devices, the first DMOS power transistors, and the first SiC IMPATT microwave diodes. Dr. Cooper served as an Associate Editor of the IEEE TRANSACTIONS ON ELECTRON DEVICES from 1983 through 1986. He was Guest Editor of the 1999 Special Issue of the IEEE TRANSACTIONS ON ELECTRON DEVICES on SiC device technology.