Some parametric limits are subject to change. MITSUBISHI SEMICONDUCTOR <pplicati Specific Specific Intelligent Power Power Module> PS1117 PS1117 TYPE TYPE PS1117 INTEGRTED FUNCTIONS ND FETURES 3-phase IGBT inverter bridge cfigured by the latest 3rd. generati IGBT and diode technologies. Circuit for dynamic braking of motor regenerative energy. Inverter output current capability IO (Note 1): Type Name 1% load 15% over load PS1117 17. (rms) 25.5 (rms), 1min (Note 1) : The inverter output current is assumed to be sinusoidal and the peak current value of each of the above loading cases is defined as : IOP = IO 2 INTEGRTED DRIE, PROTECTION ND SYSTEM CONTROL FUNCTIONS: For P-Side IGBTs : Drive circuit, High voltage isolated high-speed level shifting, Short-circuit protecti (SC), Bootstrap circuit supply scheme (Single drive-power-supply) and Under voltage protecti (U). For N-Side IGBTs : Drive circuit, Short circuit protecti (SC), Ctrol-supply Under voltage and Over voltage protecti (O/U), System Over-temperature protecti (OT), Fault output (FO) signaling circuit, and Current-Limit warning signal output (CL) For Brake circuit IGBT : Drive circuit Warning and Fault signaling : FO1 : Short circuit protecti for lower-leg IGBTs and Input interlocking against spurious arm shoot-through. FO2 : N-side ctrol supply abnormality locking (O/U) FO3 : System over-temperature protecti (OT). CL : Warning for inverter current overload cditi For system feedback ctrol : nalogue signal feedback reproducing actual inverter phase current (3φ). Input Interface : 5 CMOS/TTL compatible, Schmitt trigger input, and rm-shoot-through interlock protecti. PPLICTION coustic noise-less 3.7kW/C2 class 3 phase inverter and other motor ctrol applicatis. PCKGE OUTLINES 76 ± 1 5 41 ±.5 1 32 15.5 5 15.5 5 1 5 1 7 23 2 ±.3.5 6 ±.3 12.7 ±.3 15 ±.5 115 ± 1 96 56 ±.8 15.5 4-φ4.5 2.4 ± 1 MOUNTING HOLE (12) 1 (22).5 63.5 ±.8 17.5 3 4-φ5 31 36 2.5 6 ±.5 4-R2 1 ±.3 63 ±.8 4-R5 4-φ3.2 3 17 ±.8 Terminals ssignment: 1 CBU+ 2 CBU 3 CB+ 4 CB 5 CBW+ 6 CBW 7 GND 8 NC 9 DH 1 CL 11 FO1 12 FO2 13 FO3 14 CU 15 C 16 CW 17 UP 18 P 19 WP 2 UN 21 N 22 WN 23 Br 31 P 32 Br 33 N 34 U 35 36 W LBEL 8.5 13 (Fig. 1) May 21
PS1117 INTERNL FUNCTIONS BLOCK DIGRM pplicati Specific Intelligent Power Module CBU CBU+ CB CB+ CBW CBW+ Brake resistor cnecti, Inrush preventi circuit, etc. P B Protecti Circuit Drive Circuit Level shifter C 2 line input R S T U W M Z C N T S C 2 line output Z : Surge absorber. C : C filter (Ceramic cdenser 2.2~6.5nF) [Note : dditially an appropriate Line-to line surge absorber circuit may become necessary depending the applicati envirment]. Current sensing circuit Input signal cditiing Drive Circuit Fo Logic Protecti circuit Ctrol supply fault sense CU C CW nalogue signal output correspding to each phase current (5 line) Note 1) UP P WP UN N WN Br PWM input (5 line) Note 2) CL, FO1, FO2, FO3 Fault output (5 line) Note 3) Note 1) To prevent chances of signal oscillati, a series resistor (1kΩ) coupling at each output is recommended. Note 2) By virtue of integrating an photo-coupler inside the module, direct coupling to CPU, without any external opto or transformer isolati is possible. Note 3) ll outputs are open collector type. Each signal line should be pulled up to plus side of the 5 power supply with approximately 5.1kΩ resistance. Note 4) The wiring between power DC link capacitor and P/N terminals should be as short as possible to protect the SIPM against catastrophic high surge voltage. For extra precauti, a small film snubber capacitor (.1~.22µF, high voltage type) is recommended to be mounted close to these P and N DC power input pins. GND DH (Fig. 2) MXIMUM RTINGS (Tj = 25) INERTER PRT (Including Brake Part) Symbol Item Cditi CC Supply voltage pplied between P-N CC(surge) Supply voltage (surge) pplied between P-N, Surge-value P or N Each output IGBT collector-emitter static voltage pplied between P-U,, W, Br or U,, W, Br-N P(S) or N(S) Each output IGBT collector-emitter pplied between P-U,, W, Br or U,, W, switching surge voltage Br-N ±IC(±ICP) IC(ICP) IF(IFP) Each output IGBT collector current Brake IGBT collector current Brake diode anode current TC = 25 Note: ( ) means IC peak value 45 5 6 6 ±5 (±1) 15 (3) 15 (3) CONTROL PRT Symbol Item DH, DB CIN FO IFO CL ICL ICO Supply voltage Input signal voltage Fault output supply voltage Fault output current Current-limit warning (CL) output voltage CL output current nalogue current signal output current Cditi pplied between DH-GND, CBU+-CBU, CB+-CB, CBW+-CBW pplied between UP P WP UN N WN Br-GND pplied between FO1 FO2 FO3-GND Sink current of FO1 FO2 FO3 pplied between CL-GND Sink current of CL Sink current of CU C CW 2.5 ~ 7.5.5 ~ 7 15.5 ~ 7 15 ±1 May 21
PS1117 TOTL SYSTEM Symbol Item Cditi Tj Juncti temperature (Note 2) 2 ~ +125 Tstg TC iso Storage temperature Module case operating temperature Isolati voltage Mounting torque (Fig. 3) 6 Hz sinusoidal C applied between all terminals and the base plate for 1 minute. Mounting screw: M4. 4 ~ +125 2 ~ +1 25.98 ~ 1.47 Note 2) The item defines the maximum juncti temperature for the power elements (IGBT/Diode) of the SIPM to ensure safe operati. However, these power elements can endure instantaneous juncti temperature as high as 15 instantaneously. To make use of this additial temperature allowance, a detailed study of the exact applicati cditis is required and, accordingly, necessary informati is requested to be provided before use. CSE TEMPERTURE MESUREMENT POINT (3mm from the base surface) rms N m LBEL Tc (Fig. 3) THERML RESISTNCE Symbol Rth(j-c)Q Rth(j-c)F Rth(j-c)Q Rth(j-c)F Rth(c-f) Item Juncti to case Thermal Resistance Ctact Thermal Resistance Cditi Inverter IGBT (1/6) Inverter FWDi (1/6) Brake IGBT Brake FWDi Case to fin, thermal grease applied Min. Typ. Max. 1.75 2.4 4.5.31 ELECTRICL CHRCTERISTICS (Tj = 25, DH = 15, DB = 15 unless otherwise noted) Symbol CE(sat) EC CE(sat)Br FBr t tc() toff tc(off) trr IDH th() th(off) Ri Item Cditi Min. Collector-emitter saturati voltage DH = DB = 15, Input = ON, Tj = 25, Ic = 5 FWDi forward voltage Tj = 25, Ic = 5, Input = OFF Brake IGBT Collector-emitter saturati voltage DH = 15, Input = ON, Tj = 25, Ic = 15 Brake diode forward voltage Tj = 25, IF = 15, Input = OFF 1/2 Bridge inductive, Input = ON.4 Switching times CC = 3, Ic = 5, Tj = 125 DH = 15, DB = 15 Note : t, toff include delay time of the internal ctrol FWD reverse recovery time circuit Short circuit endurance CC 4, Input = ON (e-shot) (Output, rm, and Load, Tj = 125 start Short Circuit Modes) 13.5 DH = DB 16.5 CC 4, Tj 125, Switching SO Ic < IOL(CL) operati level, Input = ON, 13.5 DH = DB 16.5 Circuit current Input threshold voltage Input off threshold voltage Input pull-up resister DH = 15, CIN = 5 Integrated between input terminal-dh.8 2.5 Typ..8.4 1.5.6.15 Max. No destructi FO output by protecti operati No destructi No protecting operati No FO output 1.4 3. 15 3.5 2. 1. 2.4 1.3 15 2. 4. kω May 21
PS1117 ELECTRICL CHRCTERISTICS (Tj = 25, DH = 15, DB = 15 unless otherwise noted) Symbol Item Cditi Min. Typ. Max. fpwm txx PWM input frequency llowable input -pulse width TC 1, Tj 125 DH = 15, TC = 2 ~ +1 (Note 3) 1 15 5 tdead llowable input signal dead time for Relates to correspding inputs, blocking arm shoot-through (Except brake part), TC = 2 ~ +1 2.5 tint Input inter-lock sensing Relates to correspding input (Except break part) 65 1 CO C+(2%) C (2%) nalogue signal linearity with output current Ic = Ic = IOP(2%) Ic = IOP(2%) DH = 15 TC = 2 ~ 1 (Fig. 4) 1.87.77 7 2.27 1.17 3.37 2.57 1.47 3.67 CO Offset change area vs temperature DH = 15, TC = 2 ~ 1 15 C+ Ic > IOP(2%), DH = 15.7 nalogue signal output voltage limit C (Fig. 4) 4. C(2%) nalogue signal over all linear variati CO-C±(2%) 1.1 rch nalogue signal data hold accuracy Correspd to max. 5 data hold period ly, Ic = IOP(2%) (Fig. 5) 5 5 td(read) nalogue signal reading time fter input signal trigger point (Fig. 8) 3 ICL(H) Signal output current of Idle 1 Open collector output ICL(L) CL operati ctive 1 ±IOL CL warning operati level D = 15, TC = 2 ~ 1 (Note 4) 48.2 6. 72. SC Short circuit over current trip level Tj = 25 (Fig. 7) (Note 5) 79.2 12 OT Over temperature Trip level 1 11 12 DH = 15 OTr protecti 9 UDH UDHr ODH Trip level Trip level 11.5 11.55 18. 12. 12.5 19.2 12.75 13.25 2.15 ODHr Supply circuit under & TC = 2 ~ +1, 16.5 17.5 18.65 over voltage protecti Tj 125 UDB Trip level 1. 11. 12. UDBr td Filter time 1.5 11.5 1 12.5 IFO(H) Idle 1 Fault output current Open collector output IFO(L) ctive 1 (Note 3) : (a) llowable minimum input -pulse width : This item applies to P-side circuit ly. (b) llowable maximum input -pulse width : This item applies to both P-side and N-side circuits excluding the brake circuit. (Note4) : CL output : The "current limit warning (CL) operati circuit outputs warning signal whenever the arm current exceeds this limit. The circuit is reset automatically by the next input signal and thus, it operates a pulse-by-pulse scheme. (Note5) : The short circuit protecti works instantaneously when a high short circuit current flows through an internal IGBT rising up momentarily. The protecti functi is, thus meant primarily to protect the SIPM against short circuit distracti. Therefore, this functi is not recommended to be used for any system load current regulati or any over load ctrol as this might, cause a failure due to excessive temperature rise. Instead, the analogue current output feature or the over load warning feature (CL) should be appropriately used for such current regulati or over load ctrol operati. In other words, the PWM signals to the SIPM should be shut down, in principle, and not to be restarted before the juncti temperature would recover to normal, as so as a fault is feed back from its FO1 pin of the SIPM indicating a short circuit situati. khz ns m % µ µ RECOMMENDED CONDITIONS Symbol Item Cditi CC Supply voltage pplied across P-N terminals 4 (max.) DH, DB Ctrol Supply voltage pplied between DH-GND, CBU+-CBU, CB+-CB, CBW+-CBW 15±1.5 DH, DB CIN() CIN(off) fpwm tdead Supply voltage ripple Input voltage Input off voltage PWM Input frequency rm shoot-through blocking time Using applicati circuit Using applicati circuit ±1 (max.) ~.3 4.8 ~ 5. 2 ~ 15 2.5 (min.) / khz May 21
PS1117 Fig. 4 OUTPUT CURRENT NLOGUE SIG- NLING LINERITY Fig. 5 OUTPUT CURRENT NLOGUE SIGNLING DT HOLD DEFINITION 5 C C 4 min max C (2%) DH=15 TC= 2~1 C 5 3 C CH(5) CH(55) C() 2 C+(2%) rch= CH(55)-CH(5) CH(5) 1 4 3 2 1 nalogue output signal data hold range 1 2 3 4 C+ Note ; Ringing happens around the point where the signal output voltage changes state from analogue to data hold due to test circuit arrangement and instrumentatial trouble. Therefore, the rate of change is measured at a 5 delayed point. Real load current peak value.(%)(ic=io 2) (Fig. 4) Fig. 6 INPUT INTERLOCK OPERTION TIMING CHRT Input signal CIN(p) of each phase upper arm Input signal CIN(n) of each phase lower arm Gate signal o(p) of each phase upper arm (SIPM internal) Gate signal o(n) of each phase upper arm (SIPM internal) Error output FO1 Note : Input interlock protecti circuit ; It is operated when the input signals for any upper-arm / lower-arm pair of a phase are simultaneously in LOW level. By this interlocking, both upper and lower IGBTs of this mal-triggered phase are cut off, and FO signal is outputted. fter an input interlock operati the circuit is latched. The FO is reset by the high-to-low going edge of either an upper-leg, or a lower-leg input, whichever comes in later. Fig. 7 TIMING CHRT ND SHORT CIRCUIT PROTECTION OPERTION Input signal CIN of each phase upper arm Short circuit sensing signal S Gate signal o of each phase upper arm(sipm internal) SC delay time Error output FO1 Note : Short circuit protecti operati. The protecti operates with FO flag and reset a pulse-by-pulse scheme. The protecti by gate shutdown is given ly to the IGBT that senses an overload (excluding the IGBT for the Brake ). May 21
PS1117 Fig. 8 INERTER OUTPUT NLOGUE CURRENT SENSING ND SIGNLING TIMING CHRT CIN (hold) off off N-side IGBT Current N-side FWDi Current IC (S) +ICL ICL C CL Ref off t(hold) Delay time td(read) Fig. 9 STRT-UP SEQUENCE Normally at start-up, Fo and CL output signals will be pulled-up High to Supply voltage (OFF level); however, FO1 output may fall to Low (ON) level at the instant of the first ON input pulse to an N-Side IGBT. This can happen particularly when the boot-strap capacitor is of large size. FO1 resetting sequence (together with the boot-strap charging sequence) is explained in the following graph DC-Bus voltage Ctrol voltage supply Boot-strap voltage N-Side input signal PN DH DB CIN(N) PWM starts a) b) Fig. 1 RECOMMENDED I/O INTERFCE CIRCUIT CPU 5.1kΩ R.1nF 5 1kΩ R.1nF UP,P,WP,UN,N,WN,Br F1,F2,F3,CL CU,C,CW GND(Logic) SIPM P-Side input signal CIN(P) Brake input signal FO1 output signal CIN(Br) FOI a) Boot-strap charging scheme : pply a train of short ON pulses at all N-IGBT input pins for adequate charging (pulse width = approx. 2 number of pulses =1 ~ 5 depending the boot-strap capacitor size) b) FO1 resetting sequence: pply ON signals to the following input pins : Br Un/n/Wn Up/p/Wp in that order. May 21