PD 97357 Applications l DC Motor Drive l High Efficiency Synchronous Rectification in SMPS l Uninterruptible Power Supply l High Speed Power Switching l Hard Switched and High Frequency Circuits G D S HEXFET Power MOSFET V DSS 60V R DS(on) typ..9mω max. 2.4mΩ I D (Silicon Limited) 270Ac I D (Package Limited) 95A Benefits l Optimized for Logic Level Drive l Very Low R DS(ON) at 4.5V V GS l Superior R*Q at 4.5V V GS l Improved Gate, Avalanche and Dynamic dv/dt Ruggedness l Fully Characterized Capacitance and Avalanche SOA l Enhanced body diode dv/dt and di/dt Capability l LeadFree TO220AB G D S Gate Drain Source Absolute Maximum Ratings Symbol Parameter Max. Units I D @ T C = 25 C Continuous Drain Current, V GS @ V (Silicon Limited) 270c I D @ T C = C Continuous Drain Current, V GS @ V (Silicon Limited) 90c I D @ T C = 25 C Continuous Drain Current, V GS @ V (Package Limited) 95 A I DM Pulsed Drain Current d P D @T C = 25 C Maximum Power Dissipation 380 W Linear Derating Factor 2.5 W/ C V GS GatetoSource Voltage ±6 V dv/dt Peak Diode Recovery f 8.0 V/ns T J Operating Junction and T STG Storage Temperature Range 55 to 75 Soldering Temperature, for seconds (.6mm from case) C Mounting torque, 632 or M3 screw lbxin (.Nxm) Avalanche Characteristics E AS (Thermally limited) Single Pulse Avalanche Energy e 290 mj I AR Avalanche Current d A See Fig. 4, 5, 22a, 22b E AR Repetitive Avalanche Energy g mj Thermal Resistance Symbol Parameter Typ. Max. Units R θjc JunctiontoCase k 0.40 R θcs CasetoSink, Flat, Greased Surface 0.50 R θja JunctiontoAmbient (PCB Mount) jk 62 www.irf.com C/W 2/08/08
Static @ (unless otherwise specified) Symbol Parameter Min. Typ. Max. Units Conditions V (BR)DSS DraintoSource Breakdown Voltage 60 V V GS = 0V, I D = 250µA V (BR)DSS / T J Breakdown Voltage Temp. Coefficient 0.06 V/ C Reference to 25 C, I D = 5mAd R DS(on) Static DraintoSource OnResistance.9 2.4 V GS = V, I D = 65A g mω 2.2 2.8 V GS = 4.5V, I D = 40A g V GS(th) Gate Threshold Voltage.0 2.5 V I DSS I GSS DraintoSource Leakage Current GatetoSource Forward Leakage 20 GatetoSource Reverse Leakage 250 µa na R G(int) Internal Gate Resistance 2.0 Ω V DS = V GS, I D = 250µA V DS = 60V, V GS = 0V V DS = 60V, V GS = 0V, V GS = 6V V GS = 6V Dynamic @ (unless otherwise specified) Symbol Parameter Min. Typ. Max. Units Conditions gfs Forward Transconductance 340 S V DS = V, I D = 65A Q g Total Gate Charge 9 40 I D = 65A Q gs GatetoSource Charge 3 Q gd GatetoDrain ("Miller") Charge 5 Q sync Total Gate Charge Sync. (Q g Q gd ) 40 t d(on) TurnOn Delay Time 66 t r Rise Time 220 t d(off) TurnOff Delay Time t f Fall Time C iss Input Capacitance 2 C oss Output Capacitance 20 C rss Reverse Transfer Capacitance 500 C oss eff. (ER) Effective Output Capacitance (Energy Related)i 430 C oss eff. (TR) Effective Output Capacitance (Time Related) h 880 Diode Characteristics Symbol Parameter Min. Typ. Max. Units V DS = 30V V GS = 4.5V g I D = 65A, V DS =0V, V GS = 4.5V V DD = 39V I D = 65A R G = 2.Ω V GS = 4.5V g V GS = 0V V DS = 50V ƒ =.0MHz V GS = 0V, V DS = 0V to 48V i V GS = 0V, V DS = 0V to 48V h Conditions I S Continuous Source Current MOSFET symbol D 270 (Body Diode) showing the A G I SM Pulsed Source Current integral reverse S (Body Diode)e pn junction diode. V SD Diode Forward Voltage.3 V, I S = 65A, V GS = 0V g t rr Reverse Recovery Time 62 V R = 5V, ns 66 I F = 65A Q rr Reverse Recovery Charge 3 di/dt = A/µs g nc 360 I RRM Reverse Recovery Current 4.4 A t on Forward TurnOn Time Intrinsic turnon time is negligible (turnon is dominated by LSLD) nc ns pf Notes: Calcuted continuous current based on maximum allowable junction temperature Bond wire current limit is 95A. Note that current limitation arising from heating of the device leds may occur with some lead mounting arrangements. Repetitive rating; pulse width limited by max. junction temperature. ƒ Limited by T Jmax, starting, L = 0.02mH R G = 25Ω, I AS = 65A, V GS =V. Part not recommended for use above this value. I SD 65A, di/dt 430A/µs, V DD V (BR)DSS, T J 75 C. Pulse width 400µs; duty cycle 2%. C oss eff. (TR) is a fixed capacitance that gives the same charging time as C oss while V DS is rising from 0 to 80% V DSS. C oss eff. (ER) is a fixed capacitance that gives the same energy as C oss while V DS is rising from 0 to 80% V DSS. ˆ When mounted on " square PCB (FR4 or G Material). For recommended footprint and soldering techniquea refer to applocation note # AN 994 echniques refer to application note #AN994. R θ is measured at T J approximately 90 C. 2 www.irf.com
C, Capacitance (pf) V GS, GatetoSource Voltage (V) I D, DraintoSource Current (A) R DS(on), DraintoSource On Resistance (Normalized) I D, DraintoSource Current (A) I D, DraintoSource Current (A) 0 VGS TOP 5V V 4.5V 4.0V 3.5V 3.3V 3.0V BOTTOM 2.7V 0 VGS TOP 5V V 4.5V 4.0V 3.5V 3.3V 3.0V BOTTOM 2.7V 2.7V 60µs PULSE WIDTH Tj = 25 C 0. 0. 0 V DS, DraintoSource Voltage (V) 2.7V 60µs PULSE WIDTH Tj = 75 C 0. 0 V DS, DraintoSource Voltage (V) Fig. Typical Output Characteristics Fig 2. Typical Output Characteristics 0 2.5 I D = 65A V GS = V T J = 75 C 2.0.5.0 V DS = 25V 60µs PULSE WIDTH 0. 2 3 4 5 6 V GS, GatetoSource Voltage (V) Fig 3. Typical Transfer Characteristics 0.5 60 40 20 0 20 40 60 80 20406080 T J, Junction Temperature ( C) Fig 4. Normalized OnResistance vs. Temperature 000 V GS = 0V, f = MHZ C iss = C gs C gd, C ds SHORTED C rss = C gd C oss = C ds C gd 5.0 4.0 I D = 65A V DS = 48V V DS = 30V 00 C iss 3.0 C oss 0 C rss 2.0.0 0.0 0 20 40 60 80 20 V DS, DraintoSource Voltage (V) Q G, Total Gate Charge (nc) Fig 5. Typical Capacitance vs. DraintoSource Voltage Fig 6. Typical Gate Charge vs. GatetoSource Voltage www.irf.com 3
Energy (µj) E AS, Single Pulse Avalanche Energy (mj) V (BR)DSS, I D, Drain Current (A) DraintoSource Breakdown Voltage (V) I SD, Reverse Drain Current (A) I D, DraintoSource Current (A) 0 T J = 75 C 00 0 OPERATION IN THIS AREA LIMITED BY R DS (on) µsec Limited by package msec V GS = 0V 0. 0.0 0.5.0.5 2.0 2.5 Tc = 25 C Tj = 75 C Single Pulse msec DC 0 V SD, SourcetoDrain Voltage (V) Fig 7. Typical SourceDrain Diode Forward Voltage V DS, DraintoSource Voltage (V) Fig 8. Maximum Safe Operating Area 75 Id = 5mA 250 Limited By Package 70 50 65 60 50 0 25 50 75 25 50 75 T C, Case Temperature ( C) Fig 9. Maximum Drain Current vs. Case Temperature 3.0 2.5 2.0 55 60 40 20 0 20 40 60 80 20406080 T J, Temperature ( C ) 0 800 Fig. DraintoSource Breakdown Voltage I D TOP 27A 50A BOTTOM 65A.5 600.0 400 0.5 0.0 0 20 30 40 50 60 70 V DS, DraintoSource Voltage (V) 0 25 50 75 25 50 75 Starting T J, Junction Temperature ( C) Fig. Typical C OSS Stored Energy Fig 2. Maximum Avalanche Energy vs. DrainCurrent 4 www.irf.com
E AR, Avalanche Energy (mj) Avalanche Current (A) D = 0.50 0. 0.20 Thermal Response ( Z thjc ) C/W 0.0 0. 0.05 0.02 0.0 SINGLE PULSE ( THERMAL RESPONSE ) R R R 2 R 2 R 3 R 3 τ J τ J τ τ τ 2 τ 2 τ 3 τ 3 Ci= τi/ri Ci i Ri R 4 Ri ( C/W) τi (sec) R 4 0.05 0.000009 Notes:. Duty Factor D = t/t2 2. Peak Tj = P dm x Zthjc Tc 0.00 E006 E005 0.000 0.00 0.0 0. t, Rectangular Pulse Duration (sec) Fig 3. Maximum Effective Transient Thermal Impedance, JunctiontoCase τ 4 τ 4 τ C τ 0.08360 0.000080 0.8950 0.00295 0.59 0.006726 0 Duty Cycle = Single Pulse 0.0 Allowed avalanche Current vs avalanche pulsewidth, tav, assuming Tj = 50 C and Tstart =25 C (Single Pulse) 0.05 0. Allowed avalanche Current vs avalanche pulsewidth, tav, assuming Τ j = 25 C and Tstart = 50 C..0E06.0E05.0E04.0E03.0E02.0E0 tav (sec) Fig 4. Typical Avalanche Current vs.pulsewidth 250 50 50 TOP Single Pulse BOTTOM.0% Duty Cycle I D = 65A Notes on Repetitive Avalanche Curves, Figures 4, 5: (For further info, see AN5 at www.irf.com). Avalanche failures assumption: Purely a thermal phenomenon and failure occurs at a temperature far in excess of T jmax. This is validated for every part type. 2. Safe operation in Avalanche is allowed as long ast jmax is not exceeded. 3. Equation below based on circuit and waveforms shown in Figures 6a, 6b. 4. P D (ave) = Average power dissipation per single avalanche pulse. 5. BV = Rated breakdown voltage (.3 factor accounts for voltage increase during avalanche). 6. I av = Allowable avalanche current. 7. T = Allowable rise in junction temperature, not to exceed T jmax (assumed as 25 C in Figure 4, 5). t av = Average time in avalanche. D = Duty cycle in avalanche = t av f Z thjc (D, t av ) = Transient thermal resistance, see Figures 3) 0 25 50 75 25 50 75 Starting T J, Junction Temperature ( C) Fig 5. Maximum Avalanche Energy vs. Temperature P D (ave) = /2 (.3 BV I av ) = DT/ Z thjc I av = 2DT/ [.3 BV Z th ] E AS (AR) = P D (ave) t av www.irf.com 5
Q RR (A) I RRM (A) Q RR (A) V GS(th), Gate threshold Voltage (V) I RRM (A) 3.0 4 I F = A 2.5 2 V R = 5V 2.0.5 I D = 250µA I D =.0mA I D =.0A 8 6.0 4 0.5 75 50 25 0 25 50 75 25 50 75 T J, Temperature ( C ) Fig 6. Threshold Voltage vs. Temperature 2 0 400 500 di F /dt (A/µs) Fig. 7 Typical Recovery Current vs. di f /dt 2 8 I F = 65A V R = 5V 900 800 700 600 I F = A V R = 5V 500 6 400 4 2 0 400 500 di F /dt (A/µs) Fig. 8 Typical Recovery Current vs. di f /dt 0 400 500 di F /dt (A/µs) Fig. 9 Typical Stored Charge vs. di f /dt 600 500 I F = 65A V R = 5V 400 0 400 500 di F /dt (A/µs) Fig. 20 Typical Stored Charge vs. di f /dt 6 www.irf.com
D.U.T ƒ Circuit Layout Considerations Low Stray Inductance Ground Plane Low Leakage Inductance Current Transformer Reverse Recovery Current Driver Gate Drive Period P.W. D.U.T. I SD Waveform Body Diode Forward Current di/dt D.U.T. V DS Waveform Diode Recovery dv/dt D = P.W. Period V GS =V V DD * R G dv/dt controlled by RG Driver same type as D.U.T. I SD controlled by Duty Factor "D" D.U.T. Device Under Test V DD ReApplied Voltage Body Diode Inductor Curent Current Forward Drop Ripple 5% I SD * V GS = 5V for Logic Level Devices Fig 2. Peak Diode Recovery dv/dt Test Circuit for NChannel HEXFET Power MOSFETs 5V tp V (BR)DSS V DS L DRIVER R G 20V V GS tp D.U.T IAS 0.0Ω V DD A I AS Fig 22a. Unclamped Inductive Test Circuit Fig 22b. Unclamped Inductive Waveforms V DS R D V DS V GS D.U.T. 90% R G V DD VV GS Pulse Width µs Duty Factor 0. % % V GS t d(on) t r t d(off) t f Fig 23a. Switching Time Test Circuit Fig 23b. Switching Time Waveforms Current Regulator Same Type as D.U.T. Vds Id 50KΩ Vgs 2V.2µF.3µF V GS D.U.T. V DS Vgs(th) 3mA I G I D Current Sampling Resistors Qgs Qgs2 Qgd Qgodr Fig 24a. Gate Charge Test Circuit Fig 24b. Gate Charge Waveform www.irf.com 7
TO220AB Package Outline Dimensions are shown in millimeters (inches) TO220AB Part Marking Information (;$03/( 7,6,6$,5) /27&2'( $66(0%/('2::,7($66(0%/</,(& RWH3LQDVVHPEO\OLQHSRVLWLRQ LQGLFDWHV/HDG)UHH,7(5$7,2$/ 5(&7,),(5 /2*2 $66(0%/< /27&2'( 3$5780%(5 '$7(&2'( <($5 :((. /,(& TO220AB packages are not recommended for Surface Mount Application. Note: For the most current drawing please refer to IR website at http://www.irf.com/package/ Data and specifications subject to change without notice. This product has been designed and qualified for the Industrial market. Qualification Standards can be found on IR s Web site. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (3) 25275 TAC Fax: (3) 2527903 Visit us at www.irf.com for sales contact information. 2/8 8 www.irf.com